From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thierry Reding Subject: Re: [PATCH 2/3] arm64: tegra: Enable DFLL support on Jetson Nano Date: Tue, 14 Jul 2020 11:18:49 +0200 Message-ID: <20200714091849.GD141356@ulmo> References: <20200712102506.23686-1-jonathanh@nvidia.com> <20200712102506.23686-3-jonathanh@nvidia.com> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="RhUH2Ysw6aD5utA4" Return-path: Content-Disposition: inline In-Reply-To: <20200712102506.23686-3-jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jon Hunter Cc: Rob Herring , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org --RhUH2Ysw6aD5utA4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Jul 12, 2020 at 11:25:05AM +0100, Jon Hunter wrote: > Populate the DFLL node and corresponding PWM pin nodes in order to > enable CPUFREQ support on the Jetson Nano platform. >=20 > Signed-off-by: Jon Hunter > --- > .../boot/dts/nvidia/tegra210-p3450-0000.dts | 37 +++++++++++++++++++ > 1 file changed, 37 insertions(+) Applied, thanks. Thierry --RhUH2Ysw6aD5utA4 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl8NeHgACgkQ3SOs138+ s6GTrBAAveQYfikelPWoSGyB7pOtruDvFpIQ5mth2Gq+WsQcCiH2Wd4PEW3qucj4 787DGzApuSlKpD8g6lP0RlUqFkSD0Diye9l1sNUodUranfc0VoM5bf8ctUcPnTiP E2WETtWnzZXhP/Lsn/Bf/lL483G52vWDx/UZSO/74SkUyZUhjKYu8OcDTnd4pigb mwKhxOtt5m4ic/RLT/OgH41AFQo8Ac8j01rjZZ/3Bhy8jQ/xpfAfCF6sui5eGPn6 Wcpf+IU0GOZeZCYhsYRf3hjrhqe05Yhbfx5PVwgl8M5UHLooH3XXe0aa7xoesRfq tss9OFAf7C+rG9NodN93xnPmGwD22H2wFSGpV2mPn+oZELw06OFJs/C74SJNdtOX ba58yrtUxbdacKXwl+I7+TwxLDLzPLOQWN2rXeecooInw7M5CkjUxTmh5B+JX/pV 6Vg8jR/3apz46k2UWilwe4o5vwixIHvUqSENfSM4BajQDe0RN1pZL2h9aNwtlpTv 29JdNnG3Q8SOastfjTJEWIXitjYpXpfaCbfiPJr8Nc3vWoWhSy/TQAcWxpI/EeWy iOcLfXbLpdh5oDgtDKZ9lJIMEehagV+v3FOgMGpSaNPZ4hlfGBl1vmelnmAyTOSA 0F7b7M4AkYhrPRRjHUkboknTclVoQdkSUfO99MDg31iUfi8aUNM= =eYI1 -----END PGP SIGNATURE----- --RhUH2Ysw6aD5utA4-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B4E4C433E2 for ; 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Tue, 14 Jul 2020 02:18:52 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id bs18sm14019738edb.38.2020.07.14.02.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2020 02:18:50 -0700 (PDT) Date: Tue, 14 Jul 2020 11:18:49 +0200 From: Thierry Reding To: Jon Hunter Cc: Rob Herring , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH 2/3] arm64: tegra: Enable DFLL support on Jetson Nano Message-ID: <20200714091849.GD141356@ulmo> References: <20200712102506.23686-1-jonathanh@nvidia.com> <20200712102506.23686-3-jonathanh@nvidia.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="RhUH2Ysw6aD5utA4" Content-Disposition: inline In-Reply-To: <20200712102506.23686-3-jonathanh@nvidia.com> User-Agent: Mutt/1.14.4 (2020-06-18) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org --RhUH2Ysw6aD5utA4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sun, Jul 12, 2020 at 11:25:05AM +0100, Jon Hunter wrote: > Populate the DFLL node and corresponding PWM pin nodes in order to > enable CPUFREQ support on the Jetson Nano platform. >=20 > Signed-off-by: Jon Hunter > --- > .../boot/dts/nvidia/tegra210-p3450-0000.dts | 37 +++++++++++++++++++ > 1 file changed, 37 insertions(+) Applied, thanks. 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