From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A132DC433DF for ; Tue, 14 Jul 2020 14:36:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 876892067D for ; Tue, 14 Jul 2020 14:36:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726456AbgGNOgX (ORCPT ); Tue, 14 Jul 2020 10:36:23 -0400 Received: from foss.arm.com ([217.140.110.172]:34706 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725890AbgGNOgW (ORCPT ); Tue, 14 Jul 2020 10:36:22 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 734AF1FB; Tue, 14 Jul 2020 07:36:21 -0700 (PDT) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C1A13F792; Tue, 14 Jul 2020 07:36:20 -0700 (PDT) Date: Tue, 14 Jul 2020 15:36:14 +0100 From: Lorenzo Pieralisi To: Shmuel Hazan Cc: Thomas Petazzoni , Jason Cooper , Marek =?iso-8859-1?Q?Beh=FAn?= , Baruch Siach , Chris Packham , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bjorn Helgaas Subject: Re: [PATCH v3] PCI: mvebu: Setup BAR0 in order to fix MSI Message-ID: <20200714143614.GA14416@e121166-lin.cambridge.arm.com> References: <20200623060334.108444-1-sh@tkos.co.il> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200623060334.108444-1-sh@tkos.co.il> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Jun 23, 2020 at 09:03:35AM +0300, Shmuel Hazan wrote: > According to the Armada XP datasheet, section 10.2.6: "in order for > the device to do a write to the MSI doorbell address, it needs to write > to a register in the internal registers space". > > As a result of the requirement above, without this patch, MSI won't > function and therefore some devices won't operate properly without > pci=nomsi. > > This requirement was not present at the time of writing this driver > since the vendor u-boot always initializes all PCIe controllers > (incl. BAR0 initialization) and for some time, the vendor u-boot was > the only available bootloader for this driver's SoCs (e.g. A38x,A37x, > etc). > > Tested on an Armada 385 board on mainline u-boot (2020.4), without > u-boot PCI initialization and the following PCIe devices: > - Wilocity Wil6200 rev 2 (wil6210) > - Qualcomm Atheros QCA6174 (ath10k_pci) > > Both failed to get a response from the device after loading the > firmware and seem to operate properly with this patch. > > Signed-off-by: Shmuel Hazan > > --- > > Changes in v3: > * Added sign-off. > > --- > drivers/pci/controller/pci-mvebu.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) Applied to pci/mvebu, thanks. Lorenzo > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c > index 153a64676bc9..101c06602aa1 100644 > --- a/drivers/pci/controller/pci-mvebu.c > +++ b/drivers/pci/controller/pci-mvebu.c > @@ -105,6 +105,7 @@ struct mvebu_pcie_port { > struct mvebu_pcie_window memwin; > struct mvebu_pcie_window iowin; > u32 saved_pcie_stat; > + struct resource regs; > }; > > static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) > @@ -149,7 +150,9 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) > > /* > * Setup PCIE BARs and Address Decode Wins: > - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks > + * BAR[0] -> internal registers (needed for MSI) > + * BAR[1] -> covers all DRAM banks > + * BAR[2] -> Disabled > * WIN[0-3] -> DRAM bank[0-3] > */ > static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) > @@ -203,6 +206,12 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) > mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); > mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, > PCIE_BAR_CTRL_OFF(1)); > + > + /* > + * Point BAR[0] to the device's internal registers. > + */ > + mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); > + mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); > } > > static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) > @@ -708,14 +717,13 @@ static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, > struct device_node *np, > struct mvebu_pcie_port *port) > { > - struct resource regs; > int ret = 0; > > - ret = of_address_to_resource(np, 0, ®s); > + ret = of_address_to_resource(np, 0, &port->regs); > if (ret) > return (void __iomem *)ERR_PTR(ret); > > - return devm_ioremap_resource(&pdev->dev, ®s); > + return devm_ioremap_resource(&pdev->dev, &port->regs); > } > > #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) > -- > 2.27.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DE96C433E0 for ; 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Tue, 14 Jul 2020 07:36:20 -0700 (PDT) Date: Tue, 14 Jul 2020 15:36:14 +0100 From: Lorenzo Pieralisi To: Shmuel Hazan Subject: Re: [PATCH v3] PCI: mvebu: Setup BAR0 in order to fix MSI Message-ID: <20200714143614.GA14416@e121166-lin.cambridge.arm.com> References: <20200623060334.108444-1-sh@tkos.co.il> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200623060334.108444-1-sh@tkos.co.il> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200714_103629_666751_35E59DD4 X-CRM114-Status: GOOD ( 24.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Baruch Siach , Jason Cooper , linux-pci@vger.kernel.org, Marek =?iso-8859-1?Q?Beh=FAn?= , Chris Packham , Bjorn Helgaas , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jun 23, 2020 at 09:03:35AM +0300, Shmuel Hazan wrote: > According to the Armada XP datasheet, section 10.2.6: "in order for > the device to do a write to the MSI doorbell address, it needs to write > to a register in the internal registers space". > > As a result of the requirement above, without this patch, MSI won't > function and therefore some devices won't operate properly without > pci=nomsi. > > This requirement was not present at the time of writing this driver > since the vendor u-boot always initializes all PCIe controllers > (incl. BAR0 initialization) and for some time, the vendor u-boot was > the only available bootloader for this driver's SoCs (e.g. A38x,A37x, > etc). > > Tested on an Armada 385 board on mainline u-boot (2020.4), without > u-boot PCI initialization and the following PCIe devices: > - Wilocity Wil6200 rev 2 (wil6210) > - Qualcomm Atheros QCA6174 (ath10k_pci) > > Both failed to get a response from the device after loading the > firmware and seem to operate properly with this patch. > > Signed-off-by: Shmuel Hazan > > --- > > Changes in v3: > * Added sign-off. > > --- > drivers/pci/controller/pci-mvebu.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) Applied to pci/mvebu, thanks. Lorenzo > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c > index 153a64676bc9..101c06602aa1 100644 > --- a/drivers/pci/controller/pci-mvebu.c > +++ b/drivers/pci/controller/pci-mvebu.c > @@ -105,6 +105,7 @@ struct mvebu_pcie_port { > struct mvebu_pcie_window memwin; > struct mvebu_pcie_window iowin; > u32 saved_pcie_stat; > + struct resource regs; > }; > > static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) > @@ -149,7 +150,9 @@ static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr) > > /* > * Setup PCIE BARs and Address Decode Wins: > - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks > + * BAR[0] -> internal registers (needed for MSI) > + * BAR[1] -> covers all DRAM banks > + * BAR[2] -> Disabled > * WIN[0-3] -> DRAM bank[0-3] > */ > static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) > @@ -203,6 +206,12 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port) > mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1)); > mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, > PCIE_BAR_CTRL_OFF(1)); > + > + /* > + * Point BAR[0] to the device's internal registers. > + */ > + mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); > + mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0)); > } > > static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port) > @@ -708,14 +717,13 @@ static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev, > struct device_node *np, > struct mvebu_pcie_port *port) > { > - struct resource regs; > int ret = 0; > > - ret = of_address_to_resource(np, 0, ®s); > + ret = of_address_to_resource(np, 0, &port->regs); > if (ret) > return (void __iomem *)ERR_PTR(ret); > > - return devm_ioremap_resource(&pdev->dev, ®s); > + return devm_ioremap_resource(&pdev->dev, &port->regs); > } > > #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03) > -- > 2.27.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel