From: Mauro Rossi <issor.oruam@gmail.com>
To: amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com, harry.wentland@amd.com
Subject: [PATCH v3 01/27] drm/amdgpu: add some required DCE6 registers (v6)
Date: Thu, 16 Jul 2020 23:22:25 +0200 [thread overview]
Message-ID: <20200716212251.1539094-2-issor.oruam@gmail.com> (raw)
In-Reply-To: <20200716212251.1539094-1-issor.oruam@gmail.com>
From: Alex Deucher <alexander.deucher@amd.com>
To help with the DC port.
v2: add missing masks, add additional registers
v3: more updates
v4: fix accidently dropped changes
v5: add missing nb pstate mask
v6: add vblank, vline masks
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/include/asic_reg/dce/dce_6_0_d.h | 62 ++++++++++++-
.../include/asic_reg/dce/dce_6_0_sh_mask.h | 92 +++++++++++++++++++
2 files changed, 153 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
index ae798f768853..74897b046006 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h
@@ -4444,14 +4444,74 @@
/* Registers that spilled out of sid.h */
#define mmDATA_FORMAT 0x1AC0
+#define mmLB0_DATA_FORMAT 0x1AC0
+#define mmLB1_DATA_FORMAT 0x1DC0
+#define mmLB2_DATA_FORMAT 0x40C0
+#define mmLB3_DATA_FORMAT 0x43C0
+#define mmLB4_DATA_FORMAT 0x46C0
+#define mmLB5_DATA_FORMAT 0x49C0
#define mmDESKTOP_HEIGHT 0x1AC1
+#define mmLB0_DESKTOP_HEIGHT 0x1AC1
+#define mmLB1_DESKTOP_HEIGHT 0x1DC1
+#define mmLB2_DESKTOP_HEIGHT 0x40C1
+#define mmLB3_DESKTOP_HEIGHT 0x43C1
+#define mmLB4_DESKTOP_HEIGHT 0x46C1
+#define mmLB5_DESKTOP_HEIGHT 0x49C1
#define mmDC_LB_MEMORY_SPLIT 0x1AC3
+#define mmLB0_DC_LB_MEMORY_SPLIT 0x1AC3
+#define mmLB1_DC_LB_MEMORY_SPLIT 0x1DC3
+#define mmLB2_DC_LB_MEMORY_SPLIT 0x40C3
+#define mmLB3_DC_LB_MEMORY_SPLIT 0x43C3
+#define mmLB4_DC_LB_MEMORY_SPLIT 0x46C3
+#define mmLB5_DC_LB_MEMORY_SPLIT 0x49C3
+#define mmDC_LB_MEM_SIZE 0x1AC4
+#define mmLB0_DC_LB_MEM_SIZE 0x1AC4
+#define mmLB1_DC_LB_MEM_SIZE 0x1DC4
+#define mmLB2_DC_LB_MEM_SIZE 0x40C4
+#define mmLB3_DC_LB_MEM_SIZE 0x43C4
+#define mmLB4_DC_LB_MEM_SIZE 0x46C4
+#define mmLB5_DC_LB_MEM_SIZE 0x49C4
#define mmPRIORITY_A_CNT 0x1AC6
+#define mmLB0_PRIORITY_A_CNT 0x1AC6
+#define mmLB1_PRIORITY_A_CNT 0x1DC6
+#define mmLB2_PRIORITY_A_CNT 0x40C6
+#define mmLB3_PRIORITY_A_CNT 0x43C6
+#define mmLB4_PRIORITY_A_CNT 0x46C6
+#define mmLB5_PRIORITY_A_CNT 0x49C6
#define mmPRIORITY_B_CNT 0x1AC7
+#define mmLB0_PRIORITY_B_CNT 0x1AC7
+#define mmLB1_PRIORITY_B_CNT 0x1DC7
+#define mmLB2_PRIORITY_B_CNT 0x40C7
+#define mmLB3_PRIORITY_B_CNT 0x43C7
+#define mmLB4_PRIORITY_B_CNT 0x46C7
+#define mmLB5_PRIORITY_B_CNT 0x49C7
#define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32
+#define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 0x1B32
+#define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 0x1E32
+#define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 0x4132
+#define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 0x4432
+#define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 0x4732
+#define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 0x4A32
#define mmINT_MASK 0x1AD0
+#define mmLB0_INT_MASK 0x1AD0
+#define mmLB1_INT_MASK 0x1DD0
+#define mmLB2_INT_MASK 0x40D0
+#define mmLB3_INT_MASK 0x43D0
+#define mmLB4_INT_MASK 0x46D0
+#define mmLB5_INT_MASK 0x49D0
#define mmVLINE_STATUS 0x1AEE
+#define mmLB0_VLINE_STATUS 0x1AEE
+#define mmLB1_VLINE_STATUS 0x1DEE
+#define mmLB2_VLINE_STATUS 0x40EE
+#define mmLB3_VLINE_STATUS 0x43EE
+#define mmLB4_VLINE_STATUS 0x46EE
+#define mmLB5_VLINE_STATUS 0x49EE
#define mmVBLANK_STATUS 0x1AEF
-
+#define mmLB0_VBLANK_STATUS 0x1AEF
+#define mmLB1_VBLANK_STATUS 0x1DEF
+#define mmLB2_VBLANK_STATUS 0x40EF
+#define mmLB3_VBLANK_STATUS 0x43EF
+#define mmLB4_VBLANK_STATUS 0x46EF
+#define mmLB5_VBLANK_STATUS 0x49EF
#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
index abe05bc80752..bf262460b0b9 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h
@@ -2076,6 +2076,8 @@
#define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c
#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L
#define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004
+#define CRTC_CONTROL__CRTC_PREFETCH_EN_MASK 0x10000000L
+#define CRTC_CONTROL__CRTC_PREFETCH_EN__SHIFT 0x0000001c
#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L
#define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000
#define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL
@@ -6364,6 +6366,8 @@
#define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000
#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L
#define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010
+#define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK_MASK 0x00030000L
+#define DPG_PIPE_ARBITRATION_CONTROL3__URGENCY_WATERMARK_MASK__SHIFT 0x00000010
#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L
#define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000
#define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L
@@ -6384,6 +6388,8 @@
#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008
#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L
#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x00003000L
+#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c
#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L
#define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010
#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L
@@ -6406,6 +6412,8 @@
#define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008
#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L
#define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK_MASK 0x00003000L
+#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK__SHIFT 0x0000000c
#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L
#define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010
#define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L
@@ -7256,6 +7264,8 @@
#define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008
#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L
#define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012
+#define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L
+#define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014
#define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL
#define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002
#define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L
@@ -9835,4 +9845,86 @@
#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
#define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
+// DATA_FORMAT
+#define DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L
+#define DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x00000000
+#define DATA_FORMAT__RESET_REQ_AT_EOL_MASK 0x00000010L
+#define DATA_FORMAT__RESET_REQ_AT_EOL__SHIFT 0x00000004
+#define DATA_FORMAT__PREFETCH_MASK 0x00001000L
+#define DATA_FORMAT__PREFETCH__SHIFT 0x0000000c
+#define DATA_FORMAT__SOF_READ_PT_MASK 0x001f0000L
+#define DATA_FORMAT__SOF_READ_PT__SHIFT 0x00000010
+#define DATA_FORMAT__REQUEST_MODE_MASK 0x03000000L
+#define DATA_FORMAT__REQUEST_MODE__SHIFT 0x00000018
+#define DATA_FORMAT__ALLOW_REQ_MODE_1_2_MASK 0x10000000L
+#define DATA_FORMAT__ALLOW_REQ_MODE_1_2__SHIFT 0x0000001c
+
+
+// DC_LB_MEMORY_SPLIT
+#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS_MASK 0x000f0000L
+#define DC_LB_MEMORY_SPLIT__LB_NUM_PARTITIONS__SHIFT 0x00000010
+#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG_MASK 0x00300000L
+#define DC_LB_MEMORY_SPLIT__DC_LB_MEMORY_CONFIG__SHIFT 0x00000014
+
+// DC_LB_MEM_SIZE
+#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE_MASK 0x000007ffL
+#define DC_LB_MEM_SIZE__DC_LB_MEM_SIZE__SHIFT 0x00000000
+
+// SCL_TAP_CONTROL
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS_MASK 0x00000007L
+#define SCL_TAP_CONTROL__SCL_V_NUM_OF_TAPS__SHIFT 0x00000000
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS_MASK 0x00000f00L
+#define SCL_TAP_CONTROL__SCL_H_NUM_OF_TAPS__SHIFT 0x00000008
+
+// INT_MASK
+#define INT_MASK__VBLANK_INT_MASK 0x00000001L
+#define INT_MASK__VBLANK_INT__SHIFT 0x00000000
+#define INT_MASK__VLINE_INT_MASK 0x00000010L
+#define INT_MASK__VLINE_INT__SHIFT 0x00000004
+
+// PRIORITY_A_CNT
+#define PRIORITY_A_CNT__PRIORITY_MARK_A_MASK 0x00007fffL
+#define PRIORITY_A_CNT__PRIORITY_MARK_A__SHIFT 0x00000000
+#define PRIORITY_A_CNT__PRIORITY_A_OFF_MASK 0x00010000L
+#define PRIORITY_A_CNT__PRIORITY_A_OFF__SHIFT 0x00000010
+#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON_MASK 0x00100000L
+#define PRIORITY_A_CNT__PRIORITY_A_ALWAYS_ON__SHIFT 0x00000014
+#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK_MASK 0x01000000L
+#define PRIORITY_A_CNT__PRIORITY_A_FORCE_MASK__SHIFT 0x00000018
+
+// PRIORITY_B_CNT
+#define PRIORITY_B_CNT__PRIORITY_MARK_B_MASK 0x00007fffL
+#define PRIORITY_B_CNT__PRIORITY_MARK_B__SHIFT 0x00000000
+#define PRIORITY_B_CNT__PRIORITY_B_OFF_MASK 0x00010000L
+#define PRIORITY_B_CNT__PRIORITY_B_OFF__SHIFT 0x00000010
+#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON_MASK 0x00100000L
+#define PRIORITY_B_CNT__PRIORITY_B_ALWAYS_ON__SHIFT 0x00000014
+#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK_MASK 0x01000000L
+#define PRIORITY_B_CNT__PRIORITY_B_FORCE_MASK__SHIFT 0x00000018
+
+// VLINE_STATUS
+#define VLINE_STATUS__VLINE_OCCURRED_MASK 0x00000001L
+#define VLINE_STATUS__VLINE_OCCURRED__SHIFT 0x00000000
+#define VLINE_STATUS__VLINE_ACK_MASK 0x00000010L
+#define VLINE_STATUS__VLINE_ACK__SHIFT 0x00000004
+#define VLINE_STATUS__VLINE_STAT_MASK 0x00001000L
+#define VLINE_STATUS__VLINE_STAT__SHIFT 0x0000000c
+#define VLINE_STATUS__VLINE_INTERRUPT_MASK 0x00010000L
+#define VLINE_STATUS__VLINE_INTERRUPT__SHIFT 0x00000010
+#define VLINE_STATUS__VLINE_INTERRUPT_TYPE_MASK 0x00020000L
+#define VLINE_STATUS__VLINE_INTERRUPT_TYPE__SHIFT 0x00000011
+
+// VBLANK_STATUS
+#define VBLANK_STATUS__VBLANK_OCCURRED_MASK 0x00000001L
+#define VBLANK_STATUS__VBLANK_OCCURRED__SHIFT 0x00000000
+#define VBLANK_STATUS__VBLANK_ACK_MASK 0x00000010L
+#define VBLANK_STATUS__VBLANK_ACK__SHIFT 0x00000004
+#define VBLANK_STATUS__VBLANK_STAT_MASK 0x00001000L
+#define VBLANK_STATUS__VBLANK_STAT__SHIFT 0x0000000c
+#define VBLANK_STATUS__VBLANK_INTERRUPT_MASK 0x00010000L
+#define VBLANK_STATUS__VBLANK_INTERRUPT__SHIFT 0x00000010
+#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE_MASK 0x00020000L
+#define VBLANK_STATUS__VBLANK_INTERRUPT_TYPE__SHIFT 0x00000011
+
+
#endif
--
2.25.1
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next prev parent reply other threads:[~2020-07-16 21:23 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 21:22 Mauro Rossi
2020-07-16 21:22 ` Mauro Rossi [this message]
2020-07-16 21:22 ` [PATCH v3 02/27] drm/amd/display: add asics info for SI parts Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 03/27] drm/amd/display: dc/dce: add initial DCE6 support (v9b) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 04/27] drm/amd/display: dc/core: add SI/DCE6 support (v2) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 05/27] drm/amd/display: dc/bios: add support for DCE6 Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 06/27] drm/amd/display: dc/gpio: add support for DCE6 (v2) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 07/27] drm/amd/display: dc/irq: add support for DCE6 (v4) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 08/27] drm/amd/display: amdgpu_dm: add SI support (v4) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 09/27] drm/amd/display: dc/clk_mgr: add support for SI parts (v2) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 10/27] drm/amd/display: dc/dce60: set max_cursor_size to 64 Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 11/27] drm/amd/display: dce_audio: add DCE6 specific macros, functions Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 12/27] drm/amd/display: dce_dmcu: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 13/27] drm/amd/display: dce_hwseq: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 14/27] drm/amd/display: dce_ipp: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 15/27] drm/amd/display: dce_link_encoder: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 16/27] drm/amd/display: dce_mem_input: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 17/27] drm/amd/display: dce_opp: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 18/27] drm/amd/display: dce_transform: " Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 19/27] drm/amdgpu: add some required DCE6 registers (v7) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 20/27] drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 21/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific functions Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 22/27] drm/amd/display: dce60_hw_sequencer: add DCE6 specific .cursor_lock Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 23/27] drm/amd/display: dce60_timing_generator: add DCE6 specific functions Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 24/27] drm/amd/display: dc/dce60: use DCE6 headers (v6) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 25/27] drm/amd/display: create plane rotation property for Bonaire and later Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 26/27] drm/amdgpu: enable DC support for SI parts (v2) Mauro Rossi
2020-07-16 21:22 ` [PATCH v3 27/27] drm/amd/display: enable SI support in the Kconfig (v2) Mauro Rossi
2020-07-20 9:00 ` Christian König
2020-07-20 9:59 ` Re: Mauro Rossi
2020-07-22 2:51 ` Re: Alex Deucher
2020-07-22 7:56 ` Re: Mauro Rossi
2020-07-24 18:31 ` Re: Alex Deucher
2020-07-26 15:31 ` Re: Mauro Rossi
2020-07-27 18:31 ` Re: Alex Deucher
2020-07-27 19:46 ` Re: Mauro Rossi
2020-07-27 19:54 ` Re: Alex Deucher
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