All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jianqun Xu <jay.xu@rock-chips.com>
To: heiko@sntech.de, linus.walleij@linaro.org
Cc: linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org,
	linux-kernel@vger.kernel.org, kever.yang@rock-chips.com,
	david.wu@rock-chips.com, Jianqun Xu <jay.xu@rock-chips.com>
Subject: [PATCH 12/13] pinctrl: rockchip: define common codes without special chip name
Date: Fri, 17 Jul 2020 11:27:29 +0800	[thread overview]
Message-ID: <20200717032729.18435-1-jay.xu@rock-chips.com> (raw)
In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com>

Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and
modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 drivers/pinctrl/pinctrl-rockchip.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3b74455dcdb2..71a367896297 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -75,6 +75,9 @@ enum rockchip_pinctrl_type {
 #define IOMUX_WIDTH_3BIT	BIT(4)
 #define IOMUX_WIDTH_2BIT	BIT(5)
 
+#define ROCKCHIP_DRV_3BITS_PER_PIN	(3)
+#define ROCKCHIP_DRV_BITS_PER_PIN	(2)
+
 /**
  * @type: iomux variant using IOMUX_* constants
  * @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 
 #define RK3399_PULL_GRF_OFFSET		0xe040
 #define RK3399_PULL_PMU_OFFSET		0x40
-#define RK3399_DRV_3BITS_PER_PIN	3
 #define RK3399_PULL_BITS_PER_PIN	2
 #define RK3399_PULL_PINS_PER_REG	8
 #define RK3399_PULL_BANK_STRIDE		16
@@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 	switch (drv_type) {
 	case DRV_TYPE_IO_1V8_3V0_AUTO:
 	case DRV_TYPE_IO_3V3_ONLY:
-		rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+		rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
 		switch (bit) {
 		case 0 ... 12:
 			/* regular case, nothing to do */
@@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
 	case DRV_TYPE_IO_DEFAULT:
 	case DRV_TYPE_IO_1V8_OR_3V0:
 	case DRV_TYPE_IO_1V8_ONLY:
-		rmask_bits = RK3288_DRV_BITS_PER_PIN;
+		rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
 		break;
 	default:
 		dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
@@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 	switch (drv_type) {
 	case DRV_TYPE_IO_1V8_3V0_AUTO:
 	case DRV_TYPE_IO_3V3_ONLY:
-		rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+		rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
 		switch (bit) {
 		case 0 ... 12:
 			/* regular case, nothing to do */
@@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
 	case DRV_TYPE_IO_DEFAULT:
 	case DRV_TYPE_IO_1V8_OR_3V0:
 	case DRV_TYPE_IO_1V8_ONLY:
-		rmask_bits = RK3288_DRV_BITS_PER_PIN;
+		rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
 		break;
 	default:
 		dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
-- 
2.17.1




  parent reply	other threads:[~2020-07-17  3:27 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-17  3:23 [PATCH RESEND 00/13] pinctrl: rockchip: prepare work for split driver Jianqun Xu
2020-07-17  3:23 ` [PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl Jianqun Xu
2020-07-17  3:24 ` [PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct Jianqun Xu
2020-07-17  3:24 ` [PATCH 03/13] pinctrl: rockchip: make driver be tristate module Jianqun Xu
2020-07-18 23:32   ` kernel test robot
2020-07-18 23:32     ` kernel test robot
2020-07-18 23:32     ` kernel test robot
2020-07-17  3:24 ` [PATCH 04/13] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq Jianqun Xu
2020-07-17  3:26 ` [PATCH 05/13] pinctrl: rockchip: create irq mapping in gpio_to_irq Jianqun Xu
2020-07-17  3:26 ` [PATCH 06/13] pinctrl: rockchip: Add RK3399 definitions to separate from other SoCs Jianqun Xu
2020-07-17  3:26 ` [PATCH 07/13] pinctrl: rockchip: Add RK3368 " Jianqun Xu
2020-07-17  3:27 ` [PATCH 08/13] pinctrl: rockchip: Add RK3308 " Jianqun Xu
2020-07-17  3:27 ` [PATCH 09/13] pinctrl: rockchip: Add RK3228 " Jianqun Xu
2020-07-17  3:27 ` [PATCH 10/13] pinctrl: rockchip: Add RK3288 " Jianqun Xu
2020-07-17  3:27 ` [PATCH 11/13] pinctrl: rockchip: Add RK3128 " Jianqun Xu
2020-07-17  3:27 ` Jianqun Xu [this message]
2020-07-17  3:27 ` [PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions Jianqun Xu
  -- strict thread matches above, loose matches on Subject: below --
2020-07-17  1:48 [PATCH 00/13] pinctrl: rockchip: prepare work for split driver Jianqun Xu
2020-07-17  1:53 ` [PATCH 12/13] pinctrl: rockchip: define common codes without special chip name Jianqun Xu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200717032729.18435-1-jay.xu@rock-chips.com \
    --to=jay.xu@rock-chips.com \
    --cc=david.wu@rock-chips.com \
    --cc=heiko@sntech.de \
    --cc=kever.yang@rock-chips.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-gpio@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-rockchip@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.