From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE6B1C433F4 for ; Fri, 17 Jul 2020 14:08:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C26F422CB2 for ; Fri, 17 Jul 2020 14:08:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728135AbgGQOIE (ORCPT ); Fri, 17 Jul 2020 10:08:04 -0400 Received: from mga01.intel.com ([192.55.52.88]:11837 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727986AbgGQOH1 (ORCPT ); Fri, 17 Jul 2020 10:07:27 -0400 IronPort-SDR: xjOEaVRL5FsZQMjz/eMiXbzDKtEgsqgAe1y6wuUPHYvD6vDaqhGPz7g0ZM4wP+taXdNXpUyT9r 5zS+hyg7ZzXA== X-IronPort-AV: E=McAfee;i="6000,8403,9684"; a="167722810" X-IronPort-AV: E=Sophos;i="5.75,362,1589266800"; d="scan'208";a="167722810" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2020 07:07:27 -0700 IronPort-SDR: 3LRflFszD+gkChtUTjMXPL/544T4lv2YGa31DrlHoexqkXL6VBkWy72U3XUHNWgQuQZzDCG6Et ytVAatouC4vg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,362,1589266800"; d="scan'208";a="460856491" Received: from labuser-ice-lake-client-platform.jf.intel.com ([10.54.55.65]) by orsmga005.jf.intel.com with ESMTP; 17 Jul 2020 07:07:26 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, acme@redhat.com, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: jolsa@kernel.org, eranian@google.com, alexander.shishkin@linux.intel.com, ak@linux.intel.com, Kan Liang Subject: [PATCH V6 08/14] perf/x86: Add a macro for RDPMC offset of fixed counters Date: Fri, 17 Jul 2020 07:05:48 -0700 Message-Id: <20200717140554.22863-9-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717140554.22863-1-kan.liang@linux.intel.com> References: <20200717140554.22863-1-kan.liang@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Kan Liang The RDPMC base offset of fixed counters is hard-code. Use a meaningful name to replace the magic number to improve the readability of the code. Signed-off-by: Kan Liang --- arch/x86/events/core.c | 3 ++- arch/x86/include/asm/perf_event.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 8aa7da80f5d6..ace21b133015 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1158,7 +1158,8 @@ static inline void x86_assign_hw_event(struct perf_event *event, hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (idx - INTEL_PMC_IDX_FIXED); - hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | 1<<30; + hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | + INTEL_PMC_FIXED_RDPMC_BASE; break; default: diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 8870eb1c3b17..84bfb9d1f948 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -196,6 +196,9 @@ struct x86_pmu_capability { * Fixed-purpose performance events: */ +/* RDPMC offset for Fixed PMCs */ +#define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30) + /* * All the fixed-mode PMCs are configured via this single MSR: */ -- 2.17.1