Hi Jordan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20200720]
[also build test ERROR on v5.8-rc6]
[cannot apply to iommu/next robh/for-next arm-perf/for-next/perf arm64/for-next/core linus/master v5.8-rc6 v5.8-rc5 v5.8-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Jordan-Crouse/iommu-arm-smmu-Add-Adreno-SMMU-specific-implementation/20200721-004820
base:    ab8be66e724ecf4bffb2895c9c91bbd44fa687c7
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   drivers/gpu/drm/msm/adreno/a6xx_gpu.c:33:6: warning: no previous prototype for 'a6xx_idle' [-Wmissing-prototypes]
      33 | bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
         |      ^~~~~~~~~
   drivers/gpu/drm/msm/adreno/a6xx_gpu.c: In function 'a6xx_set_pagetable':
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:97:17: error: implicit declaration of function 'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO' [-Werror=implicit-function-declaration]
      97 |  OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:99:3: error: implicit declaration of function 'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI' [-Werror=implicit-function-declaration]
      99 |   CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:100:3: error: implicit declaration of function 'CP_SMMU_TABLE_UPDATE_1_ASID' [-Werror=implicit-function-declaration]
     100 |   CP_SMMU_TABLE_UPDATE_1_ASID(asid));
         |   ^~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:101:17: error: implicit declaration of function 'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR' [-Werror=implicit-function-declaration]
     101 |  OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:102:17: error: implicit declaration of function 'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK' [-Werror=implicit-function-declaration]
     102 |  OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
         |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:108:17: error: implicit declaration of function 'CP_MEM_WRITE_0_ADDR_LO'; did you mean 'CP_EVENT_WRITE_1_ADDR_0_LO'? [-Werror=implicit-function-declaration]
     108 |  OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
         |                 ^~~~~~~~~~~~~~~~~~~~~~
         |                 CP_EVENT_WRITE_1_ADDR_0_LO
>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c:109:17: error: implicit declaration of function 'CP_MEM_WRITE_1_ADDR_HI'; did you mean 'CP_EVENT_WRITE_2_ADDR_0_HI'? [-Werror=implicit-function-declaration]
     109 |  OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
         |                 ^~~~~~~~~~~~~~~~~~~~~~
         |                 CP_EVENT_WRITE_2_ADDR_0_HI
   cc1: some warnings being treated as errors

vim +/CP_SMMU_TABLE_UPDATE_0_TTBR0_LO +97 drivers/gpu/drm/msm/adreno/a6xx_gpu.c

    81	
    82	static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
    83			struct msm_ringbuffer *ring, struct msm_file_private *ctx)
    84	{
    85		phys_addr_t ttbr;
    86		u32 asid;
    87		u64 memptr = rbmemptr(ring, ttbr0);
    88	
    89		if (ctx == a6xx_gpu->cur_ctx)
    90			return;
    91	
    92		if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
    93			return;
    94	
    95		/* Execute the table update */
    96		OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
  > 97		OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
    98		OUT_RING(ring,
  > 99			CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
 > 100			CP_SMMU_TABLE_UPDATE_1_ASID(asid));
 > 101		OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
 > 102		OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
   103	
   104		/*
   105		 * Write the new TTBR0 to the memstore. This is good for debugging.
   106		 */
   107		OUT_PKT7(ring, CP_MEM_WRITE, 4);
 > 108		OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
 > 109		OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
   110		OUT_RING(ring, lower_32_bits(ttbr));
   111		OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
   112	
   113	
   114		a6xx_gpu->cur_ctx = ctx;
   115	}
   116	

---
0-DAY CI Kernel Test Service, Intel Corporation
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