[PATCH 0/3] Add RTC related clocks for Ingenic SoCs.

[PATCH 0/3] Add RTC related clocks for Ingenic SoCs.

[周琰杰 (Zhou Yanjie)]

1.Add RTC related clocks bindings for the JZ4780 SoC,
  the X1000 SoC, and the X1830 SoC.
2.Add "XXXX_CLK_EXCLK_DIV512" and "XXXX_CLK_RTC" for
  the JZ4780 SoC, the X1000 SoC, and the X1830 SoC.

周琰杰 (Zhou Yanjie) (3):
  dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
  dt-bindings: clock: Add tabs to align code.
  clk: Ingenic: Add RTC related clocks for Ingenic SoCs.

 drivers/clk/ingenic/jz4780-cgu.c       |  12 +++
 drivers/clk/ingenic/x1000-cgu.c        |  13 +++
 drivers/clk/ingenic/x1830-cgu.c        |  13 +++
 include/dt-bindings/clock/jz4780-cgu.h | 144 +++++++++++++++++----------------
 include/dt-bindings/clock/x1000-cgu.h  |   2 +
 include/dt-bindings/clock/x1830-cgu.h  |   2 +
 6 files changed, 115 insertions(+), 71 deletions(-)

-- 
2.11.0

[PATCH 1/3] dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.

[周琰杰 (Zhou Yanjie)]

Add RTC related clocks bindings for the JZ4780 SoC, the X1000 SoC,
and the X1830 SoC from Ingenic.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
 include/dt-bindings/clock/jz4780-cgu.h | 2 ++
 include/dt-bindings/clock/x1000-cgu.h  | 2 ++
 include/dt-bindings/clock/x1830-cgu.h  | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
index 1859ce53ee38..cb07a0978301 100644
--- a/include/dt-bindings/clock/jz4780-cgu.h
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -85,5 +85,7 @@
 #define JZ4780_CLK_DES		70
 #define JZ4780_CLK_X2D		71
 #define JZ4780_CLK_CORE1	72
+#define JZ4780_CLK_EXCLK_DIV512	73
+#define JZ4780_CLK_RTC		74
 
 #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
index 0367c8c02e16..f187e0719fd3 100644
--- a/include/dt-bindings/clock/x1000-cgu.h
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -48,5 +48,7 @@
 #define X1000_CLK_SSI			33
 #define X1000_CLK_OST			34
 #define X1000_CLK_PDMA			35
+#define X1000_CLK_EXCLK_DIV512	36
+#define X1000_CLK_RTC			37
 
 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h
index 801e1d09c881..88455376a950 100644
--- a/include/dt-bindings/clock/x1830-cgu.h
+++ b/include/dt-bindings/clock/x1830-cgu.h
@@ -51,5 +51,7 @@
 #define X1830_CLK_TCU			36
 #define X1830_CLK_DTRNG			37
 #define X1830_CLK_OST			38
+#define X1830_CLK_EXCLK_DIV512	39
+#define X1830_CLK_RTC			40
 
 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
-- 
2.11.0

[PATCH 2/3] dt-bindings: clock: Add tabs to align code.

[周琰杰 (Zhou Yanjie)]

The "JZ4780_CLK_LCD0PIXCLK" and the "JZ4780_CLK_LCD1PIXCLK"
in the "jz4780.h" and the new added "JZ4780_CLK_EXCLK_DIV512"
in the previous patch is too long, add tabs to other lines
to align them.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
 include/dt-bindings/clock/jz4780-cgu.h | 144 ++++++++++++++++-----------------
 1 file changed, 72 insertions(+), 72 deletions(-)

diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h
index cb07a0978301..85cf8eb5081b 100644
--- a/include/dt-bindings/clock/jz4780-cgu.h
+++ b/include/dt-bindings/clock/jz4780-cgu.h
@@ -12,80 +12,80 @@
 #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
 #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__
 
-#define JZ4780_CLK_EXCLK	0
-#define JZ4780_CLK_RTCLK	1
-#define JZ4780_CLK_APLL		2
-#define JZ4780_CLK_MPLL		3
-#define JZ4780_CLK_EPLL		4
-#define JZ4780_CLK_VPLL		5
-#define JZ4780_CLK_OTGPHY	6
-#define JZ4780_CLK_SCLKA	7
-#define JZ4780_CLK_CPUMUX	8
-#define JZ4780_CLK_CPU		9
-#define JZ4780_CLK_L2CACHE	10
-#define JZ4780_CLK_AHB0		11
-#define JZ4780_CLK_AHB2PMUX	12
-#define JZ4780_CLK_AHB2		13
-#define JZ4780_CLK_PCLK		14
-#define JZ4780_CLK_DDR		15
-#define JZ4780_CLK_VPU		16
-#define JZ4780_CLK_I2SPLL	17
-#define JZ4780_CLK_I2S		18
+#define JZ4780_CLK_EXCLK		0
+#define JZ4780_CLK_RTCLK		1
+#define JZ4780_CLK_APLL			2
+#define JZ4780_CLK_MPLL			3
+#define JZ4780_CLK_EPLL			4
+#define JZ4780_CLK_VPLL			5
+#define JZ4780_CLK_OTGPHY		6
+#define JZ4780_CLK_SCLKA		7
+#define JZ4780_CLK_CPUMUX		8
+#define JZ4780_CLK_CPU			9
+#define JZ4780_CLK_L2CACHE		10
+#define JZ4780_CLK_AHB0			11
+#define JZ4780_CLK_AHB2PMUX		12
+#define JZ4780_CLK_AHB2			13
+#define JZ4780_CLK_PCLK			14
+#define JZ4780_CLK_DDR			15
+#define JZ4780_CLK_VPU			16
+#define JZ4780_CLK_I2SPLL		17
+#define JZ4780_CLK_I2S			18
 #define JZ4780_CLK_LCD0PIXCLK	19
 #define JZ4780_CLK_LCD1PIXCLK	20
-#define JZ4780_CLK_MSCMUX	21
-#define JZ4780_CLK_MSC0		22
-#define JZ4780_CLK_MSC1		23
-#define JZ4780_CLK_MSC2		24
-#define JZ4780_CLK_UHC		25
-#define JZ4780_CLK_SSIPLL	26
-#define JZ4780_CLK_SSI		27
-#define JZ4780_CLK_CIMMCLK	28
-#define JZ4780_CLK_PCMPLL	29
-#define JZ4780_CLK_PCM		30
-#define JZ4780_CLK_GPU		31
-#define JZ4780_CLK_HDMI		32
-#define JZ4780_CLK_BCH		33
-#define JZ4780_CLK_NEMC		34
-#define JZ4780_CLK_OTG0		35
-#define JZ4780_CLK_SSI0		36
-#define JZ4780_CLK_SMB0		37
-#define JZ4780_CLK_SMB1		38
-#define JZ4780_CLK_SCC		39
-#define JZ4780_CLK_AIC		40
-#define JZ4780_CLK_TSSI0	41
-#define JZ4780_CLK_OWI		42
-#define JZ4780_CLK_KBC		43
-#define JZ4780_CLK_SADC		44
-#define JZ4780_CLK_UART0	45
-#define JZ4780_CLK_UART1	46
-#define JZ4780_CLK_UART2	47
-#define JZ4780_CLK_UART3	48
-#define JZ4780_CLK_SSI1		49
-#define JZ4780_CLK_SSI2		50
-#define JZ4780_CLK_PDMA		51
-#define JZ4780_CLK_GPS		52
-#define JZ4780_CLK_MAC		53
-#define JZ4780_CLK_SMB2		54
-#define JZ4780_CLK_CIM		55
-#define JZ4780_CLK_LCD		56
-#define JZ4780_CLK_TVE		57
-#define JZ4780_CLK_IPU		58
-#define JZ4780_CLK_DDR0		59
-#define JZ4780_CLK_DDR1		60
-#define JZ4780_CLK_SMB3		61
-#define JZ4780_CLK_TSSI1	62
-#define JZ4780_CLK_COMPRESS	63
-#define JZ4780_CLK_AIC1		64
-#define JZ4780_CLK_GPVLC	65
-#define JZ4780_CLK_OTG1		66
-#define JZ4780_CLK_UART4	67
-#define JZ4780_CLK_AHBMON	68
-#define JZ4780_CLK_SMB4		69
-#define JZ4780_CLK_DES		70
-#define JZ4780_CLK_X2D		71
-#define JZ4780_CLK_CORE1	72
+#define JZ4780_CLK_MSCMUX		21
+#define JZ4780_CLK_MSC0			22
+#define JZ4780_CLK_MSC1			23
+#define JZ4780_CLK_MSC2			24
+#define JZ4780_CLK_UHC			25
+#define JZ4780_CLK_SSIPLL		26
+#define JZ4780_CLK_SSI			27
+#define JZ4780_CLK_CIMMCLK		28
+#define JZ4780_CLK_PCMPLL		29
+#define JZ4780_CLK_PCM			30
+#define JZ4780_CLK_GPU			31
+#define JZ4780_CLK_HDMI			32
+#define JZ4780_CLK_BCH			33
+#define JZ4780_CLK_NEMC			34
+#define JZ4780_CLK_OTG0			35
+#define JZ4780_CLK_SSI0			36
+#define JZ4780_CLK_SMB0			37
+#define JZ4780_CLK_SMB1			38
+#define JZ4780_CLK_SCC			39
+#define JZ4780_CLK_AIC			40
+#define JZ4780_CLK_TSSI0		41
+#define JZ4780_CLK_OWI			42
+#define JZ4780_CLK_KBC			43
+#define JZ4780_CLK_SADC			44
+#define JZ4780_CLK_UART0		45
+#define JZ4780_CLK_UART1		46
+#define JZ4780_CLK_UART2		47
+#define JZ4780_CLK_UART3		48
+#define JZ4780_CLK_SSI1			49
+#define JZ4780_CLK_SSI2			50
+#define JZ4780_CLK_PDMA			51
+#define JZ4780_CLK_GPS			52
+#define JZ4780_CLK_MAC			53
+#define JZ4780_CLK_SMB2			54
+#define JZ4780_CLK_CIM			55
+#define JZ4780_CLK_LCD			56
+#define JZ4780_CLK_TVE			57
+#define JZ4780_CLK_IPU			58
+#define JZ4780_CLK_DDR0			59
+#define JZ4780_CLK_DDR1			60
+#define JZ4780_CLK_SMB3			61
+#define JZ4780_CLK_TSSI1		62
+#define JZ4780_CLK_COMPRESS		63
+#define JZ4780_CLK_AIC1			64
+#define JZ4780_CLK_GPVLC		65
+#define JZ4780_CLK_OTG1			66
+#define JZ4780_CLK_UART4		67
+#define JZ4780_CLK_AHBMON		68
+#define JZ4780_CLK_SMB4			69
+#define JZ4780_CLK_DES			70
+#define JZ4780_CLK_X2D			71
+#define JZ4780_CLK_CORE1		72
 #define JZ4780_CLK_EXCLK_DIV512	73
-#define JZ4780_CLK_RTC		74
+#define JZ4780_CLK_RTC			74
 
 #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */
-- 
2.11.0

[PATCH 3/3] clk: Ingenic: Add RTC related clocks for Ingenic SoCs.

[周琰杰 (Zhou Yanjie)]

The RTC unit in the Ingenic SoCs has two clock sources, one
is from an external 32.768kHz clock, and the other is from an
external 24MHz/48MHz main clock that is divided by 512. The
choice of these two clocks is controlled by the ERCS bit in
the OPCR register. The RNG unit will also use this clock.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
 drivers/clk/ingenic/jz4780-cgu.c | 12 ++++++++++++
 drivers/clk/ingenic/x1000-cgu.c  | 13 +++++++++++++
 drivers/clk/ingenic/x1830-cgu.c  | 13 +++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 6c5b8029cc8a..288e9694285b 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -516,6 +516,18 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
 		.gate = { CGU_REG_CLKGR0, 1 },
 	},
 
+	[JZ4780_CLK_EXCLK_DIV512] = {
+		"exclk_div512", CGU_CLK_FIXDIV,
+		.parents = { JZ4780_CLK_EXCLK },
+		.fixdiv = { 512 },
+	},
+
+	[JZ4780_CLK_RTC] = {
+		"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
+		.parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
+		.mux = { CGU_REG_OPCR, 2, 1},
+	},
+
 	/* Gate-only clocks */
 
 	[JZ4780_CLK_NEMC] = {
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index 453f3323cb99..3cc37466ce6b 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -278,6 +278,19 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
 		.mux = { CGU_REG_SSICDR, 30, 1 },
 	},
 
+	[X1000_CLK_EXCLK_DIV512] = {
+		"exclk_div512", CGU_CLK_FIXDIV,
+		.parents = { X1000_CLK_EXCLK },
+		.fixdiv = { 512 },
+	},
+
+	[X1000_CLK_RTC] = {
+		"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
+		.parents = { X1000_CLK_EXCLK_DIV512, X1000_CLK_RTCLK },
+		.mux = { CGU_REG_OPCR, 2, 1},
+		.gate = { CGU_REG_CLKGR, 27 },
+	},
+
 	/* Gate-only clocks */
 
 	[X1000_CLK_EMC] = {
diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c
index a1b2ff0ee487..950aee243364 100644
--- a/drivers/clk/ingenic/x1830-cgu.c
+++ b/drivers/clk/ingenic/x1830-cgu.c
@@ -329,6 +329,19 @@ static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
 		.mux = { CGU_REG_SSICDR, 29, 1 },
 	},
 
+	[X1830_CLK_EXCLK_DIV512] = {
+		"exclk_div512", CGU_CLK_FIXDIV,
+		.parents = { X1830_CLK_EXCLK },
+		.fixdiv = { 512 },
+	},
+
+	[X1830_CLK_RTC] = {
+		"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
+		.parents = { X1830_CLK_EXCLK_DIV512, X1830_CLK_RTCLK },
+		.mux = { CGU_REG_OPCR, 2, 1},
+		.gate = { CGU_REG_CLKGR0, 29 },
+	},
+
 	/* Gate-only clocks */
 
 	[X1830_CLK_EMC] = {
-- 
2.11.0

Re: [PATCH 0/3] Add RTC related clocks for Ingenic SoCs.

[Stephen Boyd]

Quoting 周琰杰 (Zhou Yanjie) (2020-07-24 22:11:33)
> 1.Add RTC related clocks bindings for the JZ4780 SoC,
>   the X1000 SoC, and the X1830 SoC.
> 2.Add "XXXX_CLK_EXCLK_DIV512" and "XXXX_CLK_RTC" for
>   the JZ4780 SoC, the X1000 SoC, and the X1830 SoC.
> 
> 周琰杰 (Zhou Yanjie) (3):
>   dt-bindings: clock: Add RTC related clocks for Ingenic SoCs.
>   dt-bindings: clock: Add tabs to align code.
>   clk: Ingenic: Add RTC related clocks for Ingenic SoCs.
> 
>  drivers/clk/ingenic/jz4780-cgu.c       |  12 +++
>  drivers/clk/ingenic/x1000-cgu.c        |  13 +++
>  drivers/clk/ingenic/x1830-cgu.c        |  13 +++
>  include/dt-bindings/clock/jz4780-cgu.h | 144 +++++++++++++++++----------------

Thanks. Applied to clk-next.