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Tue, 28 Jul 2020 13:09:57 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 60DC7304B6D; Tue, 28 Jul 2020 15:09:56 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 2142029DE2958; Tue, 28 Jul 2020 15:09:56 +0200 (CEST) Date: Tue, 28 Jul 2020 15:09:56 +0200 From: Peter Zijlstra To: "Liang, Kan" Cc: acme@redhat.com, mingo@kernel.org, linux-kernel@vger.kernel.org, jolsa@kernel.org, eranian@google.com, alexander.shishkin@linux.intel.com, ak@linux.intel.com, like.xu@linux.intel.com Subject: Re: [PATCH V7 08/14] perf/x86/intel: Generic support for hardware TopDown metrics Message-ID: <20200728130956.GK10769@hirez.programming.kicks-ass.net> References: <20200723171117.9918-1-kan.liang@linux.intel.com> <20200723171117.9918-9-kan.liang@linux.intel.com> <20200724131906.GW119549@hirez.programming.kicks-ass.net> <20200724152755.GK43129@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 24, 2020 at 03:10:52PM -0400, Liang, Kan wrote: > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 6cb079e0c9d9..010ac74afc09 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -2405,27 +2405,18 @@ static u64 icl_update_topdown_event(struct > perf_event *event) > return slots; > } > > -static void intel_pmu_read_topdown_event(struct perf_event *event) > +static void intel_pmu_read_event(struct perf_event *event) > { > - struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); > - > - /* Only need to call update_topdown_event() once for group read. */ > - if ((cpuc->txn_flags & PERF_PMU_TXN_READ) && > - !is_slots_event(event)) > return; > > - perf_pmu_disable(event->pmu); > - x86_pmu.update_topdown_event(event); > - perf_pmu_enable(event->pmu); > -} > - > -static void intel_pmu_read_event(struct perf_event *event) > -{ > if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) > intel_pmu_auto_reload_read(event); > - else if (is_topdown_count(event) && x86_pmu.update_topdown_event) > - intel_pmu_read_topdown_event(event); > - else > + else if (is_slots_count(event) && x86_pmu.update_topdown_event) { > + perf_pmu_disable(event->pmu); > + x86_pmu.update_topdown_event(event); > + perf_pmu_enable(event->pmu); > + } else > x86_perf_event_update(event); > } I'm a little puzzled by this; what happens if you: fd = sys_perf_event_open(&attr_slots); fd1 = sys_perf_event_open(&attr_metric, .group_fd=fd); read(fd1); ?