[Intel-gfx] [PATCH v5 00/22] Introduce DG1

[Intel-gfx] [PATCH v5 00/22] Introduce DG1

[Lucas De Marchi]

v4:
- Remove already applied patches and rebase the rest
- Add new workarounds
- Add change to DMC_DEBUG register

v3:
- Make sure we don't bind the driver to the device while the driver is
  not complete. This should unblock us to have these basic patches
  merged so the next parts can be developed/refactored/implemented,
  particularly related to lmem.

  When we have these patches applied and lmem part working for at least
  a display-only driver we can make it bind again. This guarantees we
  don't regress.

- Remove most of the RKL patches. The only one I'm still carrying is the
  one for WAs as they are very similar to the ones for DG1.
  Particularly the patch for PLL on RKL was making CI for this series to
  fail, so untangle both and let them both continue the review process
  in parallel.

v2:
- Remove some wrong/unneeded patches
- Collect R-b
- Rebase

As in previous version, the RKL patches are here only for completeness
and avoid future conflicts, not to be reviewed/applied.

Original cover:
DG1 is a gen12 dgfx platform. This is the first batch of patches to
support it. It also depends on some in-flight patches adding RKL. In
order for this series to be compiled, I'm including them here.

While converting some of these patches to the current
intel_uncore/intel_de APIs I thought it could be useful to return the
previous value. The patch for that is included here, but I ended up
not using and it can be dropped if there is no interest.

Aditya Swarup (4):
  drm/i915/dg1: Add DPLL macros for DG1
  drm/i915/dg1: Add and setup DPLLs for DG1
  drm/i915/dg1: Enable DPLL for DG1
  drm/i915/dg1: Enable first 2 ports for DG1

Anshuman Gupta (2):
  drm/i915/dg1: DG1 does not support DC6
  drm/i915/dg1: Change DMC_DEBUG{1,2} registers

Clinton A Taylor (1):
  drm/i915/dg1: invert HPD pins

Lucas De Marchi (5):
  drm/i915/dg1: Define MOCS table for DG1
  drm/i915/dg1: add hpd interrupt handling
  drm/i915/dg1: gmbus pin mapping
  drm/i915/dg1: map/unmap pll clocks
  drm/i915/dg1: enable PORT C/D aka D/E

Matt Atwood (1):
  drm/i915/dg1: Load DMC

Matt Roper (6):
  drm/i915/dg1: Initialize RAWCLK properly
  drm/i915/dg1: Wait for pcode/uncore handshake at startup
  drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
  drm/i915/dg1: Update comp master/slave relationships for PHYs
  drm/i915/dg1: Update voltage swing tables for DP
  drm/i915/dg1: provide port/phy mapping for vbt

Stuart Summers (1):
  drm/i915/dg1: Add initial DG1 workarounds

Uma Shankar (1):
  drm/i915/dg1: Add DG1 power wells

Venkata Sandeep Dhanalakota (1):
  drm/i915/dg1: Increase mmio size to 4MB

 drivers/gpu/drm/i915/display/intel_bios.c     |  12 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  16 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    |   7 +-
 drivers/gpu/drm/i915/display/intel_csr.c      |  19 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 126 ++++++++++-
 drivers/gpu/drm/i915/display/intel_display.c  |  46 +++-
 .../drm/i915/display/intel_display_debugfs.c  |   9 +-
 .../drm/i915/display/intel_display_power.c    | 211 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  71 ++++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  17 ++
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  15 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     |   9 +-
 drivers/gpu/drm/i915/display/intel_hotplug.c  |   3 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_mocs.c          |  39 +++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 101 +++++++--
 drivers/gpu/drm/i915/i915_drv.c               |   3 +
 drivers/gpu/drm/i915/i915_irq.c               |  66 +++++-
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |  63 +++++-
 drivers/gpu/drm/i915/intel_pm.c               |  17 +-
 drivers/gpu/drm/i915/intel_sideband.c         |  15 ++
 drivers/gpu/drm/i915/intel_sideband.h         |   2 +
 drivers/gpu/drm/i915/intel_uncore.c           |   4 +
 24 files changed, 800 insertions(+), 77 deletions(-)

-- 
2.26.2

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[Intel-gfx] [PATCH v5 01/22] drm/i915/dg1: Initialize RAWCLK properly

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+.  Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.

For simplicity, let's just assume that this 38.4 MHz frequency will hold
true for other future platforms with "fake" PCH south displays and that
the CNP-style behavior will remain for other platforms with a real PCH.

Bspec: 49950
Bspec: 49309
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9d6cacbdb691..7722831346ba 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2680,6 +2680,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
 			       DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
 }
 
+static int dg1_rawclk(struct drm_i915_private *dev_priv)
+{
+	/*
+	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
+	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
+	 */
+	I915_WRITE(PCH_RAWCLK_FREQ,
+		   CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
+
+	return 38400;
+}
+
 static int cnp_rawclk(struct drm_i915_private *dev_priv)
 {
 	u32 rawclk;
@@ -2788,7 +2800,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 {
 	u32 freq;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		freq = dg1_rawclk(dev_priv);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
 		freq = cnp_rawclk(dev_priv);
 	else if (HAS_PCH_SPLIT(dev_priv))
 		freq = pch_rawclk(dev_priv);
-- 
2.26.2

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[Intel-gfx] [PATCH v5 02/22] drm/i915/dg1: Define MOCS table for DG1

[Lucas De Marchi]

DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).

Bspec: 45101

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b..7217c6e2087c 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
 	GEN11_MOCS_ENTRIES
 };
 
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+	/* Error */
+	MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+	/* UC */
+	MOCS_ENTRY(1, 0, L3_1_UC),
+
+	/* Reserved */
+	MOCS_ENTRY(2, 0, L3_0_DIRECT),
+	MOCS_ENTRY(3, 0, L3_0_DIRECT),
+	MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+	/* WB - L3 */
+	MOCS_ENTRY(5, 0, L3_3_WB),
+	/* WB - L3 50% */
+	MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+	/* WB - L3 25% */
+	MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+	/* WB - L3 12.5% */
+	MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+	/* HDC:L1 + L3 */
+	MOCS_ENTRY(48, 0, L3_3_WB),
+	/* HDC:L1 */
+	MOCS_ENTRY(49, 0, L3_1_UC),
+
+	/* HW Reserved */
+	MOCS_ENTRY(60, 0, L3_1_UC),
+	MOCS_ENTRY(61, 0, L3_1_UC),
+	MOCS_ENTRY(62, 0, L3_1_UC),
+	MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
 enum {
 	HAS_GLOBAL_MOCS = BIT(0),
 	HAS_ENGINE_MOCS = BIT(1),
@@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
 	unsigned int flags;
 
-	if (INTEL_GEN(i915) >= 12) {
+	if (IS_DG1(i915)) {
+		table->size = ARRAY_SIZE(dg1_mocs_table);
+		table->table = dg1_mocs_table;
+		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+	} else if (INTEL_GEN(i915) >= 12) {
 		table->size  = ARRAY_SIZE(tgl_mocs_table);
 		table->table = tgl_mocs_table;
 		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells

[Lucas De Marchi]

From: Uma Shankar <uma.shankar@intel.com>

Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.

Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.

DDIA, DDIB, TC1 and TC2 are the active ports on DG1.

Need to keep Transcoder C and D to Pipe Power wells, this is against
the spec but else hitting unclaimed register warnings (kept the logic
same as TGL)

Bspec: 49182

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 .../drm/i915/display/intel_display_power.c    | 201 +++++++++++++++++-
 1 file changed, 200 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 0c713e83274d..b51b82cb2398 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
 
+#define DG1_PW_5_POWER_DOMAINS (			\
+	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_4_POWER_DOMAINS (			\
+	DG1_PW_5_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_3_POWER_DOMAINS (			\
+	DG1_PW_4_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
+	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
+	BIT_ULL(POWER_DOMAIN_AUX_D) |		\
+	BIT_ULL(POWER_DOMAIN_AUX_E) |		\
+	BIT_ULL(POWER_DOMAIN_VGA) |			\
+	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS (			\
+	DG1_PW_3_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS (		\
+	DG1_PW_3_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
+
 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = i9xx_always_on_power_well_noop,
@@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
 	},
 };
 
+static const struct i915_power_well_desc dg1_power_wells[] = {
+	{
+		.name = "always-on",
+		.always_on = true,
+		.domains = POWER_DOMAIN_MASK,
+		.ops = &i9xx_always_on_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
+	{
+		.name = "power well 1",
+		/* Handled by the DMC firmware */
+		.always_on = true,
+		.domains = 0,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_1,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DC off",
+		.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+		.ops = &gen9_dc_off_power_well_ops,
+		.id = SKL_DISP_DC_OFF,
+	},
+	{
+		.name = "power well 2",
+		.domains = DG1_PW_2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = SKL_DISP_PW_2,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "power well 3",
+		.domains = DG1_PW_3_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = ICL_DISP_PW_3,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
+			.hsw.irq_pipe_mask = BIT(PIPE_B),
+			.hsw.has_vga = true,
+			.hsw.has_fuses = true,
+		},
+	},
+	{
+		.name = "DDI A IO",
+		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+		}
+	},
+	{
+		.name = "DDI B IO",
+		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+		}
+	},
+	{
+		.name = "DDI D TC1 IO",
+		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+		},
+	},
+	{
+		.name = "DDI E TC2 IO",
+		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_ddi_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+		},
+	},
+	{
+		.name = "AUX A",
+		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+		},
+	},
+	{
+		.name = "AUX B",
+		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+		},
+	},
+	{
+		.name = "AUX D TC1",
+		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "AUX E TC2",
+		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
+		.ops = &icl_aux_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &icl_aux_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+			.hsw.is_tc_tbt = false,
+		},
+	},
+	{
+		.name = "power well 4",
+		.domains = DG1_PW_4_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_C),
+		}
+	},
+	{
+		.name = "power well 5",
+		.domains = DG1_PW_5_POWER_DOMAINS,
+		.ops = &hsw_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+		{
+			.hsw.regs = &hsw_power_well_regs,
+			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
+			.hsw.has_fuses = true,
+			.hsw.irq_pipe_mask = BIT(PIPE_D),
+		},
+	},
+};
+
 static int
 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
 				   int disable_power_well)
@@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
 	 */
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		err = set_power_wells(power_domains, dg1_power_wells);
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		err = set_power_wells(power_domains, rkl_power_wells);
 	} else if (IS_GEN(dev_priv, 12)) {
 		err = set_power_wells(power_domains, tgl_power_wells);
-- 
2.26.2

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[Intel-gfx] [PATCH v5 04/22] drm/i915/dg1: Increase mmio size to 4MB

[Lucas De Marchi]

From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>

On dgfx register range has been extended to go up to 4MB.

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f5edee17902a..8f9c82aa7338 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
 	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 	 * the register BAR remains the same size for all the earlier
 	 * generations up to Ironlake.
+	 * For dgfx chips register range is expanded to 4MB.
 	 */
 	if (INTEL_GEN(i915) < 5)
 		mmio_size = 512 * 1024;
+	else if (IS_DGFX(i915))
+		mmio_size = 4 * 1024 * 1024;
 	else
 		mmio_size = 2 * 1024 * 1024;
+
 	uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
 	if (uncore->regs == NULL) {
 		drm_err(&i915->drm, "failed to map registers\n");
-- 
2.26.2

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[Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshaking is complete.

The bspec doesn't give guidance on how long we may need to wait for this
handshaking to complete.  For now, let's just set a really long timeout;
if we still don't get a completion status by the end of that timeout,
we'll just continue on and hope for the best.

Bspec: 52065
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c       |  3 +++
 drivers/gpu/drm/i915/i915_reg.h       |  3 +++
 drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/intel_sideband.h |  2 ++
 4 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5fd5af4bc855..5473bfe9126c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -85,6 +85,7 @@
 #include "intel_gvt.h"
 #include "intel_memory_region.h"
 #include "intel_pm.h"
+#include "intel_sideband.h"
 #include "vlv_suspend.h"
 
 static struct drm_driver driver;
@@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 	 */
 	intel_dram_detect(dev_priv);
 
+	intel_pcode_init(dev_priv);
+
 	intel_bw_init_hw(dev_priv);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0d31f3bf634..3767b32127da 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9245,6 +9245,9 @@ enum {
 #define     GEN9_SAGV_DISABLE			0x0
 #define     GEN9_SAGV_IS_DISABLED		0x1
 #define     GEN9_SAGV_ENABLE			0x3
+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
+#define     DG1_UNCORE_INIT_COMPLETE		0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 916ccd1c0e96..8b093525240d 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
 	return ret ? ret : status;
 #undef COND
 }
+
+void intel_pcode_init(struct drm_i915_private *i915)
+{
+	int ret;
+
+	if (!IS_DGFX(i915))
+		return;
+
+	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
+				DG1_CHECK_UNCORE_INIT_STATUS,
+				DG1_UNCORE_INIT_COMPLETE,
+				DG1_UNCORE_INIT_COMPLETE, 50);
+	if (ret)
+		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 7fb95745a444..094c7b19c5d4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
 		      u32 reply_mask, u32 reply, int timeout_base_ms);
 
+void intel_pcode_init(struct drm_i915_private *i915);
+
 #endif /* _INTEL_SIDEBAND_H */
-- 
2.26.2

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[Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1

[Lucas De Marchi]

From: Aditya Swarup <aditya.swarup@intel.com>

DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.

Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.

Bspec: 50288, 50299

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 17 ++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 5d9a2bc371e7..205542fb8dc7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -154,6 +154,23 @@ enum intel_dpll_id {
 	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
 	 */
 	DPLL_ID_TGL_MGPLL6 = 8,
+
+	/**
+	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
+	 */
+	DPLL_ID_DG1_DPLL0 = 0,
+	/**
+	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
+	 */
+	DPLL_ID_DG1_DPLL1 = 1,
+	/**
+	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
+	 */
+	DPLL_ID_DG1_DPLL2 = 2,
+	/**
+	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
+	 */
+	DPLL_ID_DG1_DPLL3 = 3,
 };
 
 #define I915_NUM_PLLS 9
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3767b32127da..986e31af7763 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
 #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
-#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
+#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
+
 
 /*
  * Device info offset array based helpers for groups of registers with unevenly
@@ -10547,6 +10548,20 @@ enum skl_power_gate {
 #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
 						  _TGL_DPLL1_CFGCR1)
 
+#define _DG1_DPLL2_CFGCR0		0x16C284
+#define _DG1_DPLL3_CFGCR0		0x16C28C
+#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
+						   _TGL_DPLL1_CFGCR0, \
+						   _DG1_DPLL2_CFGCR0, \
+						   _DG1_DPLL3_CFGCR0)
+
+#define _DG1_DPLL2_CFGCR1               0x16C288
+#define _DG1_DPLL3_CFGCR1               0x16C290
+#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
+						   _TGL_DPLL1_CFGCR1, \
+						   _DG1_DPLL2_CFGCR1, \
+						   _DG1_DPLL3_CFGCR1)
+
 #define _DKL_PHY1_BASE			0x168000
 #define _DKL_PHY2_BASE			0x169000
 #define _DKL_PHY3_BASE			0x16A000
-- 
2.26.2

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[Intel-gfx] [PATCH v5 07/22] drm/i915/dg1: Add and setup DPLLs for DG1

[Lucas De Marchi]

From: Aditya Swarup <aditya.swarup@intel.com>

Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++--
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 81ab975fe4f0..39a53aa0b233 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3512,7 +3512,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 
 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		if (port == PORT_D || port == PORT_E) {
+			dpll_mask =
+				BIT(DPLL_ID_DG1_DPLL2) |
+				BIT(DPLL_ID_DG1_DPLL3);
+		} else {
+			dpll_mask =
+				BIT(DPLL_ID_DG1_DPLL0) |
+				BIT(DPLL_ID_DG1_DPLL1);
+		}
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
@@ -3808,7 +3818,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		hw_state->cfgcr0 = intel_de_read(dev_priv,
 						 RKL_DPLL_CFGCR0(id));
 		hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3866,7 +3879,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
 	const enum intel_dpll_id id = pll->info->id;
 	i915_reg_t cfgcr0_reg, cfgcr1_reg;
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
+		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		cfgcr0_reg = RKL_DPLL_CFGCR0(id);
 		cfgcr1_reg = RKL_DPLL_CFGCR1(id);
 	} else if (INTEL_GEN(dev_priv) >= 12) {
@@ -4316,6 +4332,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info dg1_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
+	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
+	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr dg1_pll_mgr = {
+	.dpll_info = dg1_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4329,7 +4360,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_DG1(dev_priv))
+		dpll_mgr = &dg1_pll_mgr;
+	else if (IS_ROCKETLAKE(dev_priv))
 		dpll_mgr = &rkl_pll_mgr;
 	else if (INTEL_GEN(dev_priv) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 08/22] drm/i915/dg1: Enable DPLL for DG1

[Lucas De Marchi]

From: Aditya Swarup <aditya.swarup@intel.com>

Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.

Bspec: 49443, 49206

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ++++++++++++-------
 drivers/gpu/drm/i915/i915_reg.h               |  4 +++
 2 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 39a53aa0b233..a47b37cc24bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3855,12 +3855,14 @@ static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
 				   struct intel_shared_dpll *pll,
 				   struct intel_dpll_hw_state *hw_state)
 {
-	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+	i915_reg_t enable_reg;
 
-	if (IS_ELKHARTLAKE(dev_priv) &&
-	    pll->info->id == DPLL_ID_EHL_DPLL4) {
+	if (IS_DG1(dev_priv))
+		enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+	else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4)
 		enable_reg = MG_PLL_ENABLE(0);
-	}
+	else
+		enable_reg = CNL_DPLL_ENABLE(pll->info->id);
 
 	return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
 }
@@ -4061,10 +4063,12 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
 static void combo_pll_enable(struct drm_i915_private *dev_priv,
 			     struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+	i915_reg_t enable_reg;
 
-	if (IS_ELKHARTLAKE(dev_priv) &&
-	    pll->info->id == DPLL_ID_EHL_DPLL4) {
+	if (IS_DG1(dev_priv)) {
+		enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+	} else if (IS_ELKHARTLAKE(dev_priv) &&
+		 pll->info->id == DPLL_ID_EHL_DPLL4) {
 		enable_reg = MG_PLL_ENABLE(0);
 
 		/*
@@ -4074,6 +4078,8 @@ static void combo_pll_enable(struct drm_i915_private *dev_priv,
 		 */
 		pll->wakeref = intel_display_power_get(dev_priv,
 						       POWER_DOMAIN_DPLL_DC_OFF);
+	} else {
+		enable_reg = CNL_DPLL_ENABLE(pll->info->id);
 	}
 
 	icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4173,16 +4179,20 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
 static void combo_pll_disable(struct drm_i915_private *dev_priv,
 			      struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+	i915_reg_t enable_reg;
 
-	if (IS_ELKHARTLAKE(dev_priv) &&
-	    pll->info->id == DPLL_ID_EHL_DPLL4) {
+	if (IS_DG1(dev_priv)) {
+		enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+	} else if (IS_ELKHARTLAKE(dev_priv) &&
+		   pll->info->id == DPLL_ID_EHL_DPLL4) {
 		enable_reg = MG_PLL_ENABLE(0);
 		icl_pll_disable(dev_priv, pll, enable_reg);
 
 		intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
 					pll->wakeref);
 		return;
+	} else {
+		enable_reg = CNL_DPLL_ENABLE(pll->info->id);
 	}
 
 	icl_pll_disable(dev_priv, pll, enable_reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 986e31af7763..a393a49cf493 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10332,6 +10332,10 @@ enum skl_power_gate {
 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
 					   _MG_PLL2_ENABLE)
 
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
-- 
2.26.2

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[Intel-gfx] [PATCH v5 09/22] drm/i915/dg1: add hpd interrupt handling

[Lucas De Marchi]

DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.

v2: Also change intel_hpd_pin_default() to include DG1 mapping

Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hotplug.c |  3 +-
 drivers/gpu/drm/i915/i915_irq.c              | 57 +++++++++++++++++---
 drivers/gpu/drm/i915/i915_reg.h              |  8 +++
 3 files changed, 61 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 3f1d7b804a66..1838e3c87e73 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -95,7 +95,8 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
 	 * shold be HPD_PORT_{D,E} rather than {C,D}.  Note that this differs
 	 * from the behavior of both TGL+TGP and RKL+CMP.
 	 */
-	if (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv))
+	if (IS_DG1(dev_priv) ||
+	    (IS_ROCKETLAKE(dev_priv) && HAS_PCH_TGP(dev_priv)))
 		return HPD_PORT_A + port - PORT_A;
 
 	switch (phy) {
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1fa67700d8f4..e8bdc52c94bb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -167,6 +167,13 @@ static const u32 hpd_tgp[HPD_NUM_PINS] = {
 	[HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
 };
 
+static const u32 hpd_dg1_sde[HPD_NUM_PINS] = {
+	[HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PHY_A),
+	[HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PHY_B),
+	[HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(PHY_C),
+	[HPD_PORT_E] = SDE_DDI_HOTPLUG_ICP(PHY_D),
+};
+
 static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 {
 	struct i915_hotplug *hpd = &dev_priv->hotplug;
@@ -193,10 +200,13 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
 	else
 		hpd->hpd = hpd_ilk;
 
-	if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
+	if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) &&
+	    (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
 		return;
 
-	if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
+	if (HAS_PCH_DG1(dev_priv))
+		hpd->pch_hpd = hpd_dg1_sde;
+	else if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
 		hpd->pch_hpd = hpd_tgp;
 	else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
 		hpd->pch_hpd = hpd_icp;
@@ -1145,6 +1155,22 @@ static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
 	}
 }
 
+static bool dg1_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
+{
+	switch (pin) {
+	case HPD_PORT_A:
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
+	case HPD_PORT_B:
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
+	case HPD_PORT_D:
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
+	case HPD_PORT_E:
+		return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_D);
+	default:
+		return false;
+	}
+}
+
 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
 {
 	switch (pin) {
@@ -1893,13 +1919,20 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 	u32 ddi_hotplug_trigger, tc_hotplug_trigger;
 	u32 pin_mask = 0, long_mask = 0;
 	bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
+	bool (*ddi_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
 
-	if (HAS_PCH_TGP(dev_priv)) {
+	if (HAS_PCH_DG1(dev_priv)) {
+		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_DG1;
+		ddi_port_hotplug_long_detect = dg1_ddi_port_hotplug_long_detect;
+		tc_hotplug_trigger = 0;
+	} else if (HAS_PCH_TGP(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+		ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
 		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
 		tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
 	} else if (HAS_PCH_JSP(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
+		ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
 		tc_hotplug_trigger = 0;
 	} else if (HAS_PCH_MCC(dev_priv)) {
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
@@ -1911,6 +1944,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 			 INTEL_PCH_TYPE(dev_priv));
 
 		ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+		ddi_port_hotplug_long_detect = icp_ddi_port_hotplug_long_detect;
 		tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
 		tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
 	}
@@ -1924,7 +1958,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
 		intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
 				   ddi_hotplug_trigger, dig_hotplug_reg,
 				   dev_priv->hotplug.pch_hpd,
-				   icp_ddi_port_hotplug_long_detect);
+				   ddi_port_hotplug_long_detect);
 	}
 
 	if (tc_hotplug_trigger) {
@@ -3145,6 +3179,13 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 			  TGP_DDI_HPD_ENABLE_MASK, 0);
 }
 
+static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
+{
+	icp_hpd_irq_setup(dev_priv,
+			  SDE_DDI_MASK_DG1, 0,
+			  DG1_DDI_HPD_ENABLE_MASK, 0);
+}
+
 static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
 {
 	u32 hotplug;
@@ -3533,7 +3574,9 @@ static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
 	gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
 	I915_WRITE(SDEIMR, ~mask);
 
-	if (HAS_PCH_TGP(dev_priv))
+	if (HAS_PCH_DG1(dev_priv))
+		icp_hpd_detection_setup(dev_priv, DG1_DDI_HPD_ENABLE_MASK, 0);
+	else if (HAS_PCH_TGP(dev_priv))
 		icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
 					TGP_TC_HPD_ENABLE_MASK);
 	else if (HAS_PCH_JSP(dev_priv))
@@ -4049,7 +4092,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		if (I915_HAS_HOTPLUG(dev_priv))
 			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
 	} else {
-		if (HAS_PCH_JSP(dev_priv))
+		if (HAS_PCH_DG1(dev_priv))
+			dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+		else if (HAS_PCH_JSP(dev_priv))
 			dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
 		else if (HAS_PCH_MCC(dev_priv))
 			dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a393a49cf493..9d0756efe915 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8249,6 +8249,10 @@ enum {
 					 SDE_TC_HOTPLUG_ICP(PORT_TC3) | \
 					 SDE_TC_HOTPLUG_ICP(PORT_TC2) | \
 					 SDE_TC_HOTPLUG_ICP(PORT_TC1))
+#define SDE_DDI_MASK_DG1		(SDE_DDI_HOTPLUG_ICP(PORT_D) | \
+					 SDE_DDI_HOTPLUG_ICP(PORT_C) | \
+					 SDE_DDI_HOTPLUG_ICP(PORT_B) | \
+					 SDE_DDI_HOTPLUG_ICP(PORT_A))
 
 #define SDEISR  _MMIO(0xc4000)
 #define SDEIMR  _MMIO(0xc4004)
@@ -8448,6 +8452,10 @@ enum {
 #define TGP_TC_HPD_ENABLE_MASK		(ICP_TC_HPD_ENABLE(PORT_TC6) | \
 					 ICP_TC_HPD_ENABLE(PORT_TC5) | \
 					 ICP_TC_HPD_ENABLE_MASK)
+#define DG1_DDI_HPD_ENABLE_MASK		(SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_D) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_C) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_B) | \
+					 SHOTPLUG_CTL_DDI_HPD_ENABLE(PORT_A))
 
 #define _PCH_DPLL_A              0xc6014
 #define _PCH_DPLL_B              0xc6018
-- 
2.26.2

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[Intel-gfx] [PATCH v5 10/22] drm/i915/dg1: invert HPD pins

[Lucas De Marchi]

From: Clinton A Taylor <clinton.a.taylor@intel.com>

HPD pins are inverted for DG1 platform.

Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e8bdc52c94bb..93367221d208 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3181,6 +3181,15 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
+	u32 val;
+
+	val = I915_READ(SOUTH_CHICKEN1);
+	val |= (INVERT_DDIA_HPD |
+		INVERT_DDIB_HPD |
+		INVERT_DDIC_HPD |
+		INVERT_DDID_HPD);
+	I915_WRITE(SOUTH_CHICKEN1, val);
+
 	icp_hpd_irq_setup(dev_priv,
 			  SDE_DDI_MASK_DG1, 0,
 			  DG1_DDI_HPD_ENABLE_MASK, 0);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9d0756efe915..bbaa64336ada 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8716,6 +8716,10 @@ enum {
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDID_HPD			(1 << 18)
+#define  INVERT_DDIC_HPD			(1 << 17)
+#define  INVERT_DDIB_HPD			(1 << 16)
+#define  INVERT_DDIA_HPD			(1 << 15)
 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-- 
2.26.2

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[Intel-gfx] [PATCH v5 11/22] drm/i915/dg1: gmbus pin mapping

[Lucas De Marchi]

Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.

The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.

From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9
mapping as in ICL/TGL.

BSpec: 49311, 49945, 20124

Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c  |  4 +++-
 drivers/gpu/drm/i915/display/intel_gmbus.c | 15 +++++++++++++--
 drivers/gpu/drm/i915/display/intel_hdmi.c  |  9 ++++++++-
 3 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index c53c85d38fa5..b6a0f5e5a9a6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1602,7 +1602,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)
 	const u8 *ddc_pin_map;
 	int n_entries;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) {
+		return vbt_pin;
+	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
 		ddc_pin_map = icp_ddc_pin_map;
 		n_entries = ARRAY_SIZE(icp_ddc_pin_map);
 	} else if (HAS_PCH_CNP(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a8d119b6b45c..528e48658340 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -90,11 +90,20 @@ static const struct gmbus_pin gmbus_pins_icp[] = {
 	[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
 };
 
+static const struct gmbus_pin gmbus_pins_dg1[] = {
+	[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
+	[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
+	[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
+	[GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
+};
+
 /* pin is expected to be valid */
 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
 					     unsigned int pin)
 {
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		return &gmbus_pins_dg1[pin];
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		return &gmbus_pins_icp[pin];
 	else if (HAS_PCH_CNP(dev_priv))
 		return &gmbus_pins_cnp[pin];
@@ -113,7 +122,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
 {
 	unsigned int size;
 
-	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		size = ARRAY_SIZE(gmbus_pins_dg1);
+	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
 		size = ARRAY_SIZE(gmbus_pins_icp);
 	else if (HAS_PCH_CNP(dev_priv))
 		size = ARRAY_SIZE(gmbus_pins_cnp);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index de2ce5632b94..7a20695722cb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3110,6 +3110,11 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
 	return GMBUS_PIN_1_BXT + phy;
 }
 
+static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
+{
+	return intel_port_to_phy(dev_priv, port) + 1;
+}
+
 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
 			      enum port port)
 {
@@ -3147,7 +3152,9 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
 		return ddc_pin;
 	}
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
+	else if (IS_ROCKETLAKE(dev_priv))
 		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
 	else if (HAS_PCH_MCC(dev_priv))
 		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
-- 
2.26.2

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[Intel-gfx] [PATCH v5 12/22] drm/i915/dg1: Enable first 2 ports for DG1

[Lucas De Marchi]

From: Aditya Swarup <aditya.swarup@intel.com>

Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db2a5a1a9b35..1d46c5712b3b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7231,6 +7231,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
+	else if (IS_DG1(dev_priv))
+		/* FIXME: Enable only two ports for now */
+		return phy <= PHY_B;
 	else if (IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
 	else if (IS_ELKHARTLAKE(dev_priv))
@@ -7243,7 +7246,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_ROCKETLAKE(dev_priv) || IS_DG1(dev_priv))
 		return false;
 	else if (INTEL_GEN(dev_priv) >= 12)
 		return phy >= PHY_D && phy <= PHY_I;
@@ -16852,7 +16855,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))
 		return;
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		/* FIXME: Enable only two ports for now */
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_D);	/* DDI TC1 */
-- 
2.26.2

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[Intel-gfx] [PATCH v5 13/22] drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B.  It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform.  Let's extend the EHL/RKL
logic that conditionally skips PHY_MISC usage to DG1 as well.

Bspec: 50107
Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d88f91038428..68137d4500b9 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -189,7 +189,8 @@ static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy)
 	 * other combo PHY's.
 	 */
 	if (IS_ELKHARTLAKE(i915) ||
-	    IS_ROCKETLAKE(i915))
+	    IS_ROCKETLAKE(i915) ||
+	    IS_DG1(i915))
 		return phy < PHY_C;
 
 	return true;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 14/22] drm/i915/dg1: Update comp master/slave relationships for PHYs

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

As with RKL, DG1's PHY C acts as a comp master for PHY D.

Bspec: 49291
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 68137d4500b9..d44109ba6603 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -243,14 +243,14 @@ static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy)
 	 *
 	 * ICL,TGL:
 	 *   A(master) -> B(slave), C(slave)
-	 * RKL:
+	 * RKL,DG1:
 	 *   A(master) -> B(slave)
 	 *   C(master) -> D(slave)
 	 *
 	 * We must set the IREFGEN bit for any PHY acting as a master
 	 * to another PHY.
 	 */
-	if (IS_ROCKETLAKE(dev_priv) && phy == PHY_C)
+	if ((IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) && phy == PHY_C)
 		return true;
 
 	return phy == PHY_A;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.

Bspec: 49291
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 714b2bc96f23..c19d5a375eba 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
 };
 
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */
+	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
+	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */
+	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
+	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
+	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
+	{ 0xC, 0x60, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */
+	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 600   900      3.5   */
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
+};
+
+static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
+						/* NT mV Trans mV db    */
+	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */
+	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
+	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */
+	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
+	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
+	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
+	{ 0xC, 0x58, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */
+	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
+	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
+};
+
 struct icl_mg_phy_ddi_buf_trans {
 	u32 cri_txdeemph_override_11_6;
 	u32 cri_txdeemph_override_5_0;
@@ -1034,6 +1062,12 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
 		return icl_combo_phy_ddi_translations_edp_hbr2;
+	} else if (IS_DG1(dev_priv) && rate > 270000) {
+		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
+		return dg1_combo_phy_ddi_translations_dp_hbr2;
+	} else if (IS_DG1(dev_priv)) {
+		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
+		return dg1_combo_phy_ddi_translations_dp_hbr;
 	}
 
 	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
-- 
2.26.2

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[Intel-gfx] [PATCH v5 16/22] drm/i915/dg1: provide port/phy mapping for vbt

[Lucas De Marchi]

From: Matt Roper <matthew.d.roper@intel.com>

As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index b6a0f5e5a9a6..2516f561fb8d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1673,7 +1673,7 @@ static enum port dvo_port_to_port(struct drm_i915_private *dev_priv,
 		[PORT_E] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 },
 	};
 
-	if (IS_ROCKETLAKE(dev_priv))
+	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping),
 					  ARRAY_SIZE(rkl_port_mapping[0]),
 					  rkl_port_mapping,
@@ -2638,10 +2638,12 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv,
 		aux_ch = AUX_CH_B;
 		break;
 	case DP_AUX_C:
-		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_D : AUX_CH_C;
+		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+			AUX_CH_D : AUX_CH_C;
 		break;
 	case DP_AUX_D:
-		aux_ch = IS_ROCKETLAKE(dev_priv) ? AUX_CH_E : AUX_CH_D;
+		aux_ch = (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) ?
+			AUX_CH_E : AUX_CH_D;
 		break;
 	case DP_AUX_E:
 		aux_ch = AUX_CH_E;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 17/22] drm/i915/dg1: map/unmap pll clocks

[Lucas De Marchi]

DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functions for DG1 since it doesn't share much with ICL/TGL
anymore.

The previous values were correct for PHY A and B since they were using
the same register as before and the bitfields were matching.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c     | 92 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display.c | 25 +++++-
 drivers/gpu/drm/i915/i915_reg.h              | 15 ++++
 3 files changed, 128 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c19d5a375eba..8bc89711349b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2893,6 +2893,38 @@ static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+static void dg1_map_plls_to_ports(struct intel_encoder *encoder,
+				  const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+	u32 val;
+
+	/*
+	 * If we fail this, something went very wrong: first 2 PLLs should be
+	 * used by first 2 phys and last 2 PLLs by last phys
+	 */
+	if (WARN_ON((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
+		    (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
+		return;
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+	WARN_ON((val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+
+	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+	val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
+	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+	intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+
+	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *crtc_state)
 {
@@ -2940,6 +2972,19 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+static void dg1_unmap_plls_to_ports(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+	mutex_lock(&dev_priv->dpll.lock);
+
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+
+	mutex_unlock(&dev_priv->dpll.lock);
+}
+
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -2955,6 +3000,40 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->dpll.lock);
 }
 
+static void dg1_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
+				      u32 port_mask, bool ddi_clk_needed)
+{
+	enum port port;
+	u32 val;
+
+	for_each_port_masked(port, port_mask) {
+		enum phy phy = intel_port_to_phy(dev_priv, port);
+		bool ddi_clk_off;
+
+		val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
+		ddi_clk_off = val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+
+		if (ddi_clk_needed == !ddi_clk_off)
+			continue;
+
+		/*
+		 * Punt on the case now where clock is gated, but it would
+		 * be needed by the port. Something else is really broken then.
+		 */
+		if (ddi_clk_needed) {
+			WARN(1, "ddi_clk_needed=%u ddi_clk_off=%u phy=%u\n",
+			     ddi_clk_needed, ddi_clk_off, phy);
+			continue;
+		}
+
+		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+			 phy_name(phy));
+
+		val |= DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+		intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+	}
+}
+
 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
 				      u32 port_mask, bool ddi_clk_needed)
 {
@@ -3037,7 +3116,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		ddi_clk_needed = false;
 	}
 
-	icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+	if (IS_DG1(dev_priv))
+		dg1_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
+	else
+		icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
 }
 
 static void intel_ddi_clk_select(struct intel_encoder *encoder,
@@ -3562,7 +3644,9 @@ static void intel_ddi_pre_enable(struct intel_atomic_state *state,
 
 	drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_DG1(dev_priv))
+		dg1_map_plls_to_ports(encoder, crtc_state);
+	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_map_plls_to_ports(encoder, crtc_state);
 
 	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -3748,7 +3832,9 @@ static void intel_ddi_post_disable(struct intel_atomic_state *state,
 		intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
 					  old_conn_state);
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_DG1(dev_priv))
+		dg1_unmap_plls_to_ports(encoder);
+	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_unmap_plls_to_ports(encoder);
 
 	if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1d46c5712b3b..b8870bc3814d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10782,6 +10782,27 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc,
 	return 0;
 }
 
+static void dg1_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
+			    struct intel_crtc_state *pipe_config)
+{
+	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
+	enum intel_dpll_id id;
+	u32 val;
+
+	val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy))
+		& DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+	id = DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy);
+
+	if (WARN_ON(id > DPLL_ID_DG1_DPLL3))
+		return;
+
+	pipe_config->icl_port_dplls[port_dpll_id].pll =
+		intel_get_shared_dpll_by_id(dev_priv, id);
+
+	icl_set_active_port_dpll(pipe_config, port_dpll_id);
+}
+
 static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
 			    struct intel_crtc_state *pipe_config)
 {
@@ -11090,7 +11111,9 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc,
 			port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 11)
+	if (IS_DG1(dev_priv))
+		dg1_get_ddi_pll(dev_priv, port, pipe_config);
+	else if (INTEL_GEN(dev_priv) >= 11)
 		icl_get_ddi_pll(dev_priv, port, pipe_config);
 	else if (IS_CANNONLAKE(dev_priv))
 		cnl_get_ddi_pll(dev_priv, port, pipe_config);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bbaa64336ada..79edada25ce1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -230,12 +230,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _TRANS(tran, a, b)		_PICK_EVEN(tran, a, b)
 #define _PORT(port, a, b)		_PICK_EVEN(port, a, b)
 #define _PLL(pll, a, b)			_PICK_EVEN(pll, a, b)
+#define _PHY(phy, a, b)			_PICK_EVEN(phy, a, b)
 
 #define _MMIO_PIPE(pipe, a, b)		_MMIO(_PIPE(pipe, a, b))
 #define _MMIO_PLANE(plane, a, b)	_MMIO(_PLANE(plane, a, b))
 #define _MMIO_TRANS(tran, a, b)		_MMIO(_TRANS(tran, a, b))
 #define _MMIO_PORT(port, a, b)		_MMIO(_PORT(port, a, b))
 #define _MMIO_PLL(pll, a, b)		_MMIO(_PLL(pll, a, b))
+#define _MMIO_PHY(phy, a, b)		_MMIO(_PHY(phy, a, b))
 
 #define _PHY3(phy, ...)			_PICK(phy, __VA_ARGS__)
 
@@ -10310,6 +10312,7 @@ enum skl_power_gate {
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
 #define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
 
+/* ICL Clocks */
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	REG_BIT((phy) + 10)
@@ -10325,6 +10328,18 @@ enum skl_power_gate {
 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
 	((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 
+/* DG1 Clocks */
+#define _DG1_DPCLKA_CFGCR0			0x164280
+#define _DG1_DPCLKA1_CFGCR0			0x16C280
+#define DG1_DPCLKA_CFGCR0(phy)			_MMIO_PHY((phy) / 2, \
+							  _DG1_DPCLKA_CFGCR0, \
+							  _DG1_DPCLKA1_CFGCR0)
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)             (1 << (10 + ((phy) % 2)))
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)        (0x3 << (((phy) % 2) * 2))
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)        (((pll) % 2) << (((phy) % 2)) * 2)
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+	  ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))
+
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
 #define DPLL1_ENABLE		0x46014
-- 
2.26.2

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[Intel-gfx] [PATCH v5 18/22] drm/i915/dg1: enable PORT C/D aka D/E

[Lucas De Marchi]

For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the index of A, B, D and E. However in some places this is
not true:

- VBT: uses C and D and have to be mapped to D/E

- IO/Combo: uses C and D, but we already differentiate those when
  we created the phy vs port distinction.

Ths additional mapping for VBT and phy are already covered in previous
patches, so now we can initialize the DDI as D/E.

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b8870bc3814d..73a530a66af5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7231,10 +7231,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (phy == PHY_NONE)
 		return false;
-	else if (IS_DG1(dev_priv))
-		/* FIXME: Enable only two ports for now */
-		return phy <= PHY_B;
-	else if (IS_ROCKETLAKE(dev_priv))
+	else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
 		return phy <= PHY_D;
 	else if (IS_ELKHARTLAKE(dev_priv))
 		return phy <= PHY_C;
@@ -7258,7 +7255,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 
 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
 {
-	if (IS_ROCKETLAKE(i915) && port >= PORT_D)
+	if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_D)
 		return (enum phy)port - 1;
 	else if (IS_ELKHARTLAKE(i915) && port == PORT_D)
 		return PHY_A;
@@ -16879,9 +16876,18 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		return;
 
 	if (IS_DG1(dev_priv)) {
-		/* FIXME: Enable only two ports for now */
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
+
+		/*
+		 * Bspec lists the ports as A, B, C (USBC1) and D (USBC2).
+		 * However from the Display Engine perspective all registers are
+		 * actually wired to handle C and D as offsets of D/E. Instead
+		 * of fighting all our macros for handling them specially for
+		 * DG1, just call them D/E
+		 */
+		intel_ddi_init(dev_priv, PORT_D);
+		intel_ddi_init(dev_priv, PORT_E);
 	} else if (IS_ROCKETLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-- 
2.26.2

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[Intel-gfx] [PATCH v5 19/22] drm/i915/dg1: Load DMC

[Lucas De Marchi]

From: Matt Atwood <matthew.s.atwood@intel.com>

Add support to load DMC v2.0.2 on DG1

While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.

Bpec: 49230

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index f22a7645c249..ccf13ea627d7 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -38,15 +38,19 @@
  * low-power state and comes back to normal.
  */
 
-#define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
+#define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
+#define DG1_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
+MODULE_FIRMWARE(DG1_CSR_PATH);
 
 #define RKL_CSR_PATH			"i915/rkl_dmc_ver2_01.bin"
 #define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)
+#define RKL_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
 #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_06.bin"
 #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 6)
-#define TGL_CSR_MAX_FW_SIZE		0x6000
+#define TGL_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 MODULE_FIRMWARE(TGL_CSR_PATH);
 
 #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
@@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_csr_runtime_pm_get(dev_priv);
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		csr->fw_path = DG1_CSR_PATH;
+		csr->required_version = DG1_CSR_VERSION_REQUIRED;
+		csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		csr->fw_path = RKL_CSR_PATH;
 		csr->required_version = RKL_CSR_VERSION_REQUIRED;
-		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+		csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		csr->fw_path = TGL_CSR_PATH;
 		csr->required_version = TGL_CSR_VERSION_REQUIRED;
-		/* Allow to load fw via parameter using the last known size */
-		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+		csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
 	} else if (IS_GEN(dev_priv, 11)) {
 		csr->fw_path = ICL_CSR_PATH;
 		csr->required_version = ICL_CSR_VERSION_REQUIRED;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 20/22] drm/i915/dg1: Add initial DG1 workarounds

[Lucas De Marchi]

From: Stuart Summers <stuart.summers@intel.com>

DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.

Media power gating should not be applied so we just set it to
nop_init_clock_gating().

v2: Corrected location of Wa_1408615072 (JohnH).

v3: Aplying WAs 1606700617, 18011464164 and 22010931296 to DG1 (José)

v4: Add Wa_22010271021 (Anusha)
- s/Wa_14010096844/Wa_1409836686  (Anusha)

BSpec: 53508

Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_sprite.c   |   4 +-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 101 +++++++++++++++---
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |  10 +-
 drivers/gpu/drm/i915/intel_pm.c               |  17 ++-
 6 files changed, 114 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b51b82cb2398..21f39c94056e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5462,8 +5462,9 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
 	unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
 	int config, i;
 
-	if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
-		/* Wa_1409767108: tgl */
+	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
+		/* Wa_1409767108:tgl,dg1 */
 		table = wa_1409767108_buddy_page_masks;
 	else
 		table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index c26ca029fc0a..d03a239e6977 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -2843,8 +2843,8 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
 					enum plane_id plane_id)
 {
-	/* Wa_14010477008:tgl[a0..c0],rkl[all] */
-	if (IS_ROCKETLAKE(dev_priv) ||
+	/* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+	if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
 	    IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index cef1c122696f..8d780e85fcfb 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -641,6 +641,20 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	       0);
 }
 
+static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
+{
+	gen12_ctx_workarounds_init(engine, wal);
+
+	/* Wa_1409044764 */
+	WA_CLR_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
+			  DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN);
+
+	/* Wa_22010493298 */
+	WA_SET_BIT_MASKED(HIZ_CHICKEN,
+			  DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE);
+}
+
 static void
 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 			   struct i915_wa_list *wal,
@@ -653,7 +667,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
+	if (IS_DG1(i915))
+		dg1_ctx_workarounds_init(engine, wal);
+	else if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915))
 		tgl_ctx_workarounds_init(engine, wal);
 	else if (IS_GEN(i915, 12))
 		gen12_ctx_workarounds_init(engine, wal);
@@ -1213,10 +1229,36 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
 }
 
+static void
+dg1_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+	gen12_gt_workarounds_init(i915, wal);
+
+	/* Wa_1607087056:dg1 */
+	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0))
+		wa_write_or(wal,
+			    SLICE_UNIT_LEVEL_CLKGATE,
+			    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
+
+	/* Wa_1409420604:dg1 */
+	if (IS_DG1(i915))
+		wa_write_or(wal,
+			    SUBSLICE_UNIT_LEVEL_CLKGATE2,
+			    CPSSUNIT_CLKGATE_DIS);
+
+	/* Wa_1408615072:dg1 */
+	/* Empirical testing shows this register is unaffected by engine reset. */
+	if (IS_DG1(i915))
+		wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
+			    VSUNIT_CLKGATE_DIS_TGL);
+}
+
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_TIGERLAKE(i915))
+	if (IS_DG1(i915))
+		dg1_gt_workarounds_init(i915, wal);
+	else if (IS_TIGERLAKE(i915))
 		tgl_gt_workarounds_init(i915, wal);
 	else if (IS_GEN(i915, 12))
 		gen12_gt_workarounds_init(i915, wal);
@@ -1581,6 +1623,20 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
 	}
 }
 
+static void dg1_whitelist_build(struct intel_engine_cs *engine)
+{
+	struct i915_wa_list *w = &engine->whitelist;
+
+	tgl_whitelist_build(engine);
+
+	/* GEN:BUG:1409280441:dg1 */
+	if (IS_DG1_REVID(engine->i915, DG1_REVID_A0, DG1_REVID_A0) &&
+	    (engine->class == RENDER_CLASS ||
+	     engine->class == COPY_ENGINE_CLASS))
+		whitelist_reg_ext(w, RING_ID(engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD);
+}
+
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1588,7 +1644,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist", engine->name);
 
-	if (IS_GEN(i915, 12))
+	if (IS_DG1(i915))
+		dg1_whitelist_build(engine);
+	else if (IS_GEN(i915, 12))
 		tgl_whitelist_build(engine);
 	else if (IS_GEN(i915, 11))
 		icl_whitelist_build(engine);
@@ -1642,15 +1700,18 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
-	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
+	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
 		/*
-		 * Wa_1607138336:tgl
-		 * Wa_1607063988:tgl
+		 * Wa_1607138336:tgl[a0],dg1[a0]
+		 * Wa_1607063988:tgl[a0],dg1[a0]
 		 */
 		wa_write_or(wal,
 			    GEN9_CTX_PREEMPT_REG,
 			    GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
+	}
 
+	if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
 		/*
 		 * Wa_1606679103:tgl
 		 * (see also Wa_1606682166:icl)
@@ -1664,24 +1725,27 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    VSUNIT_CLKGATE_DIS_TGL);
 	}
 
-	if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
-		/* Wa_1606931601:tgl,rkl */
+	if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1606931601:tgl,rkl,dg1 */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+	}
 
-		/* Wa_1409804808:tgl,rkl */
+	if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
+	    IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
+		/* Wa_1409804808:tgl,rkl,dg1[a0] */
 		wa_masked_en(wal, GEN7_ROW_CHICKEN2,
 			     GEN12_PUSH_CONST_DEREF_HOLD_DIS);
 
 		/*
 		 * Wa_1409085225:tgl
-		 * Wa_14010229206:tgl,rkl
+		 * Wa_14010229206:tgl,rkl,dg1[a0]
 		 */
 		wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
 
 		/*
 		 * Wa_1407928979:tgl A*
-		 * Wa_18011464164:tgl B0+
-		 * Wa_22010931296:tgl B0+
+		 * Wa_18011464164:tgl[B0+],dg1[B0+]
+		 * Wa_22010931296:tgl[B0+],dg1[B0+]
 		 * Wa_14010919138:rkl
 		 */
 		wa_write_or(wal, GEN7_FF_THREAD_MODE,
@@ -1690,9 +1754,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		/*
 		 * Wa_1607030317:tgl
 		 * Wa_1607186500:tgl
-		 * Wa_1607297627:tgl,rkl there are multiple entries for this
-		 * WA in the BSpec; some indicate this is an A0-only WA,
-		 * others indicate it applies to all steppings.
+		 * Wa_1607297627:tgl,rkl,dg1[a0]
+		 *
+		 * On TGL and RKL there are multiple entries for this WA in the
+		 * BSpec; some indicate this is an A0-only WA, others indicate
+		 * it applies to all steppings so we trust the "all steppings."
+		 * For DG1 this only applies to A0.
 		 */
 		wa_masked_en(wal,
 			     GEN6_RC_SLEEP_PSMI_CONTROL,
@@ -1700,8 +1767,8 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			     GEN8_RC_SEMA_IDLE_MSG_DISABLE);
 	}
 
-	if (IS_TIGERLAKE(i915)) {
-		/* Wa_1606700617:tgl */
+	if (IS_TIGERLAKE(i915) || IS_DG1(i915)) {
+		/* Wa_22010271021, Wa_1606700617: tgl,dg1 */
 		wa_masked_en(wal,
 			     GEN9_CS_DEBUG_MODE1,
 			     FF_DOP_CLOCK_GATE_DISABLE);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 366ddfc8df6b..c2dfdf52419b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -910,6 +910,8 @@ static const struct intel_device_info dg1_info __maybe_unused = {
 	.platform_engine_mask =
 		BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
 		BIT(VCS0) | BIT(VCS2),
+	/* Wa_16011227922 */
+	.ppgtt_size = 47,
 };
 
 #undef GEN
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79edada25ce1..4e95312eba24 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2542,6 +2542,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define RING_PSMI_CTL(base)	_MMIO((base) + 0x50)
 #define RING_MAX_IDLE(base)	_MMIO((base) + 0x54)
 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
+#define RING_ID(base)		_MMIO((base) + 0x8c)
 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
 #define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
@@ -4161,6 +4162,7 @@ enum {
 
 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
 #define   TGL_VRH_GATING_DIS		REG_BIT(31)
+#define   DPT_GATING_DIS		REG_BIT(22)
 
 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
@@ -8040,12 +8042,14 @@ enum {
 #define GEN8_L3CNTLREG	_MMIO(0x7034)
   #define GEN8_ERRDETBCTRL (1 << 9)
 
-#define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)
-  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC	(1 << 11)
-  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE	(1 << 9)
+#define GEN11_COMMON_SLICE_CHICKEN3			_MMIO(0x7304)
+  #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
+  #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC		REG_BIT(11)
+  #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE		REG_BIT(9)
 
 #define HIZ_CHICKEN					_MMIO(0x7018)
 # define CHV_HZ_8X8_MODE_IN_1X				(1 << 15)
+# define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE   (1 << 14)
 # define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE	(1 << 3)
 
 #define GEN9_SLICE_COMMON_ECO_CHICKEN0		_MMIO(0x7308)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0a1a95060f38..34d4a976827d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7145,6 +7145,19 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)
 			 0, DFR_DISABLE);
 }
 
+static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+	/*
+	 * As opposed to TGL, we should not touch the registers for  media power
+	 * gating
+	 */
+
+	/* Wa_1409836686 :dg1[a0] */
+	if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0))
+		I915_WRITE(GEN9_CLKGATE_DIS_3, I915_READ(GEN9_CLKGATE_DIS_3) |
+			   DPT_GATING_DIS);
+}
+
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	if (!HAS_PCH_CNP(dev_priv))
@@ -7590,7 +7603,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_GEN(dev_priv, 12))
+	if (IS_DG1(dev_priv))
+		dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+	else if (IS_GEN(dev_priv, 12))
 		dev_priv->display.init_clock_gating = tgl_init_clock_gating;
 	else if (IS_GEN(dev_priv, 11))
 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
-- 
2.26.2

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[Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6

[Lucas De Marchi]

From: Anshuman Gupta <anshuman.gupta@intel.com>

DC6 is not supported on DG1, so change the allowed DC mask for DG1.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21f39c94056e..389a0f2d3a14 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int max_dc;
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		max_dc = 4;
+		if (IS_DG1(dev_priv))
+			max_dc = 3;
+		else
+			max_dc = 4;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,
 		 * not depending on the DMC firmware. It's needed by system
-- 
2.26.2

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[Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Lucas De Marchi]

From: Anshuman Gupta <anshuman.gupta@intel.com>

DGFX devices have different DMC_DEBUG* counter MMIO address
offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
counter and handle i915_dmc_info accordingly.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
 drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3644752cc5ec..e3536edcb394 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		   CSR_VERSION_MINOR(csr->version));
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
-		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		if (IS_DG1(dev_priv)) {
+			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+		} else {
+			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		}
+
 		/*
 		 * NOTE: DMC_DEBUG3 is a general purpose reg.
 		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4e95312eba24..78bdce67da08 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7549,6 +7549,8 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
+#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
 
 #define DMC_DEBUG3		_MMIO(0x101090)
 
-- 
2.26.2

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1

[Patchwork]

== Series Details ==

Series: Introduce DG1
URL   : https://patchwork.freedesktop.org/series/79863/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
8f74e276b41a drm/i915/dg1: Initialize RAWCLK properly
c2699a393ba3 drm/i915/dg1: Define MOCS table for DG1
da0e39cc42f3 drm/i915/dg1: Add DG1 power wells
bff25189ad22 drm/i915/dg1: Increase mmio size to 4MB
6763f3077f0d drm/i915/dg1: Wait for pcode/uncore handshake at startup
e18904ffdb23 drm/i915/dg1: Add DPLL macros for DG1
4b251c381b35 drm/i915/dg1: Add and setup DPLLs for DG1
fe51b026ee82 drm/i915/dg1: Enable DPLL for DG1
cbbc5366d85e drm/i915/dg1: add hpd interrupt handling
c0b3de1be1a6 drm/i915/dg1: invert HPD pins
d24c8e3696f3 drm/i915/dg1: gmbus pin mapping
85111a9da7b5 drm/i915/dg1: Enable first 2 ports for DG1
73800c5e78e4 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
4933a57b9c0a drm/i915/dg1: Update comp master/slave relationships for PHYs
bcab535050e1 drm/i915/dg1: Update voltage swing tables for DP
72f10411364c drm/i915/dg1: provide port/phy mapping for vbt
4c68f89318f4 drm/i915/dg1: map/unmap pll clocks
-:244: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#244: FILE: drivers/gpu/drm/i915/i915_reg.h:10340:
+#define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_VAL_TO_ID(val, phy) \
+	  ((((val) & DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)) >> ((phy % 2) * 2)) + (2 * (phy / 2)))

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
472d90a048b8 drm/i915/dg1: enable PORT C/D aka D/E
2d1e6fca5292 drm/i915/dg1: Load DMC
f463503a1825 drm/i915/dg1: Add initial DG1 workarounds
5e4111a18707 drm/i915/dg1: DG1 does not support DC6
a9a8a1141462 drm/i915/dg1: Change DMC_DEBUG{1, 2} registers


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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce DG1

[Patchwork]

== Series Details ==

Series: Introduce DG1
URL   : https://patchwork.freedesktop.org/series/79863/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.


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[Intel-gfx] ✗ Fi.CI.BAT: failure for Introduce DG1

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 9608 bytes --]

== Series Details ==

Series: Introduce DG1
URL   : https://patchwork.freedesktop.org/series/79863/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8786 -> Patchwork_18242
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18242 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18242, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18242:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@gt_engines:
    - fi-skl-lmem:        [PASS][1] -> [DMESG-WARN][2] +31 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-skl-lmem/igt@i915_selftest@live@gt_engines.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-skl-lmem/igt@i915_selftest@live@gt_engines.html

  
Known issues
------------

  Here are the changes found in Patchwork_18242 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-soraka:      [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html

  * igt@gem_flink_basic@double-flink:
    - fi-tgl-y:           [PASS][5] -> [DMESG-WARN][6] ([i915#402]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-tgl-y/igt@gem_flink_basic@double-flink.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-tgl-y/igt@gem_flink_basic@double-flink.html

  * igt@i915_module_load@reload:
    - fi-byt-j1900:       [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-byt-j1900/igt@i915_module_load@reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-byt-j1900/igt@i915_module_load@reload.html
    - fi-apl-guc:         [PASS][9] -> [DMESG-WARN][10] ([i915#1635] / [i915#1982])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-apl-guc/igt@i915_module_load@reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-apl-guc/igt@i915_module_load@reload.html
    - fi-bsw-kefka:       [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-bsw-kefka/igt@i915_module_load@reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-bsw-kefka/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@active:
    - fi-bsw-nick:        [PASS][13] -> [DMESG-FAIL][14] ([i915#541])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-bsw-nick/igt@i915_selftest@live@active.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-bsw-nick/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@gt_pm:
    - fi-apl-guc:         [PASS][15] -> [DMESG-FAIL][16] ([i915#1635] / [i915#1886])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-apl-guc/igt@i915_selftest@live@gt_pm.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-apl-guc/igt@i915_selftest@live@gt_pm.html

  * igt@kms_busy@basic@flip:
    - fi-tgl-y:           [PASS][17] -> [DMESG-WARN][18] ([i915#1982])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-tgl-y/igt@kms_busy@basic@flip.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-tgl-y/igt@kms_busy@basic@flip.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-u2:          [FAIL][19] ([i915#1888]) -> [PASS][20] +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_pm_rpm@module-reload:
    - fi-bsw-n3050:       [DMESG-WARN][21] ([i915#1982]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html

  * igt@kms_addfb_basic@bad-pitch-0:
    - fi-tgl-y:           [DMESG-WARN][23] ([i915#402]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-tgl-y/igt@kms_addfb_basic@bad-pitch-0.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - fi-icl-u2:          [DMESG-WARN][25] ([i915#1982]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
    - fi-skl-guc:         [DMESG-WARN][27] ([i915#2203]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][29] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][30] ([i915#62] / [i915#92]) +2 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-x1275:       [DMESG-WARN][31] ([i915#62] / [i915#92]) -> [DMESG-WARN][32] ([i915#62] / [i915#92] / [i915#95]) +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][33] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][34] ([i915#1982] / [i915#62] / [i915#92])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8786/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (47 -> 40)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_8786 -> Patchwork_18242

  CI-20190529: 20190529
  CI_DRM_8786: e9ecbe8de4e7e7c08363c1ecaaee9270b9c6f2ec @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5747: 6980775bcadec862cd5e5affd65928ef79e5b580 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18242: a9a8a114146225c0979ed0f55216e68a4af1445b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a9a8a1141462 drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
5e4111a18707 drm/i915/dg1: DG1 does not support DC6
f463503a1825 drm/i915/dg1: Add initial DG1 workarounds
2d1e6fca5292 drm/i915/dg1: Load DMC
472d90a048b8 drm/i915/dg1: enable PORT C/D aka D/E
4c68f89318f4 drm/i915/dg1: map/unmap pll clocks
72f10411364c drm/i915/dg1: provide port/phy mapping for vbt
bcab535050e1 drm/i915/dg1: Update voltage swing tables for DP
4933a57b9c0a drm/i915/dg1: Update comp master/slave relationships for PHYs
73800c5e78e4 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
85111a9da7b5 drm/i915/dg1: Enable first 2 ports for DG1
d24c8e3696f3 drm/i915/dg1: gmbus pin mapping
c0b3de1be1a6 drm/i915/dg1: invert HPD pins
cbbc5366d85e drm/i915/dg1: add hpd interrupt handling
fe51b026ee82 drm/i915/dg1: Enable DPLL for DG1
4b251c381b35 drm/i915/dg1: Add and setup DPLLs for DG1
e18904ffdb23 drm/i915/dg1: Add DPLL macros for DG1
6763f3077f0d drm/i915/dg1: Wait for pcode/uncore handshake at startup
bff25189ad22 drm/i915/dg1: Increase mmio size to 4MB
da0e39cc42f3 drm/i915/dg1: Add DG1 power wells
c2699a393ba3 drm/i915/dg1: Define MOCS table for DG1
8f74e276b41a drm/i915/dg1: Initialize RAWCLK properly

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18242/index.html

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Re: [Intel-gfx] [PATCH v5 01/22] drm/i915/dg1: Initialize RAWCLK properly

[Souza, Jose]

On Fri, 2020-07-24 at 14:38 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.roper@intel.com
> >
> 
> DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
> frequencies on CNP+.  Note that register bits associated with this
> frequency confusingly use 37 for the divider field rather than 38 as you
> might expect.
> 
> For simplicity, let's just assume that this 38.4 MHz frequency will hold
> true for other future platforms with "fake" PCH south displays and that
> the CNP-style behavior will remain for other platforms with a real PCH.
> 
> Bspec: 49950
> Bspec: 49309

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: Aditya Swarup <
> aditya.swarup@intel.com
> >
> Cc: Clinton Taylor <
> Clinton.A.Taylor@intel.com
> >
> Cc: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9d6cacbdb691..7722831346ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2680,6 +2680,18 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  			       DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
>  }
>  
> +static int dg1_rawclk(struct drm_i915_private *dev_priv)
> +{
> +	/*
> +	 * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
> +	 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
> +	 */
> +	I915_WRITE(PCH_RAWCLK_FREQ,
> +		   CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
> +
> +	return 38400;
> +}
> +
>  static int cnp_rawclk(struct drm_i915_private *dev_priv)
>  {
>  	u32 rawclk;
> @@ -2788,7 +2800,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  {
>  	u32 freq;
>  
> -	if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> +	if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> +		freq = dg1_rawclk(dev_priv);
> +	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
>  		freq = cnp_rawclk(dev_priv);
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		freq = pch_rawclk(dev_priv);
> 
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Re: [Intel-gfx] [PATCH v5 02/22] drm/i915/dg1: Define MOCS table for DG1

[Matt Roper]

On Fri, Jul 24, 2020 at 02:38:58PM -0700, Lucas De Marchi wrote:
> DG1 has a new MOCS table. We still use the old definition of the table,
> but as for any dgfx card it doesn't contain the control_value values
> (these values don't matter as we won't program them).
> 
> Bspec: 45101
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Matches the bspec

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

I do notice that the general comment farther up the file says "The last
two entries are reserved by the hardware." --- I wonder if we should
change that to "the last few" since DG1 technically has four reserved
entries instead of just two.


Matt

> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 39 +++++++++++++++++++++++++++-
>  1 file changed, 38 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 632e08a4592b..7217c6e2087c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
>  	GEN11_MOCS_ENTRIES
>  };
>  
> +static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
> +	/* Error */
> +	MOCS_ENTRY(0, 0, L3_0_DIRECT),
> +
> +	/* UC */
> +	MOCS_ENTRY(1, 0, L3_1_UC),
> +
> +	/* Reserved */
> +	MOCS_ENTRY(2, 0, L3_0_DIRECT),
> +	MOCS_ENTRY(3, 0, L3_0_DIRECT),
> +	MOCS_ENTRY(4, 0, L3_0_DIRECT),
> +
> +	/* WB - L3 */
> +	MOCS_ENTRY(5, 0, L3_3_WB),
> +	/* WB - L3 50% */
> +	MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
> +	/* WB - L3 25% */
> +	MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
> +	/* WB - L3 12.5% */
> +	MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
> +
> +	/* HDC:L1 + L3 */
> +	MOCS_ENTRY(48, 0, L3_3_WB),
> +	/* HDC:L1 */
> +	MOCS_ENTRY(49, 0, L3_1_UC),
> +
> +	/* HW Reserved */
> +	MOCS_ENTRY(60, 0, L3_1_UC),
> +	MOCS_ENTRY(61, 0, L3_1_UC),
> +	MOCS_ENTRY(62, 0, L3_1_UC),
> +	MOCS_ENTRY(63, 0, L3_1_UC),
> +};
> +
>  enum {
>  	HAS_GLOBAL_MOCS = BIT(0),
>  	HAS_ENGINE_MOCS = BIT(1),
> @@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>  {
>  	unsigned int flags;
>  
> -	if (INTEL_GEN(i915) >= 12) {
> +	if (IS_DG1(i915)) {
> +		table->size = ARRAY_SIZE(dg1_mocs_table);
> +		table->table = dg1_mocs_table;
> +		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> +	} else if (INTEL_GEN(i915) >= 12) {
>  		table->size  = ARRAY_SIZE(tgl_mocs_table);
>  		table->table = tgl_mocs_table;
>  		table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells

[Matt Roper]

On Fri, Jul 24, 2020 at 02:38:59PM -0700, Lucas De Marchi wrote:
> From: Uma Shankar <uma.shankar@intel.com>
> 
> Most of TGL power wells are re-used for DG1. However, AUDIO Power
> Domain is moved from PG3 to PG0. Handle the change and initialize
> power wells with the new power well structure.
> 
> Some of the Audio Streaming logic still remains in PW3 so still
> it needs to be enabled.
> 
> DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
> 
> Need to keep Transcoder C and D to Pipe Power wells, this is against
> the spec but else hitting unclaimed register warnings (kept the logic
> same as TGL)

I think this paragraph is old; the bspec shows transcoders C and D in
the same power wells as pipes C and D now so this is no longer a spec
violation.

Although the bspec went through a few revisions early on, it looks like
DG1 is just a strict subset of the TGL power wells now, so there
probably isn't a need to duplicate it as a whole new table here; I think
the only thing keeping us from re-using TGL's table as-is for DG1 is the
fake "TC COLD" well that blindly makes assumptions about which outputs
are TC rather than paying attention to the real output type.  I think
Aditya has some code that would fix the TCCOLD's assumptions and then we
can just point DG1 to the TGL table.


Matt

> 
> Bspec: 49182
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  .../drm/i915/display/intel_display_power.c    | 201 +++++++++++++++++-
>  1 file changed, 200 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 0c713e83274d..b51b82cb2398 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
>  	BIT_ULL(POWER_DOMAIN_INIT))
>  
> +#define DG1_PW_5_POWER_DOMAINS (			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define DG1_PW_4_POWER_DOMAINS (			\
> +	DG1_PW_5_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define DG1_PW_3_POWER_DOMAINS (			\
> +	DG1_PW_4_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
> +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
> +	BIT_ULL(POWER_DOMAIN_AUX_D) |		\
> +	BIT_ULL(POWER_DOMAIN_AUX_E) |		\
> +	BIT_ULL(POWER_DOMAIN_VGA) |			\
> +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define DG1_PW_2_POWER_DOMAINS (			\
> +	DG1_PW_3_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS (		\
> +	DG1_PW_3_POWER_DOMAINS |			\
> +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
> +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
> +	BIT_ULL(POWER_DOMAIN_INIT))
> +
>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>  	.enable = i9xx_always_on_power_well_noop,
> @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
>  	},
>  };
>  
> +static const struct i915_power_well_desc dg1_power_wells[] = {
> +	{
> +		.name = "always-on",
> +		.always_on = true,
> +		.domains = POWER_DOMAIN_MASK,
> +		.ops = &i9xx_always_on_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +	},
> +	{
> +		.name = "power well 1",
> +		/* Handled by the DMC firmware */
> +		.always_on = true,
> +		.domains = 0,
> +		.ops = &hsw_power_well_ops,
> +		.id = SKL_DISP_PW_1,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "DC off",
> +		.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
> +		.ops = &gen9_dc_off_power_well_ops,
> +		.id = SKL_DISP_DC_OFF,
> +	},
> +	{
> +		.name = "power well 2",
> +		.domains = DG1_PW_2_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = SKL_DISP_PW_2,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "power well 3",
> +		.domains = DG1_PW_3_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = ICL_DISP_PW_3,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
> +			.hsw.irq_pipe_mask = BIT(PIPE_B),
> +			.hsw.has_vga = true,
> +			.hsw.has_fuses = true,
> +		},
> +	},
> +	{
> +		.name = "DDI A IO",
> +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> +		}
> +	},
> +	{
> +		.name = "DDI B IO",
> +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> +		}
> +	},
> +	{
> +		.name = "DDI D TC1 IO",
> +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> +		},
> +	},
> +	{
> +		.name = "DDI E TC2 IO",
> +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_ddi_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> +		},
> +	},
> +	{
> +		.name = "AUX A",
> +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> +		},
> +	},
> +	{
> +		.name = "AUX B",
> +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> +		},
> +	},
> +	{
> +		.name = "AUX D TC1",
> +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "AUX E TC2",
> +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
> +		.ops = &icl_aux_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &icl_aux_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> +			.hsw.is_tc_tbt = false,
> +		},
> +	},
> +	{
> +		.name = "power well 4",
> +		.domains = DG1_PW_4_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
> +			.hsw.has_fuses = true,
> +			.hsw.irq_pipe_mask = BIT(PIPE_C),
> +		}
> +	},
> +	{
> +		.name = "power well 5",
> +		.domains = DG1_PW_5_POWER_DOMAINS,
> +		.ops = &hsw_power_well_ops,
> +		.id = DISP_PW_ID_NONE,
> +		{
> +			.hsw.regs = &hsw_power_well_regs,
> +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
> +			.hsw.has_fuses = true,
> +			.hsw.irq_pipe_mask = BIT(PIPE_D),
> +		},
> +	},
> +};
> +
>  static int
>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>  				   int disable_power_well)
> @@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>  	 * The enabling order will be from lower to higher indexed wells,
>  	 * the disabling order is reversed.
>  	 */
> -	if (IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_DG1(dev_priv)) {
> +		err = set_power_wells(power_domains, dg1_power_wells);
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>  		err = set_power_wells(power_domains, rkl_power_wells);
>  	} else if (IS_GEN(dev_priv, 12)) {
>  		err = set_power_wells(power_domains, tgl_power_wells);
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [Intel-gfx] [PATCH v5 04/22] drm/i915/dg1: Increase mmio size to 4MB

[Matt Roper]

On Fri, Jul 24, 2020 at 02:39:00PM -0700, Lucas De Marchi wrote:
> From: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
> 
> On dgfx register range has been extended to go up to 4MB.
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
> Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

We may want to provide "Bspec: 53616" as a reference.  Technically the
overall space reserved for MMIO is 8MB, but that page helps detail the
layout.  The registers we actually use top out out 28_0000 I believe, so
a 4MB range should be sufficient.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index f5edee17902a..8f9c82aa7338 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1701,11 +1701,15 @@ static int uncore_mmio_setup(struct intel_uncore *uncore)
>  	 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
>  	 * the register BAR remains the same size for all the earlier
>  	 * generations up to Ironlake.
> +	 * For dgfx chips register range is expanded to 4MB.
>  	 */
>  	if (INTEL_GEN(i915) < 5)
>  		mmio_size = 512 * 1024;
> +	else if (IS_DGFX(i915))
> +		mmio_size = 4 * 1024 * 1024;
>  	else
>  		mmio_size = 2 * 1024 * 1024;
> +
>  	uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
>  	if (uncore->regs == NULL) {
>  		drm_err(&i915->drm, "failed to map registers\n");
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
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Re: [Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1

[Matt Roper]

On Fri, Jul 24, 2020 at 02:39:02PM -0700, Lucas De Marchi wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
> 
> DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
> DPLL2 and DPLL3 drive DDIC/DDID.

Since this is a DG1-specific commit with DG1-specific macros, we should
also use the DG1-specific terminology in the commit message to avoid
confusion (i.e., DDI-TC1 and DDI-TC2 instead of DDIC/DDID).

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> 
> Introduce DG1_DPLL_CFCRx() helper macros to configure
> DPLL registers.
> 
> Bspec: 50288, 50299
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 17 ++++++++++++++++-
>  2 files changed, 33 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 5d9a2bc371e7..205542fb8dc7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -154,6 +154,23 @@ enum intel_dpll_id {
>  	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
>  	 */
>  	DPLL_ID_TGL_MGPLL6 = 8,
> +
> +	/**
> +	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
> +	 */
> +	DPLL_ID_DG1_DPLL0 = 0,
> +	/**
> +	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
> +	 */
> +	DPLL_ID_DG1_DPLL1 = 1,
> +	/**
> +	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
> +	 */
> +	DPLL_ID_DG1_DPLL2 = 2,
> +	/**
> +	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
> +	 */
> +	DPLL_ID_DG1_DPLL3 = 3,
>  };
>  
>  #define I915_NUM_PLLS 9
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3767b32127da..986e31af7763 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
> -#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
> +#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
> +
>  
>  /*
>   * Device info offset array based helpers for groups of registers with unevenly
> @@ -10547,6 +10548,20 @@ enum skl_power_gate {
>  #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
>  						  _TGL_DPLL1_CFGCR1)
>  
> +#define _DG1_DPLL2_CFGCR0		0x16C284
> +#define _DG1_DPLL3_CFGCR0		0x16C28C
> +#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
> +						   _TGL_DPLL1_CFGCR0, \
> +						   _DG1_DPLL2_CFGCR0, \
> +						   _DG1_DPLL3_CFGCR0)
> +
> +#define _DG1_DPLL2_CFGCR1               0x16C288
> +#define _DG1_DPLL3_CFGCR1               0x16C290
> +#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> +						   _TGL_DPLL1_CFGCR1, \
> +						   _DG1_DPLL2_CFGCR1, \
> +						   _DG1_DPLL3_CFGCR1)
> +
>  #define _DKL_PHY1_BASE			0x168000
>  #define _DKL_PHY2_BASE			0x169000
>  #define _DKL_PHY3_BASE			0x16A000
> -- 
> 2.26.2
> 

-- 
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Re: [Intel-gfx] [PATCH v5 07/22] drm/i915/dg1: Add and setup DPLLs for DG1

[Matt Roper]

On Fri, Jul 24, 2020 at 02:39:03PM -0700, Lucas De Marchi wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
> 
> Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
> Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
> DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.

As on the previous patch, let's use the DG1 "DDI-TC1" and "DDI-TC2"
terminology to avoid confusion (especially since the C/D here aren't
even the same as the PORT_D/PORT_E that they index as in the driver).

> 
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 41 +++++++++++++++++--
>  1 file changed, 37 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 81ab975fe4f0..39a53aa0b233 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3512,7 +3512,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  
>  	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>  
> -	if (IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_DG1(dev_priv)) {
> +		if (port == PORT_D || port == PORT_E) {
> +			dpll_mask =
> +				BIT(DPLL_ID_DG1_DPLL2) |
> +				BIT(DPLL_ID_DG1_DPLL3);
> +		} else {
> +			dpll_mask =
> +				BIT(DPLL_ID_DG1_DPLL0) |
> +				BIT(DPLL_ID_DG1_DPLL1);
> +		}
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>  		dpll_mask =
>  			BIT(DPLL_ID_EHL_DPLL4) |
>  			BIT(DPLL_ID_ICL_DPLL1) |
> @@ -3808,7 +3818,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>  	if (!(val & PLL_ENABLE))
>  		goto out;
>  
> -	if (IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_DG1(dev_priv)) {
> +		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
> +		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>  		hw_state->cfgcr0 = intel_de_read(dev_priv,
>  						 RKL_DPLL_CFGCR0(id));
>  		hw_state->cfgcr1 = intel_de_read(dev_priv,
> @@ -3866,7 +3879,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
>  	const enum intel_dpll_id id = pll->info->id;
>  	i915_reg_t cfgcr0_reg, cfgcr1_reg;
>  
> -	if (IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_DG1(dev_priv)) {
> +		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
> +		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>  		cfgcr0_reg = RKL_DPLL_CFGCR0(id);
>  		cfgcr1_reg = RKL_DPLL_CFGCR1(id);
>  	} else if (INTEL_GEN(dev_priv) >= 12) {
> @@ -4316,6 +4332,21 @@ static const struct intel_dpll_mgr rkl_pll_mgr = {
>  	.dump_hw_state = icl_dump_hw_state,
>  };
>  
> +static const struct dpll_info dg1_plls[] = {
> +	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
> +	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
> +	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
> +	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
> +	{ },
> +};
> +
> +static const struct intel_dpll_mgr dg1_pll_mgr = {
> +	.dpll_info = dg1_plls,
> +	.get_dplls = icl_get_dplls,
> +	.put_dplls = icl_put_dplls,
> +	.dump_hw_state = icl_dump_hw_state,

Do we also need a

        .update_ref_clks = icl_update_dpll_ref_clks,

here?  That's a new hook as of ccc495fd7ac3 ("drm/i915: Unify the DPLL
ref clock frequency tracking").


Matt

> +};
> +
>  /**
>   * intel_shared_dpll_init - Initialize shared DPLLs
>   * @dev: drm device
> @@ -4329,7 +4360,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
>  	const struct dpll_info *dpll_info;
>  	int i;
>  
> -	if (IS_ROCKETLAKE(dev_priv))
> +	if (IS_DG1(dev_priv))
> +		dpll_mgr = &dg1_pll_mgr;
> +	else if (IS_ROCKETLAKE(dev_priv))
>  		dpll_mgr = &rkl_pll_mgr;
>  	else if (INTEL_GEN(dev_priv) >= 12)
>  		dpll_mgr = &tgl_pll_mgr;
> -- 
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.roper@intel.com
> >
> 
> DG1 does some additional pcode/uncore handshaking at
> boot time; this handshaking must complete before various other pcode
> commands are effective and before general work is submitted to the GPU.
> We need to poll a new pcode mailbox during startup until it reports that
> this handshaking is complete.
> 
> The bspec doesn't give guidance on how long we may need to wait for this
> handshaking to complete.  For now, let's just set a really long timeout;
> if we still don't get a completion status by the end of that timeout,
> we'll just continue on and hope for the best.
> 
> Bspec: 52065
> Cc: Clinton Taylor <
> Clinton.A.Taylor@intel.com
> >
> Cc: Ville Syrjälä <
> ville.syrjala@linux.intel.com
> >
> Cc: Radhakrishna Sripada <
> radhakrishna.sripada@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/i915_drv.c       |  3 +++
>  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
>  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/intel_sideband.h |  2 ++
>  4 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5fd5af4bc855..5473bfe9126c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -85,6 +85,7 @@
>  #include "intel_gvt.h"
>  #include "intel_memory_region.h"
>  #include "intel_pm.h"
> +#include "intel_sideband.h"
>  #include "vlv_suspend.h"
>  
>  static struct drm_driver driver;
> @@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_dram_detect(dev_priv);
>  
> +	intel_pcode_init(dev_priv);
> +
>  	intel_bw_init_hw(dev_priv);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d31f3bf634..3767b32127da 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9245,6 +9245,9 @@ enum {
>  #define     GEN9_SAGV_DISABLE			0x0
>  #define     GEN9_SAGV_IS_DISABLED		0x1
>  #define     GEN9_SAGV_ENABLE			0x3
> +#define   DG1_PCODE_STATUS			0x7E
> +#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
> +#define     DG1_UNCORE_INIT_COMPLETE		0x1

With s/DG1_CHECK_UNCORE_INIT_STATUS/DG1_CHECK_UNCORE_INIT_STATUS_COMPLETE or something similar that makes easy to understand that 0x1 is the response
of the DG1_CHECK_UNCORE_INIT_STATUS sub-command.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 916ccd1c0e96..8b093525240d 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>  	return ret ? ret : status;
>  #undef COND
>  }
> +
> +void intel_pcode_init(struct drm_i915_private *i915)
> +{
> +	int ret;
> +
> +	if (!IS_DGFX(i915))
> +		return;
> +
> +	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
> +				DG1_CHECK_UNCORE_INIT_STATUS,
> +				DG1_UNCORE_INIT_COMPLETE,
> +				DG1_UNCORE_INIT_COMPLETE, 50);
> +	if (ret)
> +		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
> +}
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> index 7fb95745a444..094c7b19c5d4 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.h
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>  		      u32 reply_mask, u32 reply, int timeout_base_ms);
>  
> +void intel_pcode_init(struct drm_i915_private *i915);
> +
>  #endif /* _INTEL_SIDEBAND_H */
> 
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Re: [Intel-gfx] [PATCH v5 19/22] drm/i915/dg1: Load DMC

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Atwood <
> matthew.s.atwood@intel.com
> >
> 
> Add support to load DMC v2.0.2 on DG1
> 
> While we're at it, tweak the TGL and RKL firmware size definition to
> follow the convention used in previous platforms. Remove obsolete
> commenting.
> 
> Bpec: 49230
> 
> Cc: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Matt Atwood <
> matthew.s.atwood@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
> index f22a7645c249..ccf13ea627d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.c
> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> @@ -38,15 +38,19 @@
>   * low-power state and comes back to normal.
>   */
>  
> -#define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
> +#define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
> +#define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
> +#define DG1_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
> +MODULE_FIRMWARE(DG1_CSR_PATH);
>  
>  #define RKL_CSR_PATH			"i915/rkl_dmc_ver2_01.bin"
>  #define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)
> +#define RKL_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
>  MODULE_FIRMWARE(RKL_CSR_PATH);
>  
>  #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_06.bin"
>  #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 6)
> -#define TGL_CSR_MAX_FW_SIZE		0x6000
> +#define TGL_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE

Until CSR_MAX_FW_SIZE of a GEN12 platform is different I don't see a reason why to define a per-platform CSR_MAX_FW_SIZE.

The rest looks good.

>  MODULE_FIRMWARE(TGL_CSR_PATH);
>  
>  #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
> @@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_csr_runtime_pm_get(dev_priv);
>  
> -	if (IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_DG1(dev_priv)) {
> +		csr->fw_path = DG1_CSR_PATH;
> +		csr->required_version = DG1_CSR_VERSION_REQUIRED;
> +		csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>  		csr->fw_path = RKL_CSR_PATH;
>  		csr->required_version = RKL_CSR_VERSION_REQUIRED;
> -		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> +		csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
>  	} else if (INTEL_GEN(dev_priv) >= 12) {
>  		csr->fw_path = TGL_CSR_PATH;
>  		csr->required_version = TGL_CSR_VERSION_REQUIRED;
> -		/* Allow to load fw via parameter using the last known size */
> -		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> +		csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
>  	} else if (IS_GEN(dev_priv, 11)) {
>  		csr->fw_path = ICL_CSR_PATH;
>  		csr->required_version = ICL_CSR_VERSION_REQUIRED;
> 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> 
> DGFX devices have different DMC_DEBUG* counter MMIO address
> offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> counter and handle i915_dmc_info accordingly.
> 
> Cc: Uma Shankar <
> uma.shankar@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
>  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3644752cc5ec..e3536edcb394 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  		   CSR_VERSION_MINOR(csr->version));
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> +		if (IS_DG1(dev_priv)) {
> +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> +		} else {
> +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> +		}
> +
>  		/*
>  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
>  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4e95312eba24..78bdce67da08 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7549,6 +7549,8 @@ enum {
>  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
>  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)

DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
Removing it:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


>  
>  #define DMC_DEBUG3		_MMIO(0x101090)
>  
> 
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Re: [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> 
> DC6 is not supported on DG1, so change the allowed DC mask for DG1.
> 
> Cc: Uma Shankar <
> uma.shankar@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 21f39c94056e..389a0f2d3a14 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>  	int max_dc;
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		max_dc = 4;
> +		if (IS_DG1(dev_priv))

Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it.
With this change:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +			max_dc = 3;
> +		else
> +			max_dc = 4;
>  		/*
>  		 * DC9 has a separate HW flow from the rest of the DC states,
>  		 * not depending on the DMC firmware. It's needed by system
> 
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Re: [Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.roper@intel.com
> >
> 
> DG1's vswing tables are the same for eDP and HDMI but have slight
> differences from ICL/TGL for DP.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 49291
> Cc: Clinton Taylor <
> Clinton.A.Taylor@intel.com
> >
> Cc: José Roberto de Souza <
> jose.souza@intel.com
> >
> Cc: Radhakrishna Sripada <
> radhakrishna.sripada@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 714b2bc96f23..c19d5a375eba 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>  };
>  
> +static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */
> +	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
> +	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */
> +	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
> +	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
> +	{ 0xC, 0x60, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */
> +	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 600   900      3.5   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */
> +	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
> +	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */
> +	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
> +	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
> +	{ 0xC, 0x58, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */
> +	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>  	u32 cri_txdeemph_override_11_6;
>  	u32 cri_txdeemph_override_5_0;
> @@ -1034,6 +1062,12 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
>  		return icl_combo_phy_ddi_translations_edp_hbr2;
> +	} else if (IS_DG1(dev_priv) && rate > 270000) {
> +		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
> +		return dg1_combo_phy_ddi_translations_dp_hbr2;
> +	} else if (IS_DG1(dev_priv)) {
> +		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
> +		return dg1_combo_phy_ddi_translations_dp_hbr;
>  	}
>  
>  	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Anshuman Gupta]

On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > From: Anshuman Gupta <
> > anshuman.gupta@intel.com
> > >
> > 
> > DGFX devices have different DMC_DEBUG* counter MMIO address
> > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > counter and handle i915_dmc_info accordingly.
> > 
> > Cc: Uma Shankar <
> > uma.shankar@intel.com
> > >
> > Signed-off-by: Anshuman Gupta <
> > anshuman.gupta@intel.com
> > >
> > Signed-off-by: Lucas De Marchi <
> > lucas.demarchi@intel.com
> > >
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
> >  2 files changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 3644752cc5ec..e3536edcb394 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> >  		   CSR_VERSION_MINOR(csr->version));
> >  
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > +		if (IS_DG1(dev_priv)) {
> > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > +		} else {
> > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > +		}
> > +
> >  		/*
> >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
> >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4e95312eba24..78bdce67da08 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7549,6 +7549,8 @@ enum {
> >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
> >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
> 
> DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> Removing it:
DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
igfx platforms, considering name consistency it has been kept with name DG1_*
inline to B.Spec Index:49787.

Thanks,
Anshuman Gupta.
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> 
> >  
> >  #define DMC_DEBUG3		_MMIO(0x101090)
> >  
> > 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Souza, Jose]

On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > From: Anshuman Gupta <
> > > anshuman.gupta@intel.com
> > > 
> > > 
> > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > counter and handle i915_dmc_info accordingly.
> > > 
> > > Cc: Uma Shankar <
> > > uma.shankar@intel.com
> > > 
> > > 
> > > Signed-off-by: Anshuman Gupta <
> > > anshuman.gupta@intel.com
> > > 
> > > 
> > > Signed-off-by: Lucas De Marchi <
> > > lucas.demarchi@intel.com
> > > 
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> > >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
> > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 3644752cc5ec..e3536edcb394 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> > >  		   CSR_VERSION_MINOR(csr->version));
> > >  
> > >  	if (INTEL_GEN(dev_priv) >= 12) {
> > > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > +		if (IS_DG1(dev_priv)) {
> > > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > +		} else {
> > > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > +		}
> > > +
> > >  		/*
> > >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
> > >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4e95312eba24..78bdce67da08 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7549,6 +7549,8 @@ enum {
> > >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> > >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
> > >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> > > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> > > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
> > 
> > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > Removing it:
> 
> DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> igfx platforms, considering name consistency it has been kept with name DG1_*
> inline to B.Spec Index:49787.

A discrete graphics card will never be able to reach DC6 as it is a SOC power saving feature.

> 
> Thanks,
> Anshuman Gupta.
> > Reviewed-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> > 
> > 
> > >  
> > >  #define DMC_DEBUG3		_MMIO(0x101090)
> > >  
> > > 
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > 
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Anshuman Gupta]

On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:
> On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> > On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > > From: Anshuman Gupta <
> > > > anshuman.gupta@intel.com
> > > > 
> > > > 
> > > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > > counter and handle i915_dmc_info accordingly.
> > > > 
> > > > Cc: Uma Shankar <
> > > > uma.shankar@intel.com
> > > > 
> > > > 
> > > > Signed-off-by: Anshuman Gupta <
> > > > anshuman.gupta@intel.com
> > > > 
> > > > 
> > > > Signed-off-by: Lucas De Marchi <
> > > > lucas.demarchi@intel.com
> > > > 
> > > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> > > >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
> > > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > index 3644752cc5ec..e3536edcb394 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> > > >  		   CSR_VERSION_MINOR(csr->version));
> > > >  
> > > >  	if (INTEL_GEN(dev_priv) >= 12) {
> > > > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > +		if (IS_DG1(dev_priv)) {
> > > > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > > +		} else {
> > > > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > +		}
> > > > +
> > > >  		/*
> > > >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
> > > >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 4e95312eba24..78bdce67da08 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7549,6 +7549,8 @@ enum {
> > > >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> > > >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
> > > >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> > > > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> > > > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
> > > 
> > > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > > Removing it:
> > 
> > DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> > igfx platforms, considering name consistency it has been kept with name DG1_*
> > inline to B.Spec Index:49787.
> 
> A discrete graphics card will never be able to reach DC6 as it is a SOC power saving feature.
Is it documented some where, AFAIK DC6 is still diplay C state where it power off its innermost power well,
with involvment of some non display third party f/w.
IMHO if any discrete-gfx would support DC6, it would be useful in the use cases where driver is yet to request runtime suspend (DC9)
but display is already being powered off.
Thanks,
Anshuman Gupta.
> 
> > 
> > Thanks,
> > Anshuman Gupta.
> > > Reviewed-by: José Roberto de Souza <
> > > jose.souza@intel.com
> > > >
> > > 
> > > 
> > > >  
> > > >  #define DMC_DEBUG3		_MMIO(0x101090)
> > > >  
> > > > 
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > 
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Lucas De Marchi]

On Mon, Aug 10, 2020 at 11:18:11AM +0530, Anshuman Gupta wrote:
>On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:
>> On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
>> > On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
>> > > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> > > > From: Anshuman Gupta <
>> > > > anshuman.gupta@intel.com
>> > > >
>> > > >
>> > > > DGFX devices have different DMC_DEBUG* counter MMIO address
>> > > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
>> > > > counter and handle i915_dmc_info accordingly.
>> > > >
>> > > > Cc: Uma Shankar <
>> > > > uma.shankar@intel.com
>> > > >
>> > > >
>> > > > Signed-off-by: Anshuman Gupta <
>> > > > anshuman.gupta@intel.com
>> > > >
>> > > >
>> > > > Signed-off-by: Lucas De Marchi <
>> > > > lucas.demarchi@intel.com
>> > > >
>> > > >
>> > > > ---
>> > > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
>> > > >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
>> > > >  2 files changed, 9 insertions(+), 2 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> > > > index 3644752cc5ec..e3536edcb394 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> > > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> > > >  		   CSR_VERSION_MINOR(csr->version));
>> > > >
>> > > >  	if (INTEL_GEN(dev_priv) >= 12) {
>> > > > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>> > > > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
>> > > > +		if (IS_DG1(dev_priv)) {
>> > > > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
>> > > > +		} else {
>> > > > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>> > > > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
>> > > > +		}
>> > > > +
>> > > >  		/*
>> > > >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
>> > > >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
>> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > > > index 4e95312eba24..78bdce67da08 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > > @@ -7549,6 +7549,8 @@ enum {
>> > > >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
>> > > >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>> > > >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
>> > > > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
>> > > > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
>> > >
>> > > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
>> > > Removing it:
>> >
>> > DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
>> > igfx platforms, considering name consistency it has been kept with name DG1_*
>> > inline to B.Spec Index:49787.
>>
>> A discrete graphics card will never be able to reach DC6 as it is a SOC power saving feature.
>Is it documented some where, AFAIK DC6 is still diplay C state where it power off its innermost power well,
>with involvment of some non display third party f/w.
>IMHO if any discrete-gfx would support DC6, it would be useful in the use cases where driver is yet to request runtime suspend (DC9)
>but display is already being powered off.

Correct, but I think the more relevant argument here is that it is _not
used_. If it was a bitfield, then ok. But it is a register. I don't think
we want to add all the unused registers. Chances are a new platform that
supports it will already have it in another address already.

I will remove it in the next version. And this is also 

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Lucas De Marchi
>Thanks,
>Anshuman Gupta.
>>
>> >
>> > Thanks,
>> > Anshuman Gupta.
>> > > Reviewed-by: José Roberto de Souza <
>> > > jose.souza@intel.com
>> > > >
>> > >
>> > >
>> > > >
>> > > >  #define DMC_DEBUG3		_MMIO(0x101090)
>> > > >
>> > > >
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > >
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> > >
>_______________________________________________
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Re: [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells

[Lucas De Marchi]

On Tue, Jul 28, 2020 at 01:51:53PM -0700, Matt Roper wrote:
>On Fri, Jul 24, 2020 at 02:38:59PM -0700, Lucas De Marchi wrote:
>> From: Uma Shankar <uma.shankar@intel.com>
>>
>> Most of TGL power wells are re-used for DG1. However, AUDIO Power
>> Domain is moved from PG3 to PG0. Handle the change and initialize
>> power wells with the new power well structure.
>>
>> Some of the Audio Streaming logic still remains in PW3 so still
>> it needs to be enabled.
>>
>> DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
>>
>> Need to keep Transcoder C and D to Pipe Power wells, this is against
>> the spec but else hitting unclaimed register warnings (kept the logic
>> same as TGL)
>
>I think this paragraph is old; the bspec shows transcoders C and D in
>the same power wells as pipes C and D now so this is no longer a spec
>violation.
>
>Although the bspec went through a few revisions early on, it looks like
>DG1 is just a strict subset of the TGL power wells now, so there
>probably isn't a need to duplicate it as a whole new table here; I think
>the only thing keeping us from re-using TGL's table as-is for DG1 is the
>fake "TC COLD" well that blindly makes assumptions about which outputs
>are TC rather than paying attention to the real output type.  I think
>Aditya has some code that would fix the TCCOLD's assumptions and then we
>can just point DG1 to the TGL table.

Aditya, are you going to submit this soon?


>
>
>Matt
>
>>
>> Bspec: 49182
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../drm/i915/display/intel_display_power.c    | 201 +++++++++++++++++-
>>  1 file changed, 200 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 0c713e83274d..b51b82cb2398 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>>  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
>>  	BIT_ULL(POWER_DOMAIN_INIT))
>>
>> +#define DG1_PW_5_POWER_DOMAINS (			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_PW_4_POWER_DOMAINS (			\
>> +	DG1_PW_5_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_PW_3_POWER_DOMAINS (			\
>> +	DG1_PW_4_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
>> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
>> +	BIT_ULL(POWER_DOMAIN_AUX_D) |		\
>> +	BIT_ULL(POWER_DOMAIN_AUX_E) |		\
>> +	BIT_ULL(POWER_DOMAIN_VGA) |			\
>> +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_PW_2_POWER_DOMAINS (			\
>> +	DG1_PW_3_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS (		\
>> +	DG1_PW_3_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>> +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>>  	.enable = i9xx_always_on_power_well_noop,
>> @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
>>  	},
>>  };
>>
>> +static const struct i915_power_well_desc dg1_power_wells[] = {
>> +	{
>> +		.name = "always-on",
>> +		.always_on = true,
>> +		.domains = POWER_DOMAIN_MASK,
>> +		.ops = &i9xx_always_on_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +	},
>> +	{
>> +		.name = "power well 1",
>> +		/* Handled by the DMC firmware */
>> +		.always_on = true,
>> +		.domains = 0,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = SKL_DISP_PW_1,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
>> +			.hsw.has_fuses = true,
>> +		},
>> +	},
>> +	{
>> +		.name = "DC off",
>> +		.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
>> +		.ops = &gen9_dc_off_power_well_ops,
>> +		.id = SKL_DISP_DC_OFF,
>> +	},
>> +	{
>> +		.name = "power well 2",
>> +		.domains = DG1_PW_2_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = SKL_DISP_PW_2,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
>> +			.hsw.has_fuses = true,
>> +		},
>> +	},
>> +	{
>> +		.name = "power well 3",
>> +		.domains = DG1_PW_3_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = ICL_DISP_PW_3,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_B),
>> +			.hsw.has_vga = true,
>> +			.hsw.has_fuses = true,
>> +		},
>> +	},
>> +	{
>> +		.name = "DDI A IO",
>> +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>> +		}
>> +	},
>> +	{
>> +		.name = "DDI B IO",
>> +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>> +		}
>> +	},
>> +	{
>> +		.name = "DDI D TC1 IO",
>> +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>> +		},
>> +	},
>> +	{
>> +		.name = "DDI E TC2 IO",
>> +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX A",
>> +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX B",
>> +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX D TC1",
>> +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>> +			.hsw.is_tc_tbt = false,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX E TC2",
>> +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>> +			.hsw.is_tc_tbt = false,
>> +		},
>> +	},
>> +	{
>> +		.name = "power well 4",
>> +		.domains = DG1_PW_4_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
>> +			.hsw.has_fuses = true,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_C),
>> +		}
>> +	},
>> +	{
>> +		.name = "power well 5",
>> +		.domains = DG1_PW_5_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
>> +			.hsw.has_fuses = true,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_D),
>> +		},
>> +	},
>> +};
>> +
>>  static int
>>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>>  				   int disable_power_well)
>> @@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>>  	 * The enabling order will be from lower to higher indexed wells,
>>  	 * the disabling order is reversed.
>>  	 */
>> -	if (IS_ROCKETLAKE(dev_priv)) {
>> +	if (IS_DG1(dev_priv)) {
>> +		err = set_power_wells(power_domains, dg1_power_wells);
>> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>>  		err = set_power_wells(power_domains, rkl_power_wells);
>>  	} else if (IS_GEN(dev_priv, 12)) {
>>  		err = set_power_wells(power_domains, tgl_power_wells);
>> --
>> 2.26.2
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1

[Lucas De Marchi]

On Tue, Jul 28, 2020 at 02:54:18PM -0700, Matt Roper wrote:
>On Fri, Jul 24, 2020 at 02:39:02PM -0700, Lucas De Marchi wrote:
>> From: Aditya Swarup <aditya.swarup@intel.com>
>>
>> DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
>> DPLL2 and DPLL3 drive DDIC/DDID.
>
>Since this is a DG1-specific commit with DG1-specific macros, we should
>also use the DG1-specific terminology in the commit message to avoid
>confusion (i.e., DDI-TC1 and DDI-TC2 instead of DDIC/DDID).
>

ok, re-reading  bspec 49182 now I agree, although I find this naming
more confusing as it doesn't use TC phy

thanks
Lucas De Marchi

>Aside from that,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>
>> Introduce DG1_DPLL_CFCRx() helper macros to configure
>> DPLL registers.
>>
>> Bspec: 50288, 50299
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
>>  drivers/gpu/drm/i915/i915_reg.h               | 17 ++++++++++++++++-
>>  2 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> index 5d9a2bc371e7..205542fb8dc7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> @@ -154,6 +154,23 @@ enum intel_dpll_id {
>>  	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
>>  	 */
>>  	DPLL_ID_TGL_MGPLL6 = 8,
>> +
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
>> +	 */
>> +	DPLL_ID_DG1_DPLL0 = 0,
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
>> +	 */
>> +	DPLL_ID_DG1_DPLL1 = 1,
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
>> +	 */
>> +	DPLL_ID_DG1_DPLL2 = 2,
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
>> +	 */
>> +	DPLL_ID_DG1_DPLL3 = 3,
>>  };
>>
>>  #define I915_NUM_PLLS 9
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 3767b32127da..986e31af7763 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
>> -#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
>> +#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
>> +
>>
>>  /*
>>   * Device info offset array based helpers for groups of registers with unevenly
>> @@ -10547,6 +10548,20 @@ enum skl_power_gate {
>>  #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
>>  						  _TGL_DPLL1_CFGCR1)
>>
>> +#define _DG1_DPLL2_CFGCR0		0x16C284
>> +#define _DG1_DPLL3_CFGCR0		0x16C28C
>> +#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
>> +						   _TGL_DPLL1_CFGCR0, \
>> +						   _DG1_DPLL2_CFGCR0, \
>> +						   _DG1_DPLL3_CFGCR0)
>> +
>> +#define _DG1_DPLL2_CFGCR1               0x16C288
>> +#define _DG1_DPLL3_CFGCR1               0x16C290
>> +#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
>> +						   _TGL_DPLL1_CFGCR1, \
>> +						   _DG1_DPLL2_CFGCR1, \
>> +						   _DG1_DPLL3_CFGCR1)
>> +
>>  #define _DKL_PHY1_BASE			0x168000
>>  #define _DKL_PHY2_BASE			0x169000
>>  #define _DKL_PHY3_BASE			0x16A000
>> --
>> 2.26.2
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Lucas De Marchi]

On Mon, Aug 03, 2020 at 04:24:17PM -0700, Jose Souza wrote:
>On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> From: Matt Roper <
>> matthew.d.roper@intel.com
>> >
>>
>> DG1 does some additional pcode/uncore handshaking at
>> boot time; this handshaking must complete before various other pcode
>> commands are effective and before general work is submitted to the GPU.
>> We need to poll a new pcode mailbox during startup until it reports that
>> this handshaking is complete.
>>
>> The bspec doesn't give guidance on how long we may need to wait for this
>> handshaking to complete.  For now, let's just set a really long timeout;
>> if we still don't get a completion status by the end of that timeout,
>> we'll just continue on and hope for the best.
>>
>> Bspec: 52065
>> Cc: Clinton Taylor <
>> Clinton.A.Taylor@intel.com
>> >
>> Cc: Ville Syrjälä <
>> ville.syrjala@linux.intel.com
>> >
>> Cc: Radhakrishna Sripada <
>> radhakrishna.sripada@intel.com
>> >
>> Signed-off-by: Matt Roper <
>> matthew.d.roper@intel.com
>> >
>> Signed-off-by: Lucas De Marchi <
>> lucas.demarchi@intel.com
>> >
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c       |  3 +++
>>  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
>>  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/intel_sideband.h |  2 ++
>>  4 files changed, 23 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 5fd5af4bc855..5473bfe9126c 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -85,6 +85,7 @@
>>  #include "intel_gvt.h"
>>  #include "intel_memory_region.h"
>>  #include "intel_pm.h"
>> +#include "intel_sideband.h"
>>  #include "vlv_suspend.h"
>>
>>  static struct drm_driver driver;
>> @@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>>  	 */
>>  	intel_dram_detect(dev_priv);
>>
>> +	intel_pcode_init(dev_priv);
>> +
>>  	intel_bw_init_hw(dev_priv);
>>
>>  	return 0;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index a0d31f3bf634..3767b32127da 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9245,6 +9245,9 @@ enum {
>>  #define     GEN9_SAGV_DISABLE			0x0
>>  #define     GEN9_SAGV_IS_DISABLED		0x1
>>  #define     GEN9_SAGV_ENABLE			0x3
>> +#define   DG1_PCODE_STATUS			0x7E
>> +#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
>> +#define     DG1_UNCORE_INIT_COMPLETE		0x1
>
>With s/DG1_CHECK_UNCORE_INIT_STATUS/DG1_CHECK_UNCORE_INIT_STATUS_COMPLETE or something similar that makes easy to understand that 0x1 is the response
>of the DG1_CHECK_UNCORE_INIT_STATUS sub-command.

checking all the other users of skl_pcode_request() I don't see a
pattern there. Examples:

ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
                         SKL_CDCLK_PREPARE_FOR_CHANGE,     
                         SKL_CDCLK_READY_FOR_CHANGE,       
                         SKL_CDCLK_READY_FOR_CHANGE, 3);   

ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,            
                         GEN9_SAGV_DISABLE,                            
                         GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 
                         1);                                           

Giveng the current uses, I'd rather rename like:

+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS		0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1


>Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

does that still stands with the rename above?

thanks
Lucas De Marchi

>
>
>>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>> index 916ccd1c0e96..8b093525240d 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>>  	return ret ? ret : status;
>>  #undef COND
>>  }
>> +
>> +void intel_pcode_init(struct drm_i915_private *i915)
>> +{
>> +	int ret;
>> +
>> +	if (!IS_DGFX(i915))
>> +		return;
>> +
>> +	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
>> +				DG1_CHECK_UNCORE_INIT_STATUS,
>> +				DG1_UNCORE_INIT_COMPLETE,
>> +				DG1_UNCORE_INIT_COMPLETE, 50);
>> +	if (ret)
>> +		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
>> index 7fb95745a444..094c7b19c5d4 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.h
>> +++ b/drivers/gpu/drm/i915/intel_sideband.h
>> @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>>  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>>  		      u32 reply_mask, u32 reply, int timeout_base_ms);
>>
>> +void intel_pcode_init(struct drm_i915_private *i915);
>> +
>>  #endif /* _INTEL_SIDEBAND_H */
>>
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Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Souza, Jose]

On Mon, 2020-08-24 at 12:24 -0700, Lucas De Marchi wrote:
> On Mon, Aug 03, 2020 at 04:24:17PM -0700, Jose Souza wrote:
> > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > From: Matt Roper <
> > > matthew.d.roper@intel.com
> > > 
> > > 
> > > DG1 does some additional pcode/uncore handshaking at
> > > boot time; this handshaking must complete before various other pcode
> > > commands are effective and before general work is submitted to the GPU.
> > > We need to poll a new pcode mailbox during startup until it reports that
> > > this handshaking is complete.
> > > 
> > > The bspec doesn't give guidance on how long we may need to wait for this
> > > handshaking to complete.  For now, let's just set a really long timeout;
> > > if we still don't get a completion status by the end of that timeout,
> > > we'll just continue on and hope for the best.
> > > 
> > > Bspec: 52065
> > > Cc: Clinton Taylor <
> > > Clinton.A.Taylor@intel.com
> > > 
> > > 
> > > Cc: Ville Syrjälä <
> > > ville.syrjala@linux.intel.com
> > > 
> > > 
> > > Cc: Radhakrishna Sripada <
> > > radhakrishna.sripada@intel.com
> > > 
> > > 
> > > Signed-off-by: Matt Roper <
> > > matthew.d.roper@intel.com
> > > 
> > > 
> > > Signed-off-by: Lucas De Marchi <
> > > lucas.demarchi@intel.com
> > > 
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.c       |  3 +++
> > >  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
> > >  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
> > >  drivers/gpu/drm/i915/intel_sideband.h |  2 ++
> > >  4 files changed, 23 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 5fd5af4bc855..5473bfe9126c 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -85,6 +85,7 @@
> > >  #include "intel_gvt.h"
> > >  #include "intel_memory_region.h"
> > >  #include "intel_pm.h"
> > > +#include "intel_sideband.h"
> > >  #include "vlv_suspend.h"
> > > 
> > >  static struct drm_driver driver;
> > > @@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> > >  	 */
> > >  	intel_dram_detect(dev_priv);
> > > 
> > > +	intel_pcode_init(dev_priv);
> > > +
> > >  	intel_bw_init_hw(dev_priv);
> > > 
> > >  	return 0;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index a0d31f3bf634..3767b32127da 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9245,6 +9245,9 @@ enum {
> > >  #define     GEN9_SAGV_DISABLE			0x0
> > >  #define     GEN9_SAGV_IS_DISABLED		0x1
> > >  #define     GEN9_SAGV_ENABLE			0x3
> > > +#define   DG1_PCODE_STATUS			0x7E
> > > +#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
> > > +#define     DG1_UNCORE_INIT_COMPLETE		0x1
> > 
> > With s/DG1_CHECK_UNCORE_INIT_STATUS/DG1_CHECK_UNCORE_INIT_STATUS_COMPLETE or something similar that makes easy to understand that 0x1 is the response
> > of the DG1_CHECK_UNCORE_INIT_STATUS sub-command.
> 
> checking all the other users of skl_pcode_request() I don't see a
> pattern there. Examples:
> 
> ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>                          SKL_CDCLK_PREPARE_FOR_CHANGE,     
>                          SKL_CDCLK_READY_FOR_CHANGE,       
>                          SKL_CDCLK_READY_FOR_CHANGE, 3);   
> 
> ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,            
>                          GEN9_SAGV_DISABLE,                            
>                          GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 
>                          1);                                           
> 
> Giveng the current uses, I'd rather rename like:
> 
> +#define   DG1_PCODE_STATUS			0x7E
> +#define     DG1_UNCORE_GET_INIT_STATUS		0x0
> +#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> 
> 
> > Reviewed-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> 
> does that still stands with the rename above?

LGTM, keep it please.

> 
> thanks
> Lucas De Marchi
> 
> > 
> > >  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> > >  #define GEN6_PCODE_DATA				_MMIO(0x138128)
> > >  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > > index 916ccd1c0e96..8b093525240d 100644
> > > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > > @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> > >  	return ret ? ret : status;
> > >  #undef COND
> > >  }
> > > +
> > > +void intel_pcode_init(struct drm_i915_private *i915)
> > > +{
> > > +	int ret;
> > > +
> > > +	if (!IS_DGFX(i915))
> > > +		return;
> > > +
> > > +	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
> > > +				DG1_CHECK_UNCORE_INIT_STATUS,
> > > +				DG1_UNCORE_INIT_COMPLETE,
> > > +				DG1_UNCORE_INIT_COMPLETE, 50);
> > > +	if (ret)
> > > +		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> > > index 7fb95745a444..094c7b19c5d4 100644
> > > --- a/drivers/gpu/drm/i915/intel_sideband.h
> > > +++ b/drivers/gpu/drm/i915/intel_sideband.h
> > > @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
> > >  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> > >  		      u32 reply_mask, u32 reply, int timeout_base_ms);
> > > 
> > > +void intel_pcode_init(struct drm_i915_private *i915);
> > > +
> > >  #endif /* _INTEL_SIDEBAND_H */
> > > 
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Re: [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6

[Lucas De Marchi]

On Mon, Aug 03, 2020 at 04:33:45PM -0700, Jose Souza wrote:
>On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> From: Anshuman Gupta <
>> anshuman.gupta@intel.com
>> >
>>
>> DC6 is not supported on DG1, so change the allowed DC mask for DG1.
>>
>> Cc: Uma Shankar <
>> uma.shankar@intel.com
>> >
>> Signed-off-by: Anshuman Gupta <
>> anshuman.gupta@intel.com
>> >
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 21f39c94056e..389a0f2d3a14 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>>  	int max_dc;
>>
>>  	if (INTEL_GEN(dev_priv) >= 12) {
>> -		max_dc = 4;
>> +		if (IS_DG1(dev_priv))
>
>Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it.
>With this change:

that doesn't seem true... it's more a dg1 thing than general dgfx

Lucas De Marchi

>Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
>> +			max_dc = 3;
>> +		else
>> +			max_dc = 4;
>>  		/*
>>  		 * DC9 has a separate HW flow from the rest of the DC states,
>>  		 * not depending on the DMC firmware. It's needed by system
>>
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