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From: Aurabindo Pillai <aurabindo.pillai@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Eryk Brol <eryk.brol@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	Qingqing.Zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	Aurabindo.Pillai@amd.com, Mikita Lipski <Mikita.Lipski@amd.com>,
	Bhawanpreet.Lakha@amd.com
Subject: [PATCH 06/16] drm/amd/display: DSC Bit target rate debugfs write entry
Date: Thu, 30 Jul 2020 15:11:36 -0400	[thread overview]
Message-ID: <20200730191146.33112-7-aurabindo.pillai@amd.com> (raw)
In-Reply-To: <20200730191146.33112-1-aurabindo.pillai@amd.com>

From: Eryk Brol <eryk.brol@amd.com>

[Why]
We need to be able to specify bits per pixel for DSC on any
connector.

[How]
Overwrite computed DSC target rate in dsc_cfg, with requested value.
Overwrites for both SST and MST connectors, but in different places, but the process is identical. Overwrites only if DSC is decided to be enabled on that connector.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 86 +++++++++++++++++++
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   |  9 +-
 4 files changed, 98 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 29570ce77967..a64c2d5789df 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4751,6 +4751,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
 			if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_slice_height)
 				stream->timing.dsc_cfg.num_slices_v = DIV_ROUND_UP(stream->timing.v_addressable,
 									aconnector->dsc_settings.dsc_slice_height);
+
+			if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
+				stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
 		}
 #endif
 	}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 333813ede0c7..3114f6e938e3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -346,6 +346,7 @@ struct dsc_preferred_settings {
 	bool dsc_clock_en;
 	uint32_t dsc_slice_width;
 	uint32_t dsc_slice_height;
+	uint32_t dsc_bits_per_pixel;
 };
 
 struct amdgpu_dm_connector {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 971b75a52e89..33e87f508991 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1441,6 +1441,18 @@ static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
 	return size;
 }
 
+/* function: read DSC target rate on the connector in bits per pixel
+ *
+ * The read function: dp_dsc_bits_per_pixel_read
+ * returns target rate of compression in bits per pixel
+ * The return is an integer: 0 or other positive integer
+ *
+ * Access it with the following command:
+ *
+ *	cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
+ *
+ *  0 - means that DSC is disabled
+ */
 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
 				    size_t size, loff_t *pos)
 {
@@ -1498,6 +1510,79 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
 	return result;
 }
 
+/* function: write DSC target rate in bits per pixel
+ *
+ * The write function: dp_dsc_bits_per_pixel_write
+ * overwrites automatically generated DSC configuration
+ * of DSC target bit rate.
+ *
+ * Also the user has to write bpp in hexidecimal
+ * rather than in decimal.
+ *
+ * Writing DSC settings is done with the following command:
+ * - To force overwrite rate (example sets to 256 bpp x 1/16):
+ *
+ *	echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
+ *
+ *  - To stop overwriting and let driver find the optimal rate,
+ * set the rate to zero:
+ *
+ *	echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
+ *
+ */
+static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
+				     size_t size, loff_t *pos)
+{
+	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
+	struct pipe_ctx *pipe_ctx;
+	int i;
+	char *wr_buf = NULL;
+	uint32_t wr_buf_size = 42;
+	int max_param_num = 1;
+	uint8_t param_nums = 0;
+	long param[1] = {0};
+
+	if (size == 0)
+		return -EINVAL;
+
+	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
+
+	if (!wr_buf) {
+		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
+		return -ENOSPC;
+	}
+
+	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
+					    (long *)param, buf,
+					    max_param_num,
+					    &param_nums)) {
+		kfree(wr_buf);
+		return -EINVAL;
+	}
+
+	if (param_nums <= 0) {
+		DRM_DEBUG_DRIVER("user data not be read\n");
+		kfree(wr_buf);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < MAX_PIPES; i++) {
+		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
+			if (pipe_ctx && pipe_ctx->stream &&
+			    pipe_ctx->stream->link == aconnector->dc_link)
+				break;
+	}
+
+	if (!pipe_ctx || !pipe_ctx->stream)
+		goto done;
+
+	aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
+
+done:
+	kfree(wr_buf);
+	return size;
+}
+
 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
 				    size_t size, loff_t *pos)
 {
@@ -1758,6 +1843,7 @@ static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
 	.owner = THIS_MODULE,
 	.read = dp_dsc_bits_per_pixel_read,
+	.write = dp_dsc_bits_per_pixel_write,
 	.llseek = default_llseek
 };
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index d433949fe53a..9ef7492e4d3b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -474,6 +474,7 @@ struct dsc_mst_fairness_params {
 	bool clock_overwrite;
 	uint32_t slice_width_overwrite;
 	uint32_t slice_height_overwrite;
+	uint32_t bpp_overwrite;
 };
 
 struct dsc_mst_fairness_vars {
@@ -507,7 +508,12 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
 					params[i].timing,
 					&params[i].timing->dsc_cfg)) {
 			params[i].timing->flags.DSC = 1;
-			params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
+
+			if (params[i].bpp_overwrite)
+				params[i].timing->dsc_cfg.bits_per_pixel = params[i].bpp_overwrite;
+			else
+				params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16;
+
 			if (params[i].slice_width_overwrite)
 				params[i].timing->dsc_cfg.num_slices_h = DIV_ROUND_UP(
 										params[i].timing->h_addressable,
@@ -735,6 +741,7 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 			debugfs_overwrite = true;
 		params[count].slice_width_overwrite = aconnector->dsc_settings.dsc_slice_width;
 		params[count].slice_height_overwrite = aconnector->dsc_settings.dsc_slice_height;
+		params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel;
 		params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
 		dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
 		if (!dc_dsc_compute_bandwidth_range(
-- 
2.25.1

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  parent reply	other threads:[~2020-07-30 19:12 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-30 19:11 [PATCH 00/16] DC Patches 2020 July 27 Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 01/16] drm/amd/display: DSC Slice height debugfs write entry Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 02/16] drm/amd/display: Update virtual stream encoder Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 03/16] drm/amd/display: Use parameter for call to set output mux Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 04/16] drm/amd/display: Read VBIOS Golden Settings Tbl Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 05/16] drm/amd/display: populate new dml variable Aurabindo Pillai
2020-07-30 19:11 ` Aurabindo Pillai [this message]
2020-07-30 19:11 ` [PATCH 07/16] drm/amd/display: Fix logger context Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 08/16] drm/amd/display: Comments on how to use DSC debugfs some entries Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 09/16] drm/amd/display: AMD OUI (DPCD 0x00300) skipped on some sink Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 10/16] drm/amd/display: Use helper function to check for HDMI signal Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 11/16] drm/amd/display: Change null plane state swizzle mode to 4kb_s Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 12/16] drm/amd/display: Display goes blank after inst Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 13/16] drm/amd/display: Add debugfs for forcing stream timing sync Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 14/16] drm/amd/display: Separate pipe disconnect from rest of progrmaming Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 15/16] drm/amd/display: [FW Promotion] Release 0.0.27 Aurabindo Pillai
2020-07-30 19:11 ` [PATCH 16/16] drm/amd/display: 3.2.97 Aurabindo Pillai

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