From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E75E5C433DF for ; Mon, 10 Aug 2020 09:50:56 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0F8F206B5 for ; Mon, 10 Aug 2020 09:50:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="wB2YZLf6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0F8F206B5 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=X3bt49Z+kxijR32fLt0ExPYwXLWgbcQtxRNsF28YR2I=; b=wB2YZLf6fTErkj2eZrU+JQQag EDlas0ztn/34vhe/z0qTku7/hY9R8LemAWyJpP6qaIL0TJUglONceK00rOsYjJXa9Cz17QL2d3qOm wKw0kWIzUz6VmIu/ylfA8b1TZVrroR3PRN9mjgM6STzmhZ75iQ9tHAOEh1Aepzaqnynkm5s6Sb6Ft Lq3ZSTxisXpJI7W4ZcjSzMQ/rumNg9ZS70D2QV9EU+ZnhkoFwxqM1b8L4h0Xh0TyvyGRx852y8tmu D3QmbbmeTa6Lat2J0y0AskREUT9qg0E5YSXl7+v4aNFneZFzLSOtG6V+zaex9mKh2tEst2fBVdAnl yYIgRPjYA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k54Qs-0003hU-LA; Mon, 10 Aug 2020 09:49:30 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k54Qp-0003h1-L3; Mon, 10 Aug 2020 09:49:28 +0000 Received: from gaia (unknown [95.146.230.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 33F0F206B5; Mon, 10 Aug 2020 09:49:26 +0000 (UTC) Date: Mon, 10 Aug 2020 10:49:23 +0100 From: Catalin Marinas To: Jason Mielke Subject: Re: Why invalidate d-cache if MMU and d-cache are disabled by rule? Message-ID: <20200810094923.GA27780@gaia> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200810_054927_768886_9F06364A X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, linux-arm@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org (adding linux-arm-kernel for kernel questions) On Sun, Aug 09, 2020 at 05:08:01PM +0200, Jason Mielke wrote: > Trying to understand the > > preserve_boot_args > > function in > > arch/arm64/kernel/head.S > > The function has a call to invalidate the 32 bytes of dcache area > > SYM_CODE_START_LOCAL(preserve_boot_args) > mov x21, x0 // x21=FDT > > adr_l x0, boot_args // record the contents of > stp x21, x1, [x0] // x0 .. x3 at kernel entry > stp x2, x3, [x0, #16] > > dmb sy // needed before dc ivac with > // MMU off > > mov x1, #0x20 // 4 x 8 bytes > b __inval_dcache_area // tail call > SYM_CODE_END(preserve_boot_args) > > This even though the MMU and d-cache must be disabled That's because when the MMU will be enabled, the cache may contain stale data for this address and a subsequent load may not see what was actually written with the MMU/caches disabled. Some examples: - the CPU on reset does not guarantee that the cache won't contain stale information - a boot-loader may have turned the MMU on, before Linux and caches were populated - if running as a guest, the hypervisor probably already maps large chunks of memory as cacheable with the MMU enabled So in all the above examples, the cache may have stale entries prior to the store with the MMU disabled. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel