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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id o2sm10700992lfi.50.2020.08.10.07.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2020 07:32:55 -0700 (PDT) Date: Mon, 10 Aug 2020 16:32:55 +0200 From: "Edgar E. Iglesias" To: Vikram Garhwal Subject: Re: [PATCH v8 2/4] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Message-ID: <20200810143255.GB2954729@toto> References: <1596575505-163040-1-git-send-email-fnu.vikram@xilinx.com> <1596575505-163040-3-git-send-email-fnu.vikram@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1596575505-163040-3-git-send-email-fnu.vikram@xilinx.com> Received-SPF: pass client-ip=2a00:1450:4864:20::242; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x242.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: francisco.iglesias@xilinx.com, Alistair Francis , qemu-devel@nongnu.org, "open list:Xilinx ZynqMP" , Peter Maydell Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Aug 04, 2020 at 02:11:43PM -0700, Vikram Garhwal wrote: > Connect CAN0 and CAN1 on the ZynqMP. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Vikram Garhwal > --- > hw/arm/xlnx-zcu102.c | 20 ++++++++++++++++++++ > hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ > include/hw/arm/xlnx-zynqmp.h | 8 ++++++++ > 3 files changed, 62 insertions(+) > > diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c > index 5997262..c3e3420 100644 > --- a/hw/arm/xlnx-zcu102.c > +++ b/hw/arm/xlnx-zcu102.c > @@ -24,6 +24,7 @@ > #include "qemu/log.h" > #include "sysemu/qtest.h" > #include "sysemu/device_tree.h" > +#include "net/can_emu.h" > > typedef struct XlnxZCU102 { > MachineState parent_obj; > @@ -33,6 +34,8 @@ typedef struct XlnxZCU102 { > bool secure; > bool virt; > > + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; > + > struct arm_boot_info binfo; > } XlnxZCU102; > > @@ -125,6 +128,14 @@ static void xlnx_zcu102_init(MachineState *machine) > object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, > &error_fatal); > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + gchar *bus_name = g_strdup_printf("canbus%d", i); > + > + object_property_set_link(OBJECT(&s->soc), bus_name, > + OBJECT(s->canbus[i]), &error_fatal); > + g_free(bus_name); > + } > + > qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); > > /* Create and plug in the SD cards */ > @@ -220,6 +231,15 @@ static void xlnx_zcu102_machine_instance_init(Object *obj) > "Set on/off to enable/disable emulating a " > "guest CPU which implements the ARM " > "Virtualization Extensions"); > + object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS, > + (Object **)&s->canbus[0], > + object_property_allow_set_link, > + 0); > + > + object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS, > + (Object **)&s->canbus[1], > + object_property_allow_set_link, > + 0); > } > > static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index c435b9d..adad3e7 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { > 21, 22, > }; > > +static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { > + 0xFF060000, 0xFF070000, > +}; > + > +static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { > + 23, 24, > +}; > + > static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { > 0xFF160000, 0xFF170000, > }; > @@ -243,6 +251,11 @@ static void xlnx_zynqmp_init(Object *obj) > TYPE_CADENCE_UART); > } > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + object_initialize_child(obj, "can[*]", &s->can[i], > + TYPE_XLNX_ZYNQMP_CAN); > + } > + > object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); > > for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { > @@ -480,6 +493,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > gic_spi[uart_intr[i]]); > } > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", > + XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); > + > + object_property_set_link(OBJECT(&s->can[i]), "canbus", > + OBJECT(s->canbus[i]), &error_fatal); > + > + sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, > + gic_spi[can_intr[i]]); > + } > + > object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, > &error_abort); > if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { > @@ -617,6 +647,10 @@ static Property xlnx_zynqmp_props[] = { > DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), > DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION, > MemoryRegion *), > + DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, > + CanBusState *), > + DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, > + CanBusState *), > DEFINE_PROP_END_OF_LIST() > }; > > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 53076fa..8cada69 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -22,6 +22,7 @@ > #include "hw/intc/arm_gic.h" > #include "hw/net/cadence_gem.h" > #include "hw/char/cadence_uart.h" > +#include "hw/net/xlnx-zynqmp-can.h" > #include "hw/ide/ahci.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/xilinx_spips.h" > @@ -32,6 +33,7 @@ > #include "hw/rtc/xlnx-zynqmp-rtc.h" > #include "hw/cpu/cluster.h" > #include "target/arm/cpu.h" > +#include "net/can_emu.h" > > #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" > #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ > @@ -41,6 +43,8 @@ > #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 > #define XLNX_ZYNQMP_NUM_GEMS 4 > #define XLNX_ZYNQMP_NUM_UARTS 2 > +#define XLNX_ZYNQMP_NUM_CAN 2 > +#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) > #define XLNX_ZYNQMP_NUM_SDHCI 2 > #define XLNX_ZYNQMP_NUM_SPIS 2 > #define XLNX_ZYNQMP_NUM_GDMA_CH 8 > @@ -92,6 +96,7 @@ typedef struct XlnxZynqMPState { > > CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; > CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; > + XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; > SysbusAHCIState sata; > SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; > XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; > @@ -112,6 +117,9 @@ typedef struct XlnxZynqMPState { > bool virt; > /* Has the RPU subsystem? */ > bool has_rpu; > + > + /* CAN bus. */ > + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; > } XlnxZynqMPState; > > #endif > -- > 2.7.4 >