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2020 11:05:12 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 17 Aug 2020 11:05:09 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 17 Aug 2020 11:05:09 +0800 From: Crystal Guo To: , , CC: , , , , , , , , , , , , Crystal Guo Subject: [v4,3/4] reset-controller: ti: introduce a new reset handler Date: Mon, 17 Aug 2020 11:03:23 +0800 Message-ID: <20200817030324.5690-4-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200817030324.5690-1-crystal.guo@mediatek.com> References: <20200817030324.5690-1-crystal.guo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SW50cm9kdWNlIHRpX3N5c2Nvbl9yZXNldCgpIHRvIGludGVncmF0ZSBhc3NlcnQgYW5kIGRlYXNz ZXJ0IHRvZ2V0aGVyLg0KSWYgc29tZSBtb2R1bGVzIG5lZWQgZG8gc2VyaWFsaXplZCBhc3NlcnQg YW5kIGRlYXNzZXJ0IG9wZXJhdGlvbnMNCnRvIHJlc2V0IGl0c2VsZiwgcmVzZXRfY29udHJvbF9y ZXNldCBjYW4gYmUgY2FsbGVkIGZvciBjb252ZW5pZW5jZS4NCg0KU3VjaCBhcyByZXNldC1xY29t LWFvc3MuYywgaXQgaW50ZWdyYXRlcyBhc3NlcnQgYW5kIGRlYXNzZXJ0IHRvZ2V0aGVyDQpieSAn cmVzZXQnIG1ldGhvZC4gTVRLIFNvY3MgYWxzbyBuZWVkIHRoaXMgbWV0aG9kIHRvIHBlcmZvcm0g cmVzZXQuDQoNClNpZ25lZC1vZmYtYnk6IENyeXN0YWwgR3VvIDxjcnlzdGFsLmd1b0BtZWRpYXRl ay5jb20+DQotLS0NCiBkcml2ZXJzL3Jlc2V0L3Jlc2V0LXRpLXN5c2Nvbi5jIHwgMjYgKysrKysr KysrKysrKysrKysrKysrKysrLS0NCiAxIGZpbGUgY2hhbmdlZCwgMjQgaW5zZXJ0aW9ucygrKSwg MiBkZWxldGlvbnMoLSkNCg0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvcmVzZXQvcmVzZXQtdGktc3lz Y29uLmMgYi9kcml2ZXJzL3Jlc2V0L3Jlc2V0LXRpLXN5c2Nvbi5jDQppbmRleCBhMjYzNWMyMWRi N2YuLjA4Mjg5MzQyZjlhZiAxMDA2NDQNCi0tLSBhL2RyaXZlcnMvcmVzZXQvcmVzZXQtdGktc3lz Y29uLmMNCisrKyBiL2RyaXZlcnMvcmVzZXQvcmVzZXQtdGktc3lzY29uLmMNCkBAIC0xNSw2ICsx NSw3IEBADQogICogR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgZm9yIG1vcmUgZGV0YWlscy4N CiAgKi8NCiANCisjaW5jbHVkZSA8bGludXgvZGVsYXkuaD4NCiAjaW5jbHVkZSA8bGludXgvbWZk L3N5c2Nvbi5oPg0KICNpbmNsdWRlIDxsaW51eC9tb2R1bGUuaD4NCiAjaW5jbHVkZSA8bGludXgv b2YuaD4NCkBAIC01Niw2ICs1Nyw3IEBAIHN0cnVjdCB0aV9zeXNjb25fcmVzZXRfZGF0YSB7DQog CXN0cnVjdCByZWdtYXAgKnJlZ21hcDsNCiAJc3RydWN0IHRpX3N5c2Nvbl9yZXNldF9jb250cm9s ICpjb250cm9sczsNCiAJdW5zaWduZWQgaW50IG5yX2NvbnRyb2xzOw0KKwl1bnNpZ25lZCBpbnQg cmVzZXRfZHVyYXRpb25fdXM7DQogfTsNCiANCiAjZGVmaW5lIHRvX3RpX3N5c2Nvbl9yZXNldF9k YXRhKHJjZGV2KQlcDQpAQCAtODksNyArOTEsNyBAQCBzdGF0aWMgaW50IHRpX3N5c2Nvbl9yZXNl dF9hc3NlcnQoc3RydWN0IHJlc2V0X2NvbnRyb2xsZXJfZGV2ICpyY2RldiwNCiAJbWFzayA9IEJJ VChjb250cm9sLT5hc3NlcnRfYml0KTsNCiAJdmFsdWUgPSAoY29udHJvbC0+ZmxhZ3MgJiBBU1NF UlRfU0VUKSA/IG1hc2sgOiAweDA7DQogDQotCXJldHVybiByZWdtYXBfdXBkYXRlX2JpdHMoZGF0 YS0+cmVnbWFwLCBjb250cm9sLT5hc3NlcnRfb2Zmc2V0LCBtYXNrLCB2YWx1ZSk7DQorCXJldHVy biByZWdtYXBfd3JpdGVfYml0cyhkYXRhLT5yZWdtYXAsIGNvbnRyb2wtPmFzc2VydF9vZmZzZXQs IG1hc2ssIHZhbHVlKTsNCiB9DQogDQogLyoqDQpAQCAtMTIwLDcgKzEyMiw3IEBAIHN0YXRpYyBp bnQgdGlfc3lzY29uX3Jlc2V0X2RlYXNzZXJ0KHN0cnVjdCByZXNldF9jb250cm9sbGVyX2RldiAq cmNkZXYsDQogCW1hc2sgPSBCSVQoY29udHJvbC0+ZGVhc3NlcnRfYml0KTsNCiAJdmFsdWUgPSAo Y29udHJvbC0+ZmxhZ3MgJiBERUFTU0VSVF9TRVQpID8gbWFzayA6IDB4MDsNCiANCi0JcmV0dXJu IHJlZ21hcF91cGRhdGVfYml0cyhkYXRhLT5yZWdtYXAsIGNvbnRyb2wtPmRlYXNzZXJ0X29mZnNl dCwgbWFzaywgdmFsdWUpOw0KKwlyZXR1cm4gcmVnbWFwX3dyaXRlX2JpdHMoZGF0YS0+cmVnbWFw LCBjb250cm9sLT5kZWFzc2VydF9vZmZzZXQsIG1hc2ssIHZhbHVlKTsNCiB9DQogDQogLyoqDQpA QCAtMTU4LDkgKzE2MCwyNiBAQCBzdGF0aWMgaW50IHRpX3N5c2Nvbl9yZXNldF9zdGF0dXMoc3Ry dWN0IHJlc2V0X2NvbnRyb2xsZXJfZGV2ICpyY2RldiwNCiAJCSEoY29udHJvbC0+ZmxhZ3MgJiBT VEFUVVNfU0VUKTsNCiB9DQogDQorc3RhdGljIGludCB0aV9zeXNjb25fcmVzZXQoc3RydWN0IHJl c2V0X2NvbnRyb2xsZXJfZGV2ICpyY2RldiwNCisJCQkJICB1bnNpZ25lZCBsb25nIGlkKQ0KK3sN CisJc3RydWN0IHRpX3N5c2Nvbl9yZXNldF9kYXRhICpkYXRhID0gdG9fdGlfc3lzY29uX3Jlc2V0 X2RhdGEocmNkZXYpOw0KKwlpbnQgcmV0Ow0KKw0KKwlyZXQgPSB0aV9zeXNjb25fcmVzZXRfYXNz ZXJ0KHJjZGV2LCBpZCk7DQorCWlmIChyZXQpDQorCQlyZXR1cm4gcmV0Ow0KKw0KKwlpZiAoZGF0 YS0+cmVzZXRfZHVyYXRpb25fdXMpDQorCQl1c2xlZXBfcmFuZ2UoZGF0YS0+cmVzZXRfZHVyYXRp b25fdXMsIGRhdGEtPnJlc2V0X2R1cmF0aW9uX3VzICogMik7DQorDQorCXJldHVybiB0aV9zeXNj b25fcmVzZXRfZGVhc3NlcnQocmNkZXYsIGlkKTsNCit9DQorDQogc3RhdGljIGNvbnN0IHN0cnVj dCByZXNldF9jb250cm9sX29wcyB0aV9zeXNjb25fcmVzZXRfb3BzID0gew0KIAkuYXNzZXJ0CQk9 IHRpX3N5c2Nvbl9yZXNldF9hc3NlcnQsDQogCS5kZWFzc2VydAk9IHRpX3N5c2Nvbl9yZXNldF9k ZWFzc2VydCwNCisJLnJlc2V0CQk9IHRpX3N5c2Nvbl9yZXNldCwNCiAJLnN0YXR1cwkJPSB0aV9z eXNjb25fcmVzZXRfc3RhdHVzLA0KIH07DQogDQpAQCAtMjA0LDYgKzIyMyw5IEBAIHN0YXRpYyBp bnQgdGlfc3lzY29uX3Jlc2V0X3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpDQog CQljb250cm9sc1tpXS5mbGFncyA9IGJlMzJfdG9fY3B1cChsaXN0KyspOw0KIAl9DQogDQorCW9m X3Byb3BlcnR5X3JlYWRfdTMyKHBkZXYtPmRldi5vZl9ub2RlLAkicmVzZXQtZHVyYXRpb24tdXMi LA0KKwkJCQkmZGF0YS0+cmVzZXRfZHVyYXRpb25fdXMpOw0KKw0KIAlkYXRhLT5yY2Rldi5vcHMg PSAmdGlfc3lzY29uX3Jlc2V0X29wczsNCiAJZGF0YS0+cmNkZXYub3duZXIgPSBUSElTX01PRFVM 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MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 17 Aug 2020 11:05:09 +0800 From: Crystal Guo To: , , Subject: [v4,3/4] reset-controller: ti: introduce a new reset handler Date: Mon, 17 Aug 2020 11:03:23 +0800 Message-ID: <20200817030324.5690-4-crystal.guo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200817030324.5690-1-crystal.guo@mediatek.com> References: <20200817030324.5690-1-crystal.guo@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200816_230521_080838_601E9D5B X-CRM114-Status: GOOD ( 14.37 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, yong.liang@mediatek.com, stanley.chu@mediatek.com, srv_heupstream@mediatek.com, seiya.wang@mediatek.com, linux-kernel@vger.kernel.org, afd@ti.com, fan.chen@mediatek.com, Crystal Guo , linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, s-anna@ti.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Introduce ti_syscon_reset() to integrate assert and deassert together. If some modules need do serialized assert and deassert operations to reset itself, reset_control_reset can be called for convenience. Such as reset-qcom-aoss.c, it integrates assert and deassert together by 'reset' method. MTK Socs also need this method to perform reset. Signed-off-by: Crystal Guo --- drivers/reset/reset-ti-syscon.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index a2635c21db7f..08289342f9af 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -56,6 +57,7 @@ struct ti_syscon_reset_data { struct regmap *regmap; struct ti_syscon_reset_control *controls; unsigned int nr_controls; + unsigned int reset_duration_us; }; #define to_ti_syscon_reset_data(rcdev) \ @@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, mask = BIT(control->assert_bit); value = (control->flags & ASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); } /** @@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, mask = BIT(control->deassert_bit); value = (control->flags & DEASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); } /** @@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, !(control->flags & STATUS_SET); } +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev); + int ret; + + ret = ti_syscon_reset_assert(rcdev, id); + if (ret) + return ret; + + if (data->reset_duration_us) + usleep_range(data->reset_duration_us, data->reset_duration_us * 2); + + return ti_syscon_reset_deassert(rcdev, id); +} + static const struct reset_control_ops ti_syscon_reset_ops = { .assert = ti_syscon_reset_assert, .deassert = ti_syscon_reset_deassert, + .reset = ti_syscon_reset, .status = ti_syscon_reset_status, }; @@ -204,6 +223,9 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) controls[i].flags = be32_to_cpup(list++); } + of_property_read_u32(pdev->dev.of_node, "reset-duration-us", + &data->reset_duration_us); + data->rcdev.ops = &ti_syscon_reset_ops; data->rcdev.owner = THIS_MODULE; data->rcdev.of_node = np; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 539D7C433DF for ; Mon, 17 Aug 2020 03:06:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 20D7A2087D for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Introduce ti_syscon_reset() to integrate assert and deassert together. If some modules need do serialized assert and deassert operations to reset itself, reset_control_reset can be called for convenience. Such as reset-qcom-aoss.c, it integrates assert and deassert together by 'reset' method. MTK Socs also need this method to perform reset. Signed-off-by: Crystal Guo --- drivers/reset/reset-ti-syscon.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index a2635c21db7f..08289342f9af 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -56,6 +57,7 @@ struct ti_syscon_reset_data { struct regmap *regmap; struct ti_syscon_reset_control *controls; unsigned int nr_controls; + unsigned int reset_duration_us; }; #define to_ti_syscon_reset_data(rcdev) \ @@ -89,7 +91,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, mask = BIT(control->assert_bit); value = (control->flags & ASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); } /** @@ -120,7 +122,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, mask = BIT(control->deassert_bit); value = (control->flags & DEASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); } /** @@ -158,9 +160,26 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev, !(control->flags & STATUS_SET); } +static int ti_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev); + int ret; + + ret = ti_syscon_reset_assert(rcdev, id); + if (ret) + return ret; + + if (data->reset_duration_us) + usleep_range(data->reset_duration_us, data->reset_duration_us * 2); + + return ti_syscon_reset_deassert(rcdev, id); +} + static const struct reset_control_ops ti_syscon_reset_ops = { .assert = ti_syscon_reset_assert, .deassert = ti_syscon_reset_deassert, + .reset = ti_syscon_reset, .status = ti_syscon_reset_status, }; @@ -204,6 +223,9 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) controls[i].flags = be32_to_cpup(list++); } + of_property_read_u32(pdev->dev.of_node, "reset-duration-us", + &data->reset_duration_us); + data->rcdev.ops = &ti_syscon_reset_ops; data->rcdev.owner = THIS_MODULE; data->rcdev.of_node = np; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel