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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id x9sm20699893pff.145.2020.08.17.09.38.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Aug 2020 09:38:45 -0700 (PDT) Date: Mon, 17 Aug 2020 10:38:43 -0600 From: Mathieu Poirier To: Tingwei Zhang Subject: Re: [PATCH v8 19/24] coresight: cti: don't disable ect device if it's not enabled Message-ID: <20200817163843.GD3614061@xps15> References: <20200807111153.7784-1-tingwei@codeaurora.org> <20200807111153.7784-20-tingwei@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200807111153.7784-20-tingwei@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200817_123848_994005_BE56282A X-CRM114-Status: GOOD ( 24.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tsoni@codeaurora.org, Sai Prakash Ranjan , Kim Phillips , Mao Jinlong , Suzuki K Poulose , Alexander Shishkin , Greg Kroah-Hartman , coresight@lists.linaro.org, Randy Dunlap , Mian Yousaf Kaukab , Russell King , Leo Yan , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 07, 2020 at 07:11:48PM +0800, Tingwei Zhang wrote: > If associated ect device is not enabled at first place, disable > routine should not be called. Add ect_enabled flag to check whether > ect device is enabled. Fix the issue in below case. Ect device is > not available when associated coresight device enabled and the > association is established after coresight device is enabled. > > Signed-off-by: Mike Leach > Signed-off-by: Tingwei Zhang > --- > drivers/hwtracing/coresight/coresight.c | 11 ++++++++--- > include/linux/coresight.h | 1 + > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c > index d066411aa794..27ad8317e3cf 100644 > --- a/drivers/hwtracing/coresight/coresight.c > +++ b/drivers/hwtracing/coresight/coresight.c > @@ -245,13 +245,18 @@ coresight_control_assoc_ectdev(struct coresight_device *csdev, bool enable) > > if (!ect_csdev) > return 0; > + if ((!ect_ops(ect_csdev)->enable) || (!ect_ops(ect_csdev)->disable)) > + return 0; > > if (enable) { > - if (ect_ops(ect_csdev)->enable) > - ect_ret = ect_ops(ect_csdev)->enable(ect_csdev); > + ect_ret = ect_ops(ect_csdev)->enable(ect_csdev); > + if (!ect_ret) > + csdev->ect_enabled = true; > } else { > - if (ect_ops(ect_csdev)->disable) > + if (csdev->ect_enabled) { > ect_ret = ect_ops(ect_csdev)->disable(ect_csdev); > + csdev->ect_enabled = false; > + } > } > > /* output warning if ECT enable is preventing trace operation */ > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index 3bb738f9a326..7d3c87e5b97c 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -208,6 +208,7 @@ struct coresight_device { > /* sysfs links between components */ > int nr_links; > bool has_conns_grp; > + bool ect_enabled; /* true only if associated ect device is enabled */ We have cti_config::enable_req_count and cti_config::hw_enabled, both used in cti_enable_hw() and cti_disable_hw(). I would have thought they'd be sufficient to address the counting problems. If they are not I would much rather see a solution confined to the cti driver than in the core itself. Thanks, Mathieu > }; > > /* > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel