[PATCH v1 0/4] WiFi SDIO fixes and improvements for Acer A500 and Nexus 7

[PATCH v1 0/4] WiFi SDIO fixes and improvements for Acer A500 and Nexus 7

[Dmitry Osipenko]

Hello!

I was debugging WiFi performance problems that I started to notice on
Acer A500 and found couple problems. One discovered problem lays in a
wrong SDIO PINCTRL configuration of A500 device-tree, others are found
in MMC core and brcmfmac driver.

This series fixes the PINCTRL configuration and improves MMC clock setup
of Acer A500 and Nexus 7 WiFi.

Big thanks to Wright Feng of Cypress who indirectly helped me to notice the
PINCTRL bug by showing MMC IOS info of the BCM4329 setup that Wright uses,
it lead me to re-check to the PINCTRL configuration!

Dmitry Osipenko (4):
  ARM: tegra: acer-a500: Correct PINCTRL configuration
  ARM: tegra: acer-a500: Set WiFi MMC clock rate to 50MHz
  ARM: tegra: acer-a500: Use PLLC for WiFi MMC clk parent
  ARM: tegra: nexus7: Use PLLC for WiFi MMC clk parent

 .../arm/boot/dts/tegra20-acer-a500-picasso.dts | 18 +++++++++++++++---
 .../tegra30-asus-nexus7-grouper-common.dtsi    |  5 +++++
 2 files changed, 20 insertions(+), 3 deletions(-)

-- 
2.27.0

[PATCH v1 1/4] ARM: tegra: acer-a500: Correct PINCTRL configuration

[Dmitry Osipenko]

The low-power-mode drive was set to DIV_4 for some of PINCTRL groups,
while these groups should use DIV_1. This patch fixes the wrong PINCTRL
configurations and adds a full drive-setup for the changed configs, just
for completeness since the added values match the default configuration.

Now WiFi SDIO communication works properly using legacy signaling mode if
SDIO BUS clocked at 50MHz, which is a maximum SDIO clock rate on Tegra20.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index f92712e4bd34..8b4912db0d20 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -314,16 +314,24 @@ drive_ddc {
 				nvidia,pins = "drive_ddc",
 						"drive_vi1",
 						"drive_sdio1";
+				nvidia,pull-up-strength = <31>;
+				nvidia,pull-down-strength = <31>;
 				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
-				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>;
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
+				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
 			};
 			drive_dbg {
 				nvidia,pins = "drive_dbg",
 						"drive_vi2",
 						"drive_at1",
 						"drive_ao1";
+				nvidia,pull-up-strength = <31>;
+				nvidia,pull-down-strength = <31>;
 				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
-				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>;
+				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
+				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
 				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
 				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
 			};
-- 
2.27.0

[PATCH v1 2/4] ARM: tegra: acer-a500: Set WiFi MMC clock rate to 50MHz

[Dmitry Osipenko]

Previously 50MHz clock rate didn't work because of the wrong PINCTRL
configuration used for SDIO pins. Now the PINCTRL config is corrected
and the MMC clock rate could be bumped safely to 50MHz, increasing WiFi
TX throughput by 20 Mbit/s and allowing to hit the maximum 40 Mbit/s.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index 8b4912db0d20..b89e9398f681 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -744,7 +744,7 @@ mmc@c8000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		max-frequency = <25000000>;
+		max-frequency = <50000000>;
 		keep-power-in-suspend;
 		bus-width = <4>;
 		non-removable;
-- 
2.27.0

[PATCH v1 3/4] ARM: tegra: acer-a500: Use PLLC for WiFi MMC clk parent

[Dmitry Osipenko]

The default parent for all MMCs is PLLP, which is running at 216MHz on
Tegra20 and 50MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50MHz, but this rate isn't achievable using PLLP.

Let's switch the WiFi MMC clk parent to PLLC in order to get true 50MHz.
This patch doesn't fix any problems, it's just a minor improvement.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index b89e9398f681..ab3c378e5519 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -744,6 +744,10 @@ mmc@c8000000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+		assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
+		assigned-clock-rates = <50000000>;
+
 		max-frequency = <50000000>;
 		keep-power-in-suspend;
 		bus-width = <4>;
-- 
2.27.0

[PATCH v1 4/4] ARM: tegra: nexus7: Use PLLC for WiFi MMC clk parent

[Dmitry Osipenko]

The default parent for all MMCs is PLLP, which is running at 408MHz on
Tegra30 and 50MHz clock can't be derived from PLLP. The maximum SDIO
clock rate is 50MHz, but this rate isn't achievable using PLLP.

Let's switch the WiFi MMC clk parent to PLLC in order to get true 50MHz.
This patch doesn't fix any problems, it's just a minor improvement.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
index 903457292c04..21387a91c40f 100644
--- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
@@ -976,6 +976,11 @@ mmc@78000400 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
+		assigned-clock-rates = <50000000>;
+
+		max-frequency = <50000000>;
 		keep-power-in-suspend;
 		bus-width = <4>;
 		non-removable;
-- 
2.27.0

Re: [PATCH v1 0/4] WiFi SDIO fixes and improvements for Acer A500 and Nexus 7

[Thierry Reding]

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On Sun, Aug 23, 2020 at 05:47:21PM +0300, Dmitry Osipenko wrote:
> Hello!
> 
> I was debugging WiFi performance problems that I started to notice on
> Acer A500 and found couple problems. One discovered problem lays in a
> wrong SDIO PINCTRL configuration of A500 device-tree, others are found
> in MMC core and brcmfmac driver.
> 
> This series fixes the PINCTRL configuration and improves MMC clock setup
> of Acer A500 and Nexus 7 WiFi.
> 
> Big thanks to Wright Feng of Cypress who indirectly helped me to notice the
> PINCTRL bug by showing MMC IOS info of the BCM4329 setup that Wright uses,
> it lead me to re-check to the PINCTRL configuration!
> 
> Dmitry Osipenko (4):
>   ARM: tegra: acer-a500: Correct PINCTRL configuration
>   ARM: tegra: acer-a500: Set WiFi MMC clock rate to 50MHz
>   ARM: tegra: acer-a500: Use PLLC for WiFi MMC clk parent
>   ARM: tegra: nexus7: Use PLLC for WiFi MMC clk parent
> 
>  .../arm/boot/dts/tegra20-acer-a500-picasso.dts | 18 +++++++++++++++---
>  .../tegra30-asus-nexus7-grouper-common.dtsi    |  5 +++++
>  2 files changed, 20 insertions(+), 3 deletions(-)

All patches applied to for-5.10/arm/dt, thanks.

Thierry

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