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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id 10sm345251ljn.22.2020.08.27.02.24.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2020 02:24:13 -0700 (PDT) Date: Thu, 27 Aug 2020 11:24:13 +0200 From: "Edgar E. Iglesias" To: Richard Henderson Subject: Re: [PATCH 64/77] target/microblaze: Convert mbar to decodetree Message-ID: <20200827092413.GL2954729@toto> References: <20200825205950.730499-1-richard.henderson@linaro.org> <20200825205950.730499-65-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200825205950.730499-65-richard.henderson@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::144; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x144.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 10 X-Spam_score: 1.0 X-Spam_bar: + X-Spam_report: (1.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=3.066, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Aug 25, 2020 at 01:59:37PM -0700, Richard Henderson wrote: > Split this out of the normal branch instructions, as it requires > special handling. End the TB only for an instruction barrier. > > Signed-off-by: Richard Henderson > --- > target/microblaze/insns.decode | 2 + > target/microblaze/translate.c | 81 ++++++++++++++++++---------------- > 2 files changed, 45 insertions(+), 38 deletions(-) > > diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode > index 53da2b75aa..77b073be9e 100644 > --- a/target/microblaze/insns.decode > +++ b/target/microblaze/insns.decode > @@ -124,6 +124,8 @@ lwea 110010 ..... ..... ..... 0001 000 0000 @typea > lwx 110010 ..... ..... ..... 1000 000 0000 @typea > lwi 111010 ..... ..... ................ @typeb > > +mbar 101110 imm:5 00010 0000 0000 0000 0100 > + > mul 010000 ..... ..... ..... 000 0000 0000 @typea > mulh 010000 ..... ..... ..... 000 0000 0001 @typea > mulhu 010000 ..... ..... ..... 000 0000 0011 @typea > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c > index fc1c661368..a391e80fb9 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -1166,6 +1166,48 @@ static bool trans_brki(DisasContext *dc, arg_typeb_br *arg) > return true; > } > > +static bool trans_mbar(DisasContext *dc, arg_mbar *arg) > +{ > + int mbar_imm = arg->imm; > + > + /* > + * Instruction access memory barrier. > + * End the TB so that we recognize self-modified code immediately. > + */ > + if (mbar_imm & 1) { > + dc->cpustate_changed = 1; > + } This should be (mbar_imm & 1) == 0 But even with that fixed it fails some of our tests because interrupts that should become visible within a couple of cycles after a memory data barrier can now be delayed longer. I think we should always break the TB. > + /* Data access memory barrier. */ > + if (mbar_imm & 2) { > + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); > + } This should be (mbar_imm & 2) == 0 > + > + /* Sleep. */ > + if (mbar_imm & 16) { > + TCGv_i32 tmp_1; > + > + if (trap_userspace(dc, true)) { > + /* Sleep is a privileged instruction. */ > + return true; > + } > + > + t_sync_flags(dc); > + > + tmp_1 = tcg_const_i32(1); > + tcg_gen_st_i32(tmp_1, cpu_env, > + -offsetof(MicroBlazeCPU, env) > + +offsetof(CPUState, halted)); > + tcg_temp_free_i32(tmp_1); > + > + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); > + > + gen_raise_exception(dc, EXCP_HLT); > + } > + return true; > +} > + > + > static void msr_read(DisasContext *dc, TCGv_i32 d) > { > TCGv_i32 t; > @@ -1447,50 +1489,13 @@ static void dec_bcc(DisasContext *dc) > > static void dec_br(DisasContext *dc) > { > - unsigned int dslot, link, abs, mbar; > + unsigned int dslot, link, abs; > uint32_t add_pc; > > dslot = dc->ir & (1 << 20); > abs = dc->ir & (1 << 19); > link = dc->ir & (1 << 18); > > - /* Memory barrier. */ > - mbar = (dc->ir >> 16) & 31; > - if (mbar == 2 && dc->imm == 4) { > - uint16_t mbar_imm = dc->rd; > - > - /* Data access memory barrier. */ > - if ((mbar_imm & 2) == 0) { > - tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); > - } > - > - /* mbar IMM & 16 decodes to sleep. */ > - if (mbar_imm & 16) { > - TCGv_i32 tmp_1; > - > - if (trap_userspace(dc, true)) { > - /* Sleep is a privileged instruction. */ > - return; > - } > - > - t_sync_flags(dc); > - > - tmp_1 = tcg_const_i32(1); > - tcg_gen_st_i32(tmp_1, cpu_env, > - -offsetof(MicroBlazeCPU, env) > - +offsetof(CPUState, halted)); > - tcg_temp_free_i32(tmp_1); > - > - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); > - > - gen_raise_exception(dc, EXCP_HLT); > - return; > - } > - /* Break the TB. */ > - dc->cpustate_changed = 1; > - return; > - } > - > if (dslot && dec_setup_dslot(dc)) { > return; > } > -- > 2.25.1 >