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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id v27sm645111lfi.79.2020.08.27.10.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Aug 2020 10:09:48 -0700 (PDT) Date: Thu, 27 Aug 2020 19:09:48 +0200 From: "Edgar E. Iglesias" To: Richard Henderson Subject: Re: [PATCH 00/77] target/microblaze improvements Message-ID: <20200827170948.GO2954729@toto> References: <20200825205950.730499-1-richard.henderson@linaro.org> <20200827091128.GK2954729@toto> <1628c0ac-db22-ef9d-22e2-6a167ceaaf55@linaro.org> <20200827102217.GN2954729@toto> <5a787d85-a75f-60cf-0c99-a40c84222b35@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5a787d85-a75f-60cf-0c99-a40c84222b35@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::244; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x244.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 18 X-Spam_score: 1.8 X-Spam_bar: + X-Spam_report: (1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=3.899, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Aug 27, 2020 at 04:19:44AM -0700, Richard Henderson wrote: > On 8/27/20 3:22 AM, Edgar E. Iglesias wrote: > > Thanks. Here's another issue, it seems some branches are jumping > > to the wrong address. > > > > This is a disasm from a failing case: > > > > 0x00000000ffd033a0: brlid r15, -636 // 0xffffffffffd03124 > > 0x00000000ffd033a4: or r0, r0, r0 > > > > 0x00000000ffa73124: Address 0xffa73124 is out of bounds. > > That's a weird one. > > My guess is that IMM_FLAG is set in iflags incorrectly. > Can you verify this with -d in_asm,op,exec? > > When IMM_FLAG is set, you'll see in in iflags: bit 0 will be set in the second > word of the insn_data. E.g.: > > ---- 00000000ffd033a0 0000000000000001 > > It would also show up in the tb_flags of the exec lines. E.g. > > Trace 0: 0x7f38a4000940 [0000000000000000/0000000090000058/0] > > where the format is host_pc [cs_base/pc/tb_flags]. > > > If so, then we'll need to check where iflags got out of sync. > It seems to be getting out of sync when getting a slave-error and the core is not setup to take exceptions for slave errors. Looks like a pre-existing bug where we're restoring CPU state without taking the exception. The following fixes that particular case in my runs. I'm on a backported QEMU 5.1 so thing may look different in master. diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 831ff2cac1..0cae51c2df 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -432,22 +432,19 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, cpu = MICROBLAZE_CPU(cs); env = &cpu->env; - cpu_restore_state(cs, retaddr, true); - if (!(env->msr & MSR_EE)) { + if (!cpu->cfg.iopb_bus_exception || !(env->msr & MSR_EE)) { return; } + cpu_restore_state(cs, retaddr, true); + env->ear = addr; if (access_type == MMU_INST_FETCH) { - if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) { - env->esr = ESR_EC_INSN_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); - } + env->esr = ESR_EC_INSN_BUS; + helper_raise_exception(env, EXCP_HW_EXCP); } else { - if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) { - env->esr = ESR_EC_DATA_BUS; - helper_raise_exception(env, EXCP_HW_EXCP); - } + env->esr = ESR_EC_DATA_BUS; + helper_raise_exception(env, EXCP_HW_EXCP); } } #endif