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Fri, 28 Aug 2020 18:39:16 +0200 (CEST) Date: Fri, 28 Aug 2020 18:39:16 +0200 From: Sebastian Reichel To: Lars Povlsen Subject: Re: [PATCH 3/5] dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property Message-ID: <20200828163916.g6vbk3anfyijl7sx@earth.universe> References: <20200513130842.24847-1-lars.povlsen@microchip.com> <20200513130842.24847-4-lars.povlsen@microchip.com> <20200528022502.GA3234572@bogus> <87wo4piyqz.fsf@soft-dev15.microsemi.net> MIME-Version: 1.0 In-Reply-To: <87wo4piyqz.fsf@soft-dev15.microsemi.net> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200828_123919_424472_98A8D860 X-CRM114-Status: GOOD ( 30.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: Rob Herring , Alexandre Belloni , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Microchip Linux Driver Support , SoC Team , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Content-Type: multipart/mixed; boundary="===============3135593473041272497==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============3135593473041272497== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="2uz6qofapxdsjq5b" Content-Disposition: inline --2uz6qofapxdsjq5b Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Tue, Jun 02, 2020 at 11:49:08AM +0200, Lars Povlsen wrote: > Rob Herring writes: > > On Wed, May 13, 2020 at 03:08:40PM +0200, Lars Povlsen wrote: > >> This documents the 'microchip,reset-switch-core' property in the > >> ocelot-reset driver. > >> > >> Signed-off-by: Lars Povlsen > >> --- > >> .../devicetree/bindings/power/reset/ocelot-reset.txt | 6 ++++++ > >> 1 file changed, 6 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-rese= t.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt > >> index 4d530d8154848..20fff03753ad2 100644 > >> --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt > >> +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt > >> @@ -9,9 +9,15 @@ microchip Sparx5 armv8 SoC's. > >> Required Properties: > >> - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-res= et" > >> > >> +Optional properties: > >> +- microchip,reset-switch-core : Perform a switch core reset at the > >> + time of driver load. This is may be used to initialize the switch > >> + core to a known state (before other drivers are loaded). > > > > How do you know when other drivers are loaded? This could be a module > > perhaps. Doesn't seem like something that belongs in DT. > > >=20 > The reset driver is loaded at postcore_initcall() time, which ensures it > is loaded before other drivers using the switch core. I noticed other > drivers do the same to do low-level system reset and initialization at > early boot time. >=20 > > Can this behavior be implied with "microchip,sparx5-chip-reset"? >=20 > Since we need to cater for both modus operandi, I would need two driver > compatible strings per platform, which scales worse than a single > property. >=20 > The "microchip,reset-switch-core" is a device configuration property > which tells the system (driver) how the hw should be handled. Since you > do not *always* want to reset the switch core (f.ex. when implementing > systems with warm reboot), I think it makes perfect sense - but I may be > biased off course :-) >=20 > Thank you for (all) of your comments, by the way! >=20 > ---Lars > > Rob Is this series still needed? Did I miss a follow-up? -- Sebastian --2uz6qofapxdsjq5b Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAl9JMyoACgkQ2O7X88g7 +prxIw//WChtGuQRJbAJnDDduyEOCPfGFu6Tb/IMAiHmUCXPzuhKqXIkpewoCBr/ nsNGJ1SlzbbpyK8ZRYjTbIZEFefiXwa9ue3paC05lng8HgV7DzWT5zLTs7dbL6Mn b3QPzkXkqGkAue6CVxNJT0FJ2g9w3PGXWlYn2kkqZ81Kv2z3rEPt+jYLsSRjUp40 SZ5hNR8PKKwN8dBHCRrD6n8YSh9u46g68BlQoa6A1RSYbIcJA2qxqCN/WZWnH3KR 1vqyoXjUrdZt20TC5eUnVdpveuT/KLoHPnczEZK/ipBpLvKhJiyXxXk2+x32BFQc Lczlv3AcvSF54ChMY4HE3TyaTwr3ripcMcjv/ThWrfs+YKmiMtbSNUyCpHOC5ILS t/r8r0UP0gFUld8z/vEyUCyb7hAoKlAkBRXPtVaO/iZ0LehkrKGNL0GTbNA+X+qs Cydvok5QBb+YM4Y3rI8Gevc2/4WSyKtsvYGp4L3+T0GV0RCuwrUSZuRVVCAm/zn5 PeHyZanE/m658l0kf6M8TDoqxGQh24uSr8b2/cjoqpjk5uw5Qp+A+rzesgOKRQ/7 ZmMzgi9JLr0gxNwfTYedvOw732ZTMG7ei0jzITHpkfFBAPCWwWs0WzuwCGSXpuHh VFgG8gFaqqpKtF89gm8HnACIIooLcPZdJ6eFNqozYAXOmbhMKi4= =8N5+ -----END PGP SIGNATURE----- --2uz6qofapxdsjq5b-- --===============3135593473041272497== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============3135593473041272497==--