From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B06C3C433E6 for ; Fri, 28 Aug 2020 22:28:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 926322086A for ; Fri, 28 Aug 2020 22:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726839AbgH1W2w (ORCPT ); Fri, 28 Aug 2020 18:28:52 -0400 Received: from vps0.lunn.ch ([185.16.172.187]:59130 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726524AbgH1W2v (ORCPT ); Fri, 28 Aug 2020 18:28:51 -0400 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1kBmrW-00CLCh-J4; Sat, 29 Aug 2020 00:28:46 +0200 Date: Sat, 29 Aug 2020 00:28:46 +0200 From: Andrew Lunn To: Adam =?utf-8?Q?Rudzi=C5=84ski?= Cc: robh+dt@kernel.org, frowand.list@gmail.com, f.fainelli@gmail.com, netdev Subject: Re: drivers/of/of_mdio.c needs a small modification Message-ID: <20200828222846.GA2403519@lunn.ch> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi Adam > If kernel has to bring up two Ethernet interfaces, the processor has two > peripherals with functionality of MACs (in i.MX6ULL these are Fast Ethernet > Controllers, FECs), but uses a shared MDIO bus, then the kernel first probes > one MAC, enables clock for its PHY, probes MDIO bus tryng to discover _all_ > PHYs, and then probes the second MAC, and enables clock for its PHY. The > result is that the second PHY is still inactive during PHY discovery. Thus, > one Ethernet interface is not functional. What clock are you talking about? Do you have the FEC feeding a 50MHz clock to the PHY? Each FEC providing its own clock to its own PHY? And are you saying a PHY without its reference clock does not respond to MDIO reads and hence the second PHY does not probe because it has no reference clock? Andrew