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Mon, 31 Aug 2020 22:00:31 -0700 (PDT) Date: Tue, 1 Sep 2020 00:00:28 -0500 From: Bjorn Andersson To: Rob Clark Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, linux-arm-msm@vger.kernel.org, Sai Prakash Ranjan , Will Deacon , freedreno@lists.freedesktop.org, Sibi Sankar , Vivek Gautam , Stephen Boyd , Robin Murphy , Joerg Roedel , linux-arm-kernel@lists.infradead.org, Jordan Crouse , Rob Clark , Hanna Hawa , Jon Hunter , Krishna Reddy , open list Subject: Re: [PATCH 09/19] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Message-ID: <20200901050028.GQ3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-10-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200814024114.1177553-10-robdclark@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse > > Add a special implementation for the SMMU attached to most Adreno GPU > target triggered from the qcom,adreno-smmu compatible string. > > The new Adreno SMMU implementation will enable split pagetables > (TTBR1) for the domain attached to the GPU device (SID 0) and > hard code it context bank 0 so the GPU hardware can implement > per-instance pagetables. > Reviewed-by: Bjorn Andersson > Co-developed-by: Rob Clark > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 3 files changed, 151 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > index 88f17cc33023..d199b4bff15d 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > of_device_is_compatible(np, "qcom,sm8250-smmu-500")) > return qcom_smmu_impl_init(smmu); > > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) > + return qcom_adreno_smmu_impl_init(smmu); > + > if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) > smmu->impl = &mrvl_mmu500_impl; > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index be4318044f96..5640d9960610 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2019, The Linux Foundation. All rights reserved. > */ > > +#include > #include > #include > > @@ -12,6 +13,132 @@ struct qcom_smmu { > struct arm_smmu_device smmu; > }; > > +#define QCOM_ADRENO_SMMU_GPU_SID 0 > + > +static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > +{ > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > + int i; > + > + /* > + * The GPU will always use SID 0 so that is a handy way to uniquely > + * identify it and configure it for per-instance pagetables > + */ > + for (i = 0; i < fwspec->num_ids; i++) { > + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); > + > + if (sid == QCOM_ADRENO_SMMU_GPU_SID) > + return true; > + } > + > + return false; > +} > + > +static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( > + const void *cookie) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = > + io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + return &pgtable->cfg; > +} > + > +/* > + * Local implementation to configure TTBR0 with the specified pagetable config. > + * The GPU driver will call this to enable TTBR0 when per-instance pagetables > + * are active > + */ > + > +static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, > + const struct io_pgtable_cfg *pgtbl_cfg) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; > + > + /* The domain must have split pagetables already enabled */ > + if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) > + return -EINVAL; > + > + /* If the pagetable config is NULL, disable TTBR0 */ > + if (!pgtbl_cfg) { > + /* Do nothing if it is already disabled */ > + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + /* Set TCR to the original configuration */ > + cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } else { > + u32 tcr = cb->tcr[0]; > + > + /* Don't call this again if TTBR0 is already enabled */ > + if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); > + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); > + > + cb->tcr[0] = tcr; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } > + > + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); > + > + return 0; > +} > + > +static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, > + struct device *dev, int start, int count) > +{ > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + /* > + * Assign context bank 0 to the GPU device so the GPU hardware can > + * switch pagetables > + */ > + if (qcom_adreno_smmu_is_gpu_device(dev)) { > + start = 0; > + count = 1; > + } else { > + start = 1; > + } > + > + return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > +} > + > +static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > +{ > + struct adreno_smmu_priv *priv; > + > + /* Only enable split pagetables for the GPU device (SID 0) */ > + if (!qcom_adreno_smmu_is_gpu_device(dev)) > + return 0; > + > + /* > + * All targets that use the qcom,adreno-smmu compatible string *should* > + * be AARCH64 stage 1 but double check because the arm-smmu code assumes > + * that is the case when the TTBR1 quirk is enabled > + */ > + if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > + pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > + > + /* > + * Initialize private interface with GPU: > + */ > + > + priv = dev_get_drvdata(dev); > + priv->cookie = smmu_domain; > + priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > + priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + > + return 0; > +} > + > static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { > { .compatible = "qcom,adreno" }, > { .compatible = "qcom,mdp4" }, > @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { > .reset = qcom_smmu500_reset, > }; > > -struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +static const struct arm_smmu_impl qcom_adreno_smmu_impl = { > + .init_context = qcom_adreno_smmu_init_context, > + .def_domain_type = qcom_smmu_def_domain_type, > + .reset = qcom_smmu500_reset, > + .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, > +}; > + > +static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, > + const struct arm_smmu_impl *impl) > { > struct qcom_smmu *qsmmu; > > @@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > > qsmmu->smmu = *smmu; > > - qsmmu->smmu.impl = &qcom_smmu_impl; > + qsmmu->smmu.impl = impl; > devm_kfree(smmu->dev, smmu); > > return &qsmmu->smmu; > } > + > +struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > +} > + > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > +} > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 27c83333fc50..cd75a33967bb 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu); > > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); > int arm_mmu500_reset(struct arm_smmu_device *smmu); > -- > 2.26.2 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B96A0C433E6 for ; Tue, 1 Sep 2020 05:14:09 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 78F972087D for ; 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Mon, 31 Aug 2020 22:00:32 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id k21sm3206otp.40.2020.08.31.22.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:00:31 -0700 (PDT) Date: Tue, 1 Sep 2020 00:00:28 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 09/19] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Message-ID: <20200901050028.GQ3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-10-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-10-robdclark@gmail.com> Cc: Rob Clark , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , Jon Hunter , freedreno@lists.freedesktop.org, Hanna Hawa , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse > > Add a special implementation for the SMMU attached to most Adreno GPU > target triggered from the qcom,adreno-smmu compatible string. > > The new Adreno SMMU implementation will enable split pagetables > (TTBR1) for the domain attached to the GPU device (SID 0) and > hard code it context bank 0 so the GPU hardware can implement > per-instance pagetables. > Reviewed-by: Bjorn Andersson > Co-developed-by: Rob Clark > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 3 files changed, 151 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > index 88f17cc33023..d199b4bff15d 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > of_device_is_compatible(np, "qcom,sm8250-smmu-500")) > return qcom_smmu_impl_init(smmu); > > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) > + return qcom_adreno_smmu_impl_init(smmu); > + > if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) > smmu->impl = &mrvl_mmu500_impl; > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index be4318044f96..5640d9960610 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2019, The Linux Foundation. All rights reserved. > */ > > +#include > #include > #include > > @@ -12,6 +13,132 @@ struct qcom_smmu { > struct arm_smmu_device smmu; > }; > > +#define QCOM_ADRENO_SMMU_GPU_SID 0 > + > +static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > +{ > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > + int i; > + > + /* > + * The GPU will always use SID 0 so that is a handy way to uniquely > + * identify it and configure it for per-instance pagetables > + */ > + for (i = 0; i < fwspec->num_ids; i++) { > + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); > + > + if (sid == QCOM_ADRENO_SMMU_GPU_SID) > + return true; > + } > + > + return false; > +} > + > +static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( > + const void *cookie) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = > + io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + return &pgtable->cfg; > +} > + > +/* > + * Local implementation to configure TTBR0 with the specified pagetable config. > + * The GPU driver will call this to enable TTBR0 when per-instance pagetables > + * are active > + */ > + > +static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, > + const struct io_pgtable_cfg *pgtbl_cfg) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; > + > + /* The domain must have split pagetables already enabled */ > + if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) > + return -EINVAL; > + > + /* If the pagetable config is NULL, disable TTBR0 */ > + if (!pgtbl_cfg) { > + /* Do nothing if it is already disabled */ > + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + /* Set TCR to the original configuration */ > + cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } else { > + u32 tcr = cb->tcr[0]; > + > + /* Don't call this again if TTBR0 is already enabled */ > + if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); > + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); > + > + cb->tcr[0] = tcr; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } > + > + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); > + > + return 0; > +} > + > +static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, > + struct device *dev, int start, int count) > +{ > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + /* > + * Assign context bank 0 to the GPU device so the GPU hardware can > + * switch pagetables > + */ > + if (qcom_adreno_smmu_is_gpu_device(dev)) { > + start = 0; > + count = 1; > + } else { > + start = 1; > + } > + > + return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > +} > + > +static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > +{ > + struct adreno_smmu_priv *priv; > + > + /* Only enable split pagetables for the GPU device (SID 0) */ > + if (!qcom_adreno_smmu_is_gpu_device(dev)) > + return 0; > + > + /* > + * All targets that use the qcom,adreno-smmu compatible string *should* > + * be AARCH64 stage 1 but double check because the arm-smmu code assumes > + * that is the case when the TTBR1 quirk is enabled > + */ > + if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > + pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > + > + /* > + * Initialize private interface with GPU: > + */ > + > + priv = dev_get_drvdata(dev); > + priv->cookie = smmu_domain; > + priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > + priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + > + return 0; > +} > + > static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { > { .compatible = "qcom,adreno" }, > { .compatible = "qcom,mdp4" }, > @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { > .reset = qcom_smmu500_reset, > }; > > -struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +static const struct arm_smmu_impl qcom_adreno_smmu_impl = { > + .init_context = qcom_adreno_smmu_init_context, > + .def_domain_type = qcom_smmu_def_domain_type, > + .reset = qcom_smmu500_reset, > + .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, > +}; > + > +static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, > + const struct arm_smmu_impl *impl) > { > struct qcom_smmu *qsmmu; > > @@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > > qsmmu->smmu = *smmu; > > - qsmmu->smmu.impl = &qcom_smmu_impl; > + qsmmu->smmu.impl = impl; > devm_kfree(smmu->dev, smmu); > > return &qsmmu->smmu; > } > + > +struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > +} > + > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > +} > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 27c83333fc50..cd75a33967bb 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu); > > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); > int arm_mmu500_reset(struct arm_smmu_device *smmu); > -- > 2.26.2 > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FBBCC433E6 for ; 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Mon, 31 Aug 2020 22:00:32 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id k21sm3206otp.40.2020.08.31.22.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:00:31 -0700 (PDT) Date: Tue, 1 Sep 2020 00:00:28 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 09/19] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Message-ID: <20200901050028.GQ3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-10-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-10-robdclark@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200901_010034_221813_D332B61E X-CRM114-Status: GOOD ( 33.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , Jordan Crouse , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Sibi Sankar , Vivek Gautam , Jon Hunter , freedreno@lists.freedesktop.org, Hanna Hawa , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse > > Add a special implementation for the SMMU attached to most Adreno GPU > target triggered from the qcom,adreno-smmu compatible string. > > The new Adreno SMMU implementation will enable split pagetables > (TTBR1) for the domain attached to the GPU device (SID 0) and > hard code it context bank 0 so the GPU hardware can implement > per-instance pagetables. > Reviewed-by: Bjorn Andersson > Co-developed-by: Rob Clark > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 3 files changed, 151 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > index 88f17cc33023..d199b4bff15d 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > of_device_is_compatible(np, "qcom,sm8250-smmu-500")) > return qcom_smmu_impl_init(smmu); > > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) > + return qcom_adreno_smmu_impl_init(smmu); > + > if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) > smmu->impl = &mrvl_mmu500_impl; > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index be4318044f96..5640d9960610 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2019, The Linux Foundation. All rights reserved. > */ > > +#include > #include > #include > > @@ -12,6 +13,132 @@ struct qcom_smmu { > struct arm_smmu_device smmu; > }; > > +#define QCOM_ADRENO_SMMU_GPU_SID 0 > + > +static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > +{ > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > + int i; > + > + /* > + * The GPU will always use SID 0 so that is a handy way to uniquely > + * identify it and configure it for per-instance pagetables > + */ > + for (i = 0; i < fwspec->num_ids; i++) { > + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); > + > + if (sid == QCOM_ADRENO_SMMU_GPU_SID) > + return true; > + } > + > + return false; > +} > + > +static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( > + const void *cookie) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = > + io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + return &pgtable->cfg; > +} > + > +/* > + * Local implementation to configure TTBR0 with the specified pagetable config. > + * The GPU driver will call this to enable TTBR0 when per-instance pagetables > + * are active > + */ > + > +static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, > + const struct io_pgtable_cfg *pgtbl_cfg) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; > + > + /* The domain must have split pagetables already enabled */ > + if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) > + return -EINVAL; > + > + /* If the pagetable config is NULL, disable TTBR0 */ > + if (!pgtbl_cfg) { > + /* Do nothing if it is already disabled */ > + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + /* Set TCR to the original configuration */ > + cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } else { > + u32 tcr = cb->tcr[0]; > + > + /* Don't call this again if TTBR0 is already enabled */ > + if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); > + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); > + > + cb->tcr[0] = tcr; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } > + > + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); > + > + return 0; > +} > + > +static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, > + struct device *dev, int start, int count) > +{ > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + /* > + * Assign context bank 0 to the GPU device so the GPU hardware can > + * switch pagetables > + */ > + if (qcom_adreno_smmu_is_gpu_device(dev)) { > + start = 0; > + count = 1; > + } else { > + start = 1; > + } > + > + return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > +} > + > +static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > +{ > + struct adreno_smmu_priv *priv; > + > + /* Only enable split pagetables for the GPU device (SID 0) */ > + if (!qcom_adreno_smmu_is_gpu_device(dev)) > + return 0; > + > + /* > + * All targets that use the qcom,adreno-smmu compatible string *should* > + * be AARCH64 stage 1 but double check because the arm-smmu code assumes > + * that is the case when the TTBR1 quirk is enabled > + */ > + if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > + pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > + > + /* > + * Initialize private interface with GPU: > + */ > + > + priv = dev_get_drvdata(dev); > + priv->cookie = smmu_domain; > + priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > + priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + > + return 0; > +} > + > static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { > { .compatible = "qcom,adreno" }, > { .compatible = "qcom,mdp4" }, > @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { > .reset = qcom_smmu500_reset, > }; > > -struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +static const struct arm_smmu_impl qcom_adreno_smmu_impl = { > + .init_context = qcom_adreno_smmu_init_context, > + .def_domain_type = qcom_smmu_def_domain_type, > + .reset = qcom_smmu500_reset, > + .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, > +}; > + > +static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, > + const struct arm_smmu_impl *impl) > { > struct qcom_smmu *qsmmu; > > @@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > > qsmmu->smmu = *smmu; > > - qsmmu->smmu.impl = &qcom_smmu_impl; > + qsmmu->smmu.impl = impl; > devm_kfree(smmu->dev, smmu); > > return &qsmmu->smmu; > } > + > +struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > +} > + > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > +} > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 27c83333fc50..cd75a33967bb 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu); > > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); > int arm_mmu500_reset(struct arm_smmu_device *smmu); > -- > 2.26.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B123BC433E2 for ; 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Mon, 31 Aug 2020 22:00:32 -0700 (PDT) Received: from yoga ([2605:6000:e5cb:c100:8898:14ff:fe6d:34e]) by smtp.gmail.com with ESMTPSA id k21sm3206otp.40.2020.08.31.22.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Aug 2020 22:00:31 -0700 (PDT) Date: Tue, 1 Sep 2020 00:00:28 -0500 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH 09/19] iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU Message-ID: <20200901050028.GQ3715@yoga> References: <20200810222657.1841322-1-jcrouse@codeaurora.org> <20200814024114.1177553-10-robdclark@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200814024114.1177553-10-robdclark@gmail.com> X-Mailman-Approved-At: Tue, 01 Sep 2020 07:31:54 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Sai Prakash Ranjan , open list , Will Deacon , linux-arm-msm@vger.kernel.org, Joerg Roedel , Robin Murphy , dri-devel@lists.freedesktop.org, Stephen Boyd , iommu@lists.linux-foundation.org, Krishna Reddy , Sibi Sankar , Vivek Gautam , Jon Hunter , freedreno@lists.freedesktop.org, Hanna Hawa , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu 13 Aug 21:41 CDT 2020, Rob Clark wrote: > From: Jordan Crouse > > Add a special implementation for the SMMU attached to most Adreno GPU > target triggered from the qcom,adreno-smmu compatible string. > > The new Adreno SMMU implementation will enable split pagetables > (TTBR1) for the domain attached to the GPU device (SID 0) and > hard code it context bank 0 so the GPU hardware can implement > per-instance pagetables. > Reviewed-by: Bjorn Andersson > Co-developed-by: Rob Clark > Signed-off-by: Jordan Crouse > Signed-off-by: Rob Clark > --- > drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 + > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 149 ++++++++++++++++++++- > drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + > 3 files changed, 151 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > index 88f17cc33023..d199b4bff15d 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c > @@ -223,6 +223,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu) > of_device_is_compatible(np, "qcom,sm8250-smmu-500")) > return qcom_smmu_impl_init(smmu); > > + if (of_device_is_compatible(smmu->dev->of_node, "qcom,adreno-smmu")) > + return qcom_adreno_smmu_impl_init(smmu); > + > if (of_device_is_compatible(np, "marvell,ap806-smmu-500")) > smmu->impl = &mrvl_mmu500_impl; > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index be4318044f96..5640d9960610 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -3,6 +3,7 @@ > * Copyright (c) 2019, The Linux Foundation. All rights reserved. > */ > > +#include > #include > #include > > @@ -12,6 +13,132 @@ struct qcom_smmu { > struct arm_smmu_device smmu; > }; > > +#define QCOM_ADRENO_SMMU_GPU_SID 0 > + > +static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) > +{ > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > + int i; > + > + /* > + * The GPU will always use SID 0 so that is a handy way to uniquely > + * identify it and configure it for per-instance pagetables > + */ > + for (i = 0; i < fwspec->num_ids; i++) { > + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); > + > + if (sid == QCOM_ADRENO_SMMU_GPU_SID) > + return true; > + } > + > + return false; > +} > + > +static const struct io_pgtable_cfg *qcom_adreno_smmu_get_ttbr1_cfg( > + const void *cookie) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = > + io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + return &pgtable->cfg; > +} > + > +/* > + * Local implementation to configure TTBR0 with the specified pagetable config. > + * The GPU driver will call this to enable TTBR0 when per-instance pagetables > + * are active > + */ > + > +static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, > + const struct io_pgtable_cfg *pgtbl_cfg) > +{ > + struct arm_smmu_domain *smmu_domain = (void *)cookie; > + struct io_pgtable *pgtable = io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops); > + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; > + struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; > + > + /* The domain must have split pagetables already enabled */ > + if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) > + return -EINVAL; > + > + /* If the pagetable config is NULL, disable TTBR0 */ > + if (!pgtbl_cfg) { > + /* Do nothing if it is already disabled */ > + if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + /* Set TCR to the original configuration */ > + cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); > + cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } else { > + u32 tcr = cb->tcr[0]; > + > + /* Don't call this again if TTBR0 is already enabled */ > + if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) > + return -EINVAL; > + > + tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); > + tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); > + > + cb->tcr[0] = tcr; > + cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; > + cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); > + } > + > + arm_smmu_write_context_bank(smmu_domain->smmu, cb->cfg->cbndx); > + > + return 0; > +} > + > +static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, > + struct device *dev, int start, int count) > +{ > + struct arm_smmu_device *smmu = smmu_domain->smmu; > + > + /* > + * Assign context bank 0 to the GPU device so the GPU hardware can > + * switch pagetables > + */ > + if (qcom_adreno_smmu_is_gpu_device(dev)) { > + start = 0; > + count = 1; > + } else { > + start = 1; > + } > + > + return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > +} > + > +static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > + struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > +{ > + struct adreno_smmu_priv *priv; > + > + /* Only enable split pagetables for the GPU device (SID 0) */ > + if (!qcom_adreno_smmu_is_gpu_device(dev)) > + return 0; > + > + /* > + * All targets that use the qcom,adreno-smmu compatible string *should* > + * be AARCH64 stage 1 but double check because the arm-smmu code assumes > + * that is the case when the TTBR1 quirk is enabled > + */ > + if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > + pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > + > + /* > + * Initialize private interface with GPU: > + */ > + > + priv = dev_get_drvdata(dev); > + priv->cookie = smmu_domain; > + priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; > + priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; > + > + return 0; > +} > + > static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { > { .compatible = "qcom,adreno" }, > { .compatible = "qcom,mdp4" }, > @@ -65,7 +192,15 @@ static const struct arm_smmu_impl qcom_smmu_impl = { > .reset = qcom_smmu500_reset, > }; > > -struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +static const struct arm_smmu_impl qcom_adreno_smmu_impl = { > + .init_context = qcom_adreno_smmu_init_context, > + .def_domain_type = qcom_smmu_def_domain_type, > + .reset = qcom_smmu500_reset, > + .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, > +}; > + > +static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, > + const struct arm_smmu_impl *impl) > { > struct qcom_smmu *qsmmu; > > @@ -75,8 +210,18 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > > qsmmu->smmu = *smmu; > > - qsmmu->smmu.impl = &qcom_smmu_impl; > + qsmmu->smmu.impl = impl; > devm_kfree(smmu->dev, smmu); > > return &qsmmu->smmu; > } > + > +struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_smmu_impl); > +} > + > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu) > +{ > + return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl); > +} > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h > index 27c83333fc50..cd75a33967bb 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h > @@ -519,6 +519,7 @@ static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page, > struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); > struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); > +struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu); > > void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); > int arm_mmu500_reset(struct arm_smmu_device *smmu); > -- > 2.26.2 > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel