From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF187C433E2 for ; Wed, 2 Sep 2020 10:04:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C482C214F1 for ; Wed, 2 Sep 2020 10:04:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726493AbgIBKEf (ORCPT ); Wed, 2 Sep 2020 06:04:35 -0400 Received: from foss.arm.com ([217.140.110.172]:34764 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726140AbgIBKEd (ORCPT ); Wed, 2 Sep 2020 06:04:33 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3FECD6E; Wed, 2 Sep 2020 03:04:31 -0700 (PDT) Received: from bogus (unknown [10.57.4.218]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 22F113F66F; Wed, 2 Sep 2020 03:04:30 -0700 (PDT) Date: Wed, 2 Sep 2020 11:04:22 +0100 From: Sudeep Holla To: Valentin Schneider Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Robin Murphy , Jeremy Linton , Dietmar Eggemann , Sudeep Holla , Morten Rasmussen , "Zengtao (B)" Subject: Re: [PATCH] arm64: topology: Stop using MPIDR for topology information Message-ID: <20200902100422.GA25462@bogus> References: <20200829130016.26106-1-valentin.schneider@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200829130016.26106-1-valentin.schneider@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Aug 29, 2020 at 02:00:16PM +0100, Valentin Schneider wrote: > In the absence of ACPI or DT topology data, we fallback to haphazardly > decoding *something* out of MPIDR. Sadly, the contents of that register are > mostly unusable due to the implementation leniancy and things like Aff0 > having to be capped to 15 (despite being encoded on 8 bits). > > Consider a simple system with a single package of 32 cores, all under the > same LLC. We ought to be shoving them in the same core_sibling mask, but > MPIDR is going to look like: > > | CPU | 0 | ... | 15 | 16 | ... | 31 | > |------+---+-----+----+----+-----+----+ > | Aff0 | 0 | ... | 15 | 0 | ... | 15 | > | Aff1 | 0 | ... | 0 | 1 | ... | 1 | > | Aff2 | 0 | ... | 0 | 0 | ... | 0 | > > Which will eventually yield > > core_sibling(0-15) == 0-15 > core_sibling(16-31) == 16-31 > > NUMA woes > ========= > > If we try to play games with this and set up NUMA boundaries within those > groups of 16 cores via e.g. QEMU: > > # Node0: 0-9; Node1: 10-19 > $ qemu-system-aarch64 \ > -smp 20 -numa node,cpus=0-9,nodeid=0 -numa node,cpus=10-19,nodeid=1 > > The scheduler's MC domain (all CPUs with same LLC) is going to be built via > > arch_topology.c::cpu_coregroup_mask() > > In there we try to figure out a sensible mask out of the topology > information we have. In short, here we'll pick the smallest of NUMA or > core sibling mask. > > node_mask(CPU9) == 0-9 > core_sibling(CPU9) == 0-15 > > MC mask for CPU9 will thus be 0-9, not a problem. > > node_mask(CPU10) == 10-19 > core_sibling(CPU10) == 0-15 > > MC mask for CPU10 will thus be 10-19, not a problem. > > node_mask(CPU16) == 10-19 > core_sibling(CPU16) == 16-19 > > MC mask for CPU16 will thus be 16-19... Uh oh. CPUs 16-19 are in two > different unique MC spans, and the scheduler has no idea what to make of > that. That triggers the WARN_ON() added by commit > > ccf74128d66c ("sched/topology: Assert non-NUMA topology masks don't (partially) overlap") > > Fixing MPIDR-derived topology > ============================= > > We could try to come up with some cleverer scheme to figure out which of > the available masks to pick, but really if one of those masks resulted from > MPIDR then it should be discarded because it's bound to be bogus. > > I was hoping to give MPIDR a chance for SMT, to figure out which threads are > in the same core using Aff1-3 as core ID, but Sudeep and Robin pointed out > to me that there are systems out there where *all* cores have non-zero > values in their higher affinity fields (e.g. RK3288 has "5" in all of its > cores' MPIDR.Aff1), which would expose a bogus core ID to userspace. > > Stop using MPIDR for topology information. When no other source of topology > information is available, mark each CPU as its own core and its NUMA node > as its LLC domain. > Looks good to me, so: Reviewed-by: Sudeep Holla However, we need to get it tested on some systems with *weird* MPIDR values and don't have topology described in DT cpu-maps and somehow (wrongly) relied on below logic. Also though these affect user ABI via sysfs topology, I expect systems w/o DT cpu-maps and weird MPIDR are broken either way. Luckily found only one such mpidr in arm64 DTS files: arch/arm64/boot/dts/sprd/sc9860.dtsi -- Regards, Sudeep From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B250C433E2 for ; Wed, 2 Sep 2020 10:06:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2BB9E20658 for ; Wed, 2 Sep 2020 10:06:07 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="i4BtF9e4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2BB9E20658 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=95JjqVc6fhfb8q/hS/NGnF25Cqds6yfT1bac1ApA/A4=; b=i4BtF9e4av5SQaRanez/OBlp/ 53yZSkbtZqGo4IIk58S+n7AsSokD0pRrAdYRm9fJvp5kRAIVD9vh3F+l7etp3UReyYw1ktKVKpwYc nK0MEScqClgPDU/+f0cHg742QvviWdb4GYWGGPmHV1Twy3Yd5ldRcp+3wFa5ms178P6VSU1VaMrmc LffqYPHwfogzRWWv5EkdS0u0G3SwSTnz/VtwdnuqK2z63LNlwrNCI1lHg7Yeh6OkO7cSEqBw9+CV8 8QhWGytXp7wg1xcJxgPFI0o/PulVyknk70Jw6RNEEZCiNKtLyQcfnmzkFDHKP4Hx59HNQcqsh3VBM /4PPBgCJw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kDPd8-0003eM-G9; Wed, 02 Sep 2020 10:04:38 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kDPd5-0003dq-T4 for linux-arm-kernel@lists.infradead.org; Wed, 02 Sep 2020 10:04:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B3FECD6E; Wed, 2 Sep 2020 03:04:31 -0700 (PDT) Received: from bogus (unknown [10.57.4.218]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 22F113F66F; Wed, 2 Sep 2020 03:04:30 -0700 (PDT) Date: Wed, 2 Sep 2020 11:04:22 +0100 From: Sudeep Holla To: Valentin Schneider Subject: Re: [PATCH] arm64: topology: Stop using MPIDR for topology information Message-ID: <20200902100422.GA25462@bogus> References: <20200829130016.26106-1-valentin.schneider@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200829130016.26106-1-valentin.schneider@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200902_060436_039685_319ADAB5 X-CRM114-Status: GOOD ( 25.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , linux-kernel@vger.kernel.org, Jeremy Linton , Morten Rasmussen , "Zengtao $B$" , Sudeep Holla , Will Deacon , Dietmar Eggemann , linux-arm-kernel@lists.infradead.org, Robin Murphy Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Aug 29, 2020 at 02:00:16PM +0100, Valentin Schneider wrote: > In the absence of ACPI or DT topology data, we fallback to haphazardly > decoding *something* out of MPIDR. Sadly, the contents of that register are > mostly unusable due to the implementation leniancy and things like Aff0 > having to be capped to 15 (despite being encoded on 8 bits). > > Consider a simple system with a single package of 32 cores, all under the > same LLC. We ought to be shoving them in the same core_sibling mask, but > MPIDR is going to look like: > > | CPU | 0 | ... | 15 | 16 | ... | 31 | > |------+---+-----+----+----+-----+----+ > | Aff0 | 0 | ... | 15 | 0 | ... | 15 | > | Aff1 | 0 | ... | 0 | 1 | ... | 1 | > | Aff2 | 0 | ... | 0 | 0 | ... | 0 | > > Which will eventually yield > > core_sibling(0-15) == 0-15 > core_sibling(16-31) == 16-31 > > NUMA woes > ========= > > If we try to play games with this and set up NUMA boundaries within those > groups of 16 cores via e.g. QEMU: > > # Node0: 0-9; Node1: 10-19 > $ qemu-system-aarch64 \ > -smp 20 -numa node,cpus=0-9,nodeid=0 -numa node,cpus=10-19,nodeid=1 > > The scheduler's MC domain (all CPUs with same LLC) is going to be built via > > arch_topology.c::cpu_coregroup_mask() > > In there we try to figure out a sensible mask out of the topology > information we have. In short, here we'll pick the smallest of NUMA or > core sibling mask. > > node_mask(CPU9) == 0-9 > core_sibling(CPU9) == 0-15 > > MC mask for CPU9 will thus be 0-9, not a problem. > > node_mask(CPU10) == 10-19 > core_sibling(CPU10) == 0-15 > > MC mask for CPU10 will thus be 10-19, not a problem. > > node_mask(CPU16) == 10-19 > core_sibling(CPU16) == 16-19 > > MC mask for CPU16 will thus be 16-19... Uh oh. CPUs 16-19 are in two > different unique MC spans, and the scheduler has no idea what to make of > that. That triggers the WARN_ON() added by commit > > ccf74128d66c ("sched/topology: Assert non-NUMA topology masks don't (partially) overlap") > > Fixing MPIDR-derived topology > ============================= > > We could try to come up with some cleverer scheme to figure out which of > the available masks to pick, but really if one of those masks resulted from > MPIDR then it should be discarded because it's bound to be bogus. > > I was hoping to give MPIDR a chance for SMT, to figure out which threads are > in the same core using Aff1-3 as core ID, but Sudeep and Robin pointed out > to me that there are systems out there where *all* cores have non-zero > values in their higher affinity fields (e.g. RK3288 has "5" in all of its > cores' MPIDR.Aff1), which would expose a bogus core ID to userspace. > > Stop using MPIDR for topology information. When no other source of topology > information is available, mark each CPU as its own core and its NUMA node > as its LLC domain. > Looks good to me, so: Reviewed-by: Sudeep Holla However, we need to get it tested on some systems with *weird* MPIDR values and don't have topology described in DT cpu-maps and somehow (wrongly) relied on below logic. Also though these affect user ABI via sysfs topology, I expect systems w/o DT cpu-maps and weird MPIDR are broken either way. Luckily found only one such mpidr in arm64 DTS files: arch/arm64/boot/dts/sprd/sc9860.dtsi -- Regards, Sudeep _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel