From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org, qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 19/30] hw/riscv: Move sifive_e_prci model to hw/misc
Date: Thu, 10 Sep 2020 11:09:27 -0700 [thread overview]
Message-ID: <20200910180938.584205-20-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200910180938.584205-1-alistair.francis@wdc.com>
From: Bin Meng <bin.meng@windriver.com>
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/{riscv => misc}/sifive_e_prci.h | 0
hw/{riscv => misc}/sifive_e_prci.c | 2 +-
hw/riscv/sifive_e.c | 2 +-
hw/misc/Kconfig | 3 +++
hw/misc/meson.build | 3 +++
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 -
7 files changed, 9 insertions(+), 3 deletions(-)
rename include/hw/{riscv => misc}/sifive_e_prci.h (100%)
rename hw/{riscv => misc}/sifive_e_prci.c (99%)
diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h
similarity index 100%
rename from include/hw/riscv/sifive_e_prci.h
rename to include/hw/misc/sifive_e_prci.h
diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c
similarity index 99%
rename from hw/riscv/sifive_e_prci.c
rename to hw/misc/sifive_e_prci.c
index 17dfa74715..8ec4ee4b41 100644
--- a/hw/riscv/sifive_e_prci.c
+++ b/hw/misc/sifive_e_prci.c
@@ -24,7 +24,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/hw.h"
-#include "hw/riscv/sifive_e_prci.h"
+#include "hw/misc/sifive_e_prci.h"
static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size)
{
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 36ccfb2071..7f43ed953a 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -43,8 +43,8 @@
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
#include "hw/riscv/sifive_e.h"
-#include "hw/riscv/sifive_e_prci.h"
#include "hw/riscv/boot.h"
+#include "hw/misc/sifive_e_prci.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/sysemu.h"
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 92c397ca07..507398635b 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,4 +134,7 @@ config MAC_VIA
config AVR_POWER
bool
+config SIFIVE_E_PRCI
+ bool
+
source macio/Kconfig
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index e1576b81cf..b6b2e5797f 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
# Mac devices
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
+# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
+
# PKUnity SoC devices
softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c'))
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index e53ab1efa5..5855e99aaa 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -15,6 +15,7 @@ config SIFIVE_E
bool
select HART
select SIFIVE
+ select SIFIVE_E_PRCI
select UNIMP
config SIFIVE_U
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index c29a48c3f1..003994d1ea 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
-riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c'))
--
2.28.0
next prev parent reply other threads:[~2020-09-10 18:32 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 18:09 [PULL 00/30] riscv-to-apply queue Alistair Francis
2020-09-10 18:09 ` [PULL 01/30] target/riscv: Fix bug in getting trap cause name for trace_riscv_trap Alistair Francis
2020-09-10 18:09 ` [PULL 02/30] riscv: sifive_test: Allow 16-bit writes to memory region Alistair Francis
2020-09-10 18:09 ` [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property Alistair Francis
2020-09-10 18:09 ` [PULL 04/30] hw/riscv: hart: " Alistair Francis
2020-09-10 18:09 ` [PULL 05/30] target/riscv: cpu: Set reset vector based on the configured property value Alistair Francis
2020-09-10 18:09 ` [PULL 06/30] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Alistair Francis
2020-09-10 18:09 ` [PULL 07/30] hw/char: Add Microchip PolarFire SoC MMUART emulation Alistair Francis
2021-09-18 16:55 ` Philippe Mathieu-Daudé
2021-09-19 23:03 ` Alistair Francis
2020-09-10 18:09 ` [PULL 08/30] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Alistair Francis
2020-09-10 18:09 ` [PULL 09/30] hw/sd: Add Cadence SDHCI emulation Alistair Francis
2020-09-10 18:09 ` [PULL 10/30] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Alistair Francis
2020-09-10 18:09 ` [PULL 11/30] hw/dma: Add SiFive platform DMA controller emulation Alistair Francis
2020-09-10 18:09 ` [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller Alistair Francis
2020-09-10 18:09 ` [PULL 13/30] hw/net: cadence_gem: Add a new 'phy-addr' property Alistair Francis
2020-09-10 18:09 ` [PULL 14/30] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Alistair Francis
2020-09-10 18:09 ` [PULL 15/30] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Alistair Francis
2020-09-10 18:09 ` [PULL 16/30] hw/riscv: microchip_pfsoc: Hook GPIO controllers Alistair Francis
2020-09-10 18:09 ` [PULL 17/30] hw/riscv: clint: Avoid using hard-coded timebase frequency Alistair Francis
2020-09-10 18:09 ` [PULL 18/30] hw/riscv: sifive_u: Connect a DMA controller Alistair Francis
2020-09-10 18:09 ` Alistair Francis [this message]
2020-09-10 18:09 ` [PULL 20/30] hw/riscv: Move sifive_u_prci model to hw/misc Alistair Francis
2020-09-10 18:09 ` [PULL 21/30] hw/riscv: Move sifive_u_otp " Alistair Francis
2020-09-10 18:09 ` [PULL 22/30] hw/riscv: Move sifive_gpio model to hw/gpio Alistair Francis
2020-09-10 18:09 ` [PULL 23/30] hw/riscv: Move sifive_clint model to hw/intc Alistair Francis
2020-09-10 18:09 ` [PULL 24/30] hw/riscv: Move sifive_plic " Alistair Francis
2020-09-10 18:09 ` [PULL 25/30] hw/riscv: Move riscv_htif model to hw/char Alistair Francis
2020-09-10 18:09 ` [PULL 26/30] hw/riscv: Move sifive_uart " Alistair Francis
2020-09-10 18:09 ` [PULL 27/30] hw/riscv: Move sifive_test model to hw/misc Alistair Francis
2020-09-10 18:09 ` [PULL 28/30] hw/riscv: Always build riscv_hart.c Alistair Francis
2020-09-10 18:09 ` [PULL 29/30] hw/riscv: Drop CONFIG_SIFIVE Alistair Francis
2020-09-10 18:09 ` [PULL 30/30] hw/riscv: Sort the Kconfig options in alphabetical order Alistair Francis
2020-09-13 21:30 ` [PULL 00/30] riscv-to-apply queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200910180938.584205-20-alistair.francis@wdc.com \
--to=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bin.meng@windriver.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.