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10 Sep 2020 11:07:31 -0700 IronPort-SDR: ntCa7pAP2g4djQoRp9hjBPsozkKnfCVy0iVterfz/nqTx384Y1LWyfB3ilD1tuqOvT+cwUD9ax 5ZuxuqYKsnrQ== WDCIronportException: Internal Received: from fwvkpc2.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.59.152]) by uls-op-cesaip01.wdc.com with ESMTP; 10 Sep 2020 11:20:15 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 03/30] target/riscv: cpu: Add a new 'resetvec' property Date: Thu, 10 Sep 2020 11:09:11 -0700 Message-Id: <20200910180938.584205-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200910180938.584205-1-alistair.francis@wdc.com> References: <20200910180938.584205-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=515d47f05=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/10 14:20:04 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3589ae6ea..0d1728a8cd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ typedef struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + uint64_t resetvec; } cfg; } RISCVCPU; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bcdce85c5e..f6aeecac15 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -529,6 +529,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; -- 2.28.0