From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48420C43461 for ; Fri, 11 Sep 2020 21:52:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 09ED722208 for ; Fri, 11 Sep 2020 21:52:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599861159; bh=Zw0NZ9Tb0m1B4iozwIcZtqtMiYimMg0M5UjK9JfytvY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ThBgB91YnEZnv/bM3CqsYi5HWfM3ont9jfT7OtiINIy0ln76AgtUGIM2RN5TsFVmn u64RS5wekGw7+ysqYKLRGzn3iYMs6faHRfbNrtnwnUEoHwAK4gpZZlhQnXB1u44ZD7 OANX3nG818dMz31B6ds72XMK4zomIcAQG/utKPOo= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725852AbgIKVwi (ORCPT ); Fri, 11 Sep 2020 17:52:38 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:35625 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725933AbgIKVvq (ORCPT ); Fri, 11 Sep 2020 17:51:46 -0400 Received: by mail-io1-f65.google.com with SMTP id r9so12666319ioa.2 for ; Fri, 11 Sep 2020 14:51:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SPPit0voQ5iZSd9YAtw226cZcfg7JS5J3IK/RTi0Ep0=; b=DVRG88UgpEIw/PGAuv7lzIQhnzSnDlE4iXzxFm94KR6pyMl7V6tP8N5e5YNDEclZSA zHA/eTasz/EMS4wqY7AGoi/MPQuzzJb/8hz9+cqCRYlpmuuW4ogDLkTarySbLsEItv7T EMPf/6eeU1jr0jOdi40NH4+nANq8wiXZM79WNN6PiIkygxWvJWl7FiLB7omAjGXnJEhF 4erlCU/kbTBOkaroVH9UWc4ERcR3mTLXAIcEzp6VHEO19QHYd/1NcgT07QTxlXy3A0i5 ndEqTstBNbroyaHzZohtG9A2We4nhQqYHF7h3hFWCD98RdqaNf5xznaz64TtGAg9zqac O3ew== X-Gm-Message-State: AOAM5303xlsDfRB1BQrOlUs3wKpDby3VvVEx0XxN+LhLcNIxGIGRS80O F8L94ClErdiKPmzSs58RWg== X-Google-Smtp-Source: ABdhPJwXsUOdBoxG1hqbkTvcWRCS/9/3qi9AIdeT/TMf/FXFFXd3jcCl4evlYyv+FoXvTFxkkQtSpQ== X-Received: by 2002:a6b:b48c:: with SMTP id d134mr3385351iof.115.1599861094893; Fri, 11 Sep 2020 14:51:34 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.251]) by smtp.googlemail.com with ESMTPSA id a20sm1927966ilq.57.2020.09.11.14.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2020 14:51:34 -0700 (PDT) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexander Shishkin , Namhyung Kim , Raphael Gault , Mark Rutland , Jonathan Cameron , Ian Rogers , honnappa.nagarahalli@arm.com Subject: [PATCH v3 10/10] Documentation: arm64: Document PMU counters access from userspace Date: Fri, 11 Sep 2020 15:51:18 -0600 Message-Id: <20200911215118.2887710-11-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911215118.2887710-1-robh@kernel.org> References: <20200911215118.2887710-1-robh@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Raphael Gault Add a documentation file to describe the access to the pmu hardware counters from userspace Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/index.rst | 1 + .../arm64/perf_counter_user_access.rst | 56 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 Documentation/arm64/perf_counter_user_access.rst diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst index d9665d83c53a..c712a08e7627 100644 --- a/Documentation/arm64/index.rst +++ b/Documentation/arm64/index.rst @@ -15,6 +15,7 @@ ARM64 Architecture legacy_instructions memory perf + perf_counter_user_access pointer-authentication silicon-errata sve diff --git a/Documentation/arm64/perf_counter_user_access.rst b/Documentation/arm64/perf_counter_user_access.rst new file mode 100644 index 000000000000..e49e141f10cc --- /dev/null +++ b/Documentation/arm64/perf_counter_user_access.rst @@ -0,0 +1,56 @@ +============================================= +Access to PMU hardware counter from userspace +============================================= + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 pmuv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counter it is necessary to open the event +using the perf tool interface: the sys_perf_event_open syscall returns a fd which +can subsequently be used with the mmap syscall in order to retrieve a page of +memory containing information about the event. +The PMU driver uses this page to expose to the user the hardware counter's +index and other necessary data. Using this index enables the user to access the +PMU registers using the `mrs` instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events +-------------------- +Chained events are not supported in userspace. If a 64-bit counter is requested, +userspace access will only be enabled if the underlying counter is 64-bit. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15D3AC433E2 for ; Fri, 11 Sep 2020 21:54:00 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B761122207 for ; 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Fri, 11 Sep 2020 14:51:34 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.251]) by smtp.googlemail.com with ESMTPSA id a20sm1927966ilq.57.2020.09.11.14.51.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2020 14:51:34 -0700 (PDT) From: Rob Herring To: Will Deacon , Catalin Marinas , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Jiri Olsa Subject: [PATCH v3 10/10] Documentation: arm64: Document PMU counters access from userspace Date: Fri, 11 Sep 2020 15:51:18 -0600 Message-Id: <20200911215118.2887710-11-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200911215118.2887710-1-robh@kernel.org> References: <20200911215118.2887710-1-robh@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200911_175135_658496_85E2C6BB X-CRM114-Status: GOOD ( 21.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Ian Rogers , Alexander Shishkin , linux-kernel@vger.kernel.org, honnappa.nagarahalli@arm.com, Raphael Gault , Jonathan Cameron , Namhyung Kim , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raphael Gault Add a documentation file to describe the access to the pmu hardware counters from userspace Signed-off-by: Raphael Gault Signed-off-by: Rob Herring --- v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/index.rst | 1 + .../arm64/perf_counter_user_access.rst | 56 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 Documentation/arm64/perf_counter_user_access.rst diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst index d9665d83c53a..c712a08e7627 100644 --- a/Documentation/arm64/index.rst +++ b/Documentation/arm64/index.rst @@ -15,6 +15,7 @@ ARM64 Architecture legacy_instructions memory perf + perf_counter_user_access pointer-authentication silicon-errata sve diff --git a/Documentation/arm64/perf_counter_user_access.rst b/Documentation/arm64/perf_counter_user_access.rst new file mode 100644 index 000000000000..e49e141f10cc --- /dev/null +++ b/Documentation/arm64/perf_counter_user_access.rst @@ -0,0 +1,56 @@ +============================================= +Access to PMU hardware counter from userspace +============================================= + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 pmuv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counter it is necessary to open the event +using the perf tool interface: the sys_perf_event_open syscall returns a fd which +can subsequently be used with the mmap syscall in order to retrieve a page of +memory containing information about the event. +The PMU driver uses this page to expose to the user the hardware counter's +index and other necessary data. Using this index enables the user to access the +PMU registers using the `mrs` instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events +-------------------- +Chained events are not supported in userspace. If a 64-bit counter is requested, +userspace access will only be enabled if the underlying counter is 64-bit. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel