From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4DADC433E2 for ; Mon, 14 Sep 2020 23:22:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EE8720936 for ; Mon, 14 Sep 2020 23:22:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1600125734; bh=T1yKfZmZkF9mjYf/osKudHzqMUob7Uq2u8zUee9lAuc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=xSZTUTczsw45KYg+aLpVTb7HQl8e7gBwAmuJx8PPhVCzMLUICVBbVH0MpZN7vm5UM EnFtqxFLEwJ51/w5XymBcWBi/0EJeOQdNKv62bQzB27RrtK0YCUQYY2ENCyU+hv6Pb F8cM/6YQ0xNqS2+Q+7XG29F0Mqitvvti53Vsc6a0= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726040AbgINXWN (ORCPT ); Mon, 14 Sep 2020 19:22:13 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:38196 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725953AbgINXWI (ORCPT ); Mon, 14 Sep 2020 19:22:08 -0400 Received: by mail-io1-f67.google.com with SMTP id h4so2036997ioe.5; Mon, 14 Sep 2020 16:22:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=uBJaBVM5qSlFTMBKBPrOEf8kKcQcYDcZTztd+soUSx4=; b=R5k8LKDn0xZ+qT8WDMybwERUSMk3OzsOv3b8DmSIYxlW9uvkQdwitx+Wr7XvP6pOX9 jgzADxk7mcRvu+imlEJ9w7ww4+Hrx8U2lpFkAIZamQuQGz4azqV1UKBq8fS8fHlMplpP G8SHxdtFoR9ECzslIezCOxmUnXJ9+UpOL6N+fYZnsgoMmG+E4F1bQ/jviOXNTcRf2Qji uUHXrnqmzyOG4nsKt2W64QnsMc2Y67054HZ/+70XLgL3JU2sTRa410xHY98/EHdG9mkg W+JQqoS4o8bECzKdUcloR4MTMM6U5ayVgdyAShHLa0dW58YJo7+KZoFPO7G/3rpgfCDq WhNw== X-Gm-Message-State: AOAM530xP4G5gsbWSZGA9x5nmcJ6bzAMspkizblQRw3E7hcBrDwAncQh VxP4NmT8kpNdBuhXZr88/g== X-Google-Smtp-Source: ABdhPJyjhpRe595cAwHbYUZWFvDATVusi2POp3kZjIUBYWVD1rY+NkcI7WXZM4X4jBE2OGqhNcCKPQ== X-Received: by 2002:a02:778e:: with SMTP id g136mr15690979jac.49.1600125726390; Mon, 14 Sep 2020 16:22:06 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id i9sm4129664ilj.71.2020.09.14.16.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 16:22:05 -0700 (PDT) Received: (nullmailer pid 465226 invoked by uid 1000); Mon, 14 Sep 2020 23:22:04 -0000 Date: Mon, 14 Sep 2020 17:22:04 -0600 From: Rob Herring To: Yong Wu Cc: Joerg Roedel , Matthias Brugger , Robin Murphy , Will Deacon , Evan Green , Tomasz Figa , linux-mediatek@lists.infradead.org, srv_heupstream@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, youlin.pei@mediatek.com, Nicolas Boichat , anan.sun@mediatek.com, chao.hao@mediatek.com, ming-fan.chen@mediatek.com Subject: Re: [PATCH v2 01/23] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Message-ID: <20200914232204.GA457962@bogus> References: <20200905080920.13396-1-yong.wu@mediatek.com> <20200905080920.13396-2-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200905080920.13396-2-yong.wu@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Sep 05, 2020 at 04:08:58PM +0800, Yong Wu wrote: > Convert MediaTek IOMMU to DT schema. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.txt | 103 ------------ > .../bindings/iommu/mediatek,iommu.yaml | 150 ++++++++++++++++++ > 2 files changed, 150 insertions(+), 103 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > deleted file mode 100644 > index c1ccd8582eb2..000000000000 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ /dev/null > @@ -1,103 +0,0 @@ > -* Mediatek IOMMU Architecture Implementation > - > - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and > -this M4U have two generations of HW architecture. Generation one uses flat > -pagetable, and only supports 4K size page mapping. Generation two uses the > -ARM Short-Descriptor translation table format for address translation. > - > - About the M4U Hardware Block Diagram, please check below: > - > - EMI (External Memory Interface) > - | > - m4u (Multimedia Memory Management Unit) > - | > - +--------+ > - | | > - gals0-rx gals1-rx (Global Async Local Sync rx) > - | | > - | | > - gals0-tx gals1-tx (Global Async Local Sync tx) > - | | Some SoCs may have GALS. > - +--------+ > - | > - SMI Common(Smart Multimedia Interface Common) > - | > - +----------------+------- > - | | > - | gals-rx There may be GALS in some larbs. > - | | > - | | > - | gals-tx > - | | > - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > - (display) (vdec) > - | | > - | | > - +-----+-----+ +----+----+ > - | | | | | | > - | | |... | | | ... There are different ports in each larb. > - | | | | | | > -OVL0 RDMA0 WDMA0 MC PP VLD > - > - As above, The Multimedia HW will go through SMI and M4U while it > -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > -smi local arbiter and smi common. It will control whether the Multimedia > -HW should go though the m4u for translation or bypass it and talk > -directly with EMI. And also SMI help control the power domain and clocks for > -each local arbiter. > - Normally we specify a local arbiter(larb) for each multimedia HW > -like display, video decode, and camera. And there are different ports > -in each larb. Take a example, There are many ports like MC, PP, VLD in the > -video decode local arbiter, all these ports are according to the video HW. > - In some SoCs, there may be a GALS(Global Async Local Sync) module between > -smi-common and m4u, and additional GALS module between smi-larb and > -smi-common. GALS can been seen as a "asynchronous fifo" which could help > -synchronize for the modules in different clock frequency. > - > -Required properties: > -- compatible : must be one of the following string: > - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > - generation one m4u HW. > - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > -- reg : m4u register base and size. > -- interrupts : the interrupt of m4u. > -- clocks : must contain one entry for each clock-names. > -- clock-names : Only 1 optional clock: > - - "bclk": the block clock of m4u. > - Here is the list which require this "bclk": > - - mt2701, mt2712, mt7623 and mt8173. > - Note that m4u use the EMI clock which always has been enabled before kernel > - if there is no this "bclk". > -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. > - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > - according to the local arbiter index, like larb0, larb1, larb2... > -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > - Specifies the mtk_m4u_id as defined in > - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > - dt-binding/memory/mt2712-larb-port.h for mt2712, > - dt-binding/memory/mt6779-larb-port.h for mt6779, > - dt-binding/memory/mt8173-larb-port.h for mt8173, and > - dt-binding/memory/mt8183-larb-port.h for mt8183. > - > -Example: > - iommu: iommu@10205000 { > - compatible = "mediatek,mt8173-m4u"; > - reg = <0 0x10205000 0 0x1000>; > - interrupts = ; > - clocks = <&infracfg CLK_INFRA_M4U>; > - clock-names = "bclk"; > - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; > - #iommu-cells = <1>; > - }; > - > -Example for a client device: > - display { > - compatible = "mediatek,mt8173-disp"; > - iommus = <&iommu M4U_PORT_DISP_OVL0>, > - <&iommu M4U_PORT_DISP_RDMA0>; > - ... > - }; > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > new file mode 100644 > index 000000000000..d7b31bda3e35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek IOMMU Architecture Implementation > + > +maintainers: > + - Yong Wu > + - Chao Hao > + > +description: |+ > + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and > + this M4U have two generations of HW architecture. Generation one uses flat > + pagetable, and only supports 4K size page mapping. Generation two uses the > + ARM Short-Descriptor translation table format for address translation. > + > + About the M4U Hardware Block Diagram, please check below: > + > + EMI (External Memory Interface) > + | > + m4u (Multimedia Memory Management Unit) > + | > + +--------+ > + | | > + gals0-rx gals1-rx (Global Async Local Sync rx) > + | | > + | | > + gals0-tx gals1-tx (Global Async Local Sync tx) > + | | Some SoCs may have GALS. > + +--------+ > + | > + SMI Common(Smart Multimedia Interface Common) > + | > + +----------------+------- > + | | > + | gals-rx There may be GALS in some larbs. > + | | > + | | > + | gals-tx > + | | > + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > + (display) (vdec) > + | | > + | | > + +-----+-----+ +----+----+ > + | | | | | | > + | | |... | | | ... There are different ports in each larb. > + | | | | | | > + OVL0 RDMA0 WDMA0 MC PP VLD > + > + As above, The Multimedia HW will go through SMI and M4U while it > + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > + smi local arbiter and smi common. It will control whether the Multimedia > + HW should go though the m4u for translation or bypass it and talk > + directly with EMI. And also SMI help control the power domain and clocks for > + each local arbiter. > + > + Normally we specify a local arbiter(larb) for each multimedia HW > + like display, video decode, and camera. And there are different ports > + in each larb. Take a example, There are many ports like MC, PP, VLD in the > + video decode local arbiter, all these ports are according to the video HW. > + > + In some SoCs, there may be a GALS(Global Async Local Sync) module between > + smi-common and m4u, and additional GALS module between smi-larb and > + smi-common. GALS can been seen as a "asynchronous fifo" which could help > + synchronize for the modules in different clock frequency. > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-m4u #mt2701 generation one HW > + - mediatek,mt2712-m4u #mt2712 generation two HW > + - mediatek,mt6779-m4u #mt6779 generation two HW > + - mediatek,mt7623-m4u, mediatek,mt2701-m4u #mt7623 generation one HW This is not right. items: - const: mediatek,mt7623-m4u - const: mediatek,mt2701-m4u And that has to be under a 'oneOf' with the rest of this. > + - mediatek,mt8173-m4u #mt8173 generation two HW > + - mediatek,mt8183-m4u #mt8183 generation two HW > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + description: | > + bclk is optional. here is the list which require this bclk: > + mt2701, mt2712, mt7623 and mt8173. > + M4U will use the EMI clock which always has been enabled before > + kernel if there is no this bclk. > + items: > + - description: bclk is the block clock. > + > + clock-names: > + items: > + - const: bclk > + > + mediatek,larbs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle to the local arbiters in the current Socs. > + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort > + according to the local arbiter index, like larb0, larb1, larb2... > + > + '#iommu-cells': > + const: 1 > + description: | > + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as > + defined in > + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, > + dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > + dt-binding/memory/mt8173-larb-port.h for mt8173, > + dt-binding/memory/mt8183-larb-port.h for mt8183. > + > +required: > + - compatible > + - reg > + - interrupts > + - mediatek,larbs > + - '#iommu-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + iommu: iommu@10205000 { > + compatible = "mediatek,mt8173-m4u"; > + reg = <0x10205000 0x1000>; > + interrupts = ; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2 > + &larb3 &larb4 &larb5>; > + #iommu-cells = <1>; > + }; > + > + - | > + #include > + > + /* Example for a client device */ > + display { > + compatible = "mediatek,mt8173-disp"; > + iommus = <&iommu M4U_PORT_DISP_OVL0>, > + <&iommu M4U_PORT_DISP_RDMA0>; > + }; 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Mon, 14 Sep 2020 16:22:06 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id i9sm4129664ilj.71.2020.09.14.16.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 16:22:05 -0700 (PDT) Received: (nullmailer pid 465226 invoked by uid 1000); Mon, 14 Sep 2020 23:22:04 -0000 Date: Mon, 14 Sep 2020 17:22:04 -0600 From: Rob Herring To: Yong Wu Subject: Re: [PATCH v2 01/23] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Message-ID: <20200914232204.GA457962@bogus> References: <20200905080920.13396-1-yong.wu@mediatek.com> <20200905080920.13396-2-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200905080920.13396-2-yong.wu@mediatek.com> Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Sat, Sep 05, 2020 at 04:08:58PM +0800, Yong Wu wrote: > Convert MediaTek IOMMU to DT schema. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.txt | 103 ------------ > .../bindings/iommu/mediatek,iommu.yaml | 150 ++++++++++++++++++ > 2 files changed, 150 insertions(+), 103 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > deleted file mode 100644 > index c1ccd8582eb2..000000000000 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ /dev/null > @@ -1,103 +0,0 @@ > -* Mediatek IOMMU Architecture Implementation > - > - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and > -this M4U have two generations of HW architecture. Generation one uses flat > -pagetable, and only supports 4K size page mapping. Generation two uses the > -ARM Short-Descriptor translation table format for address translation. > - > - About the M4U Hardware Block Diagram, please check below: > - > - EMI (External Memory Interface) > - | > - m4u (Multimedia Memory Management Unit) > - | > - +--------+ > - | | > - gals0-rx gals1-rx (Global Async Local Sync rx) > - | | > - | | > - gals0-tx gals1-tx (Global Async Local Sync tx) > - | | Some SoCs may have GALS. > - +--------+ > - | > - SMI Common(Smart Multimedia Interface Common) > - | > - +----------------+------- > - | | > - | gals-rx There may be GALS in some larbs. > - | | > - | | > - | gals-tx > - | | > - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > - (display) (vdec) > - | | > - | | > - +-----+-----+ +----+----+ > - | | | | | | > - | | |... | | | ... There are different ports in each larb. > - | | | | | | > -OVL0 RDMA0 WDMA0 MC PP VLD > - > - As above, The Multimedia HW will go through SMI and M4U while it > -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > -smi local arbiter and smi common. It will control whether the Multimedia > -HW should go though the m4u for translation or bypass it and talk > -directly with EMI. And also SMI help control the power domain and clocks for > -each local arbiter. > - Normally we specify a local arbiter(larb) for each multimedia HW > -like display, video decode, and camera. And there are different ports > -in each larb. Take a example, There are many ports like MC, PP, VLD in the > -video decode local arbiter, all these ports are according to the video HW. > - In some SoCs, there may be a GALS(Global Async Local Sync) module between > -smi-common and m4u, and additional GALS module between smi-larb and > -smi-common. GALS can been seen as a "asynchronous fifo" which could help > -synchronize for the modules in different clock frequency. > - > -Required properties: > -- compatible : must be one of the following string: > - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > - generation one m4u HW. > - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > -- reg : m4u register base and size. > -- interrupts : the interrupt of m4u. > -- clocks : must contain one entry for each clock-names. > -- clock-names : Only 1 optional clock: > - - "bclk": the block clock of m4u. > - Here is the list which require this "bclk": > - - mt2701, mt2712, mt7623 and mt8173. > - Note that m4u use the EMI clock which always has been enabled before kernel > - if there is no this "bclk". > -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. > - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > - according to the local arbiter index, like larb0, larb1, larb2... > -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > - Specifies the mtk_m4u_id as defined in > - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > - dt-binding/memory/mt2712-larb-port.h for mt2712, > - dt-binding/memory/mt6779-larb-port.h for mt6779, > - dt-binding/memory/mt8173-larb-port.h for mt8173, and > - dt-binding/memory/mt8183-larb-port.h for mt8183. > - > -Example: > - iommu: iommu@10205000 { > - compatible = "mediatek,mt8173-m4u"; > - reg = <0 0x10205000 0 0x1000>; > - interrupts = ; > - clocks = <&infracfg CLK_INFRA_M4U>; > - clock-names = "bclk"; > - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; > - #iommu-cells = <1>; > - }; > - > -Example for a client device: > - display { > - compatible = "mediatek,mt8173-disp"; > - iommus = <&iommu M4U_PORT_DISP_OVL0>, > - <&iommu M4U_PORT_DISP_RDMA0>; > - ... > - }; > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > new file mode 100644 > index 000000000000..d7b31bda3e35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek IOMMU Architecture Implementation > + > +maintainers: > + - Yong Wu > + - Chao Hao > + > +description: |+ > + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and > + this M4U have two generations of HW architecture. Generation one uses flat > + pagetable, and only supports 4K size page mapping. Generation two uses the > + ARM Short-Descriptor translation table format for address translation. > + > + About the M4U Hardware Block Diagram, please check below: > + > + EMI (External Memory Interface) > + | > + m4u (Multimedia Memory Management Unit) > + | > + +--------+ > + | | > + gals0-rx gals1-rx (Global Async Local Sync rx) > + | | > + | | > + gals0-tx gals1-tx (Global Async Local Sync tx) > + | | Some SoCs may have GALS. > + +--------+ > + | > + SMI Common(Smart Multimedia Interface Common) > + | > + +----------------+------- > + | | > + | gals-rx There may be GALS in some larbs. > + | | > + | | > + | gals-tx > + | | > + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > + (display) (vdec) > + | | > + | | > + +-----+-----+ +----+----+ > + | | | | | | > + | | |... | | | ... There are different ports in each larb. > + | | | | | | > + OVL0 RDMA0 WDMA0 MC PP VLD > + > + As above, The Multimedia HW will go through SMI and M4U while it > + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > + smi local arbiter and smi common. It will control whether the Multimedia > + HW should go though the m4u for translation or bypass it and talk > + directly with EMI. And also SMI help control the power domain and clocks for > + each local arbiter. > + > + Normally we specify a local arbiter(larb) for each multimedia HW > + like display, video decode, and camera. And there are different ports > + in each larb. Take a example, There are many ports like MC, PP, VLD in the > + video decode local arbiter, all these ports are according to the video HW. > + > + In some SoCs, there may be a GALS(Global Async Local Sync) module between > + smi-common and m4u, and additional GALS module between smi-larb and > + smi-common. GALS can been seen as a "asynchronous fifo" which could help > + synchronize for the modules in different clock frequency. > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-m4u #mt2701 generation one HW > + - mediatek,mt2712-m4u #mt2712 generation two HW > + - mediatek,mt6779-m4u #mt6779 generation two HW > + - mediatek,mt7623-m4u, mediatek,mt2701-m4u #mt7623 generation one HW This is not right. items: - const: mediatek,mt7623-m4u - const: mediatek,mt2701-m4u And that has to be under a 'oneOf' with the rest of this. > + - mediatek,mt8173-m4u #mt8173 generation two HW > + - mediatek,mt8183-m4u #mt8183 generation two HW > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + description: | > + bclk is optional. here is the list which require this bclk: > + mt2701, mt2712, mt7623 and mt8173. > + M4U will use the EMI clock which always has been enabled before > + kernel if there is no this bclk. > + items: > + - description: bclk is the block clock. > + > + clock-names: > + items: > + - const: bclk > + > + mediatek,larbs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle to the local arbiters in the current Socs. > + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort > + according to the local arbiter index, like larb0, larb1, larb2... > + > + '#iommu-cells': > + const: 1 > + description: | > + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as > + defined in > + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, > + dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > + dt-binding/memory/mt8173-larb-port.h for mt8173, > + dt-binding/memory/mt8183-larb-port.h for mt8183. > + > +required: > + - compatible > + - reg > + - interrupts > + - mediatek,larbs > + - '#iommu-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + iommu: iommu@10205000 { > + compatible = "mediatek,mt8173-m4u"; > + reg = <0x10205000 0x1000>; > + interrupts = ; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2 > + &larb3 &larb4 &larb5>; > + #iommu-cells = <1>; > + }; > + > + - | > + #include > + > + /* Example for a client device */ > + display { > + compatible = "mediatek,mt8173-disp"; > + iommus = <&iommu M4U_PORT_DISP_OVL0>, > + <&iommu M4U_PORT_DISP_RDMA0>; > + }; > -- > 2.18.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2371C43461 for ; Mon, 14 Sep 2020 23:22:21 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6D65020936 for ; Mon, 14 Sep 2020 23:22:21 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Mon, 14 Sep 2020 16:22:06 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id i9sm4129664ilj.71.2020.09.14.16.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 16:22:05 -0700 (PDT) Received: (nullmailer pid 465226 invoked by uid 1000); Mon, 14 Sep 2020 23:22:04 -0000 Date: Mon, 14 Sep 2020 17:22:04 -0600 From: Rob Herring To: Yong Wu Subject: Re: [PATCH v2 01/23] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Message-ID: <20200914232204.GA457962@bogus> References: <20200905080920.13396-1-yong.wu@mediatek.com> <20200905080920.13396-2-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200905080920.13396-2-yong.wu@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200914_192207_562797_7E44B22B X-CRM114-Status: GOOD ( 34.01 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Sat, Sep 05, 2020 at 04:08:58PM +0800, Yong Wu wrote: > Convert MediaTek IOMMU to DT schema. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.txt | 103 ------------ > .../bindings/iommu/mediatek,iommu.yaml | 150 ++++++++++++++++++ > 2 files changed, 150 insertions(+), 103 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > deleted file mode 100644 > index c1ccd8582eb2..000000000000 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ /dev/null > @@ -1,103 +0,0 @@ > -* Mediatek IOMMU Architecture Implementation > - > - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and > -this M4U have two generations of HW architecture. Generation one uses flat > -pagetable, and only supports 4K size page mapping. Generation two uses the > -ARM Short-Descriptor translation table format for address translation. > - > - About the M4U Hardware Block Diagram, please check below: > - > - EMI (External Memory Interface) > - | > - m4u (Multimedia Memory Management Unit) > - | > - +--------+ > - | | > - gals0-rx gals1-rx (Global Async Local Sync rx) > - | | > - | | > - gals0-tx gals1-tx (Global Async Local Sync tx) > - | | Some SoCs may have GALS. > - +--------+ > - | > - SMI Common(Smart Multimedia Interface Common) > - | > - +----------------+------- > - | | > - | gals-rx There may be GALS in some larbs. > - | | > - | | > - | gals-tx > - | | > - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > - (display) (vdec) > - | | > - | | > - +-----+-----+ +----+----+ > - | | | | | | > - | | |... | | | ... There are different ports in each larb. > - | | | | | | > -OVL0 RDMA0 WDMA0 MC PP VLD > - > - As above, The Multimedia HW will go through SMI and M4U while it > -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > -smi local arbiter and smi common. It will control whether the Multimedia > -HW should go though the m4u for translation or bypass it and talk > -directly with EMI. And also SMI help control the power domain and clocks for > -each local arbiter. > - Normally we specify a local arbiter(larb) for each multimedia HW > -like display, video decode, and camera. And there are different ports > -in each larb. Take a example, There are many ports like MC, PP, VLD in the > -video decode local arbiter, all these ports are according to the video HW. > - In some SoCs, there may be a GALS(Global Async Local Sync) module between > -smi-common and m4u, and additional GALS module between smi-larb and > -smi-common. GALS can been seen as a "asynchronous fifo" which could help > -synchronize for the modules in different clock frequency. > - > -Required properties: > -- compatible : must be one of the following string: > - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > - generation one m4u HW. > - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > -- reg : m4u register base and size. > -- interrupts : the interrupt of m4u. > -- clocks : must contain one entry for each clock-names. > -- clock-names : Only 1 optional clock: > - - "bclk": the block clock of m4u. > - Here is the list which require this "bclk": > - - mt2701, mt2712, mt7623 and mt8173. > - Note that m4u use the EMI clock which always has been enabled before kernel > - if there is no this "bclk". > -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. > - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > - according to the local arbiter index, like larb0, larb1, larb2... > -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > - Specifies the mtk_m4u_id as defined in > - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > - dt-binding/memory/mt2712-larb-port.h for mt2712, > - dt-binding/memory/mt6779-larb-port.h for mt6779, > - dt-binding/memory/mt8173-larb-port.h for mt8173, and > - dt-binding/memory/mt8183-larb-port.h for mt8183. > - > -Example: > - iommu: iommu@10205000 { > - compatible = "mediatek,mt8173-m4u"; > - reg = <0 0x10205000 0 0x1000>; > - interrupts = ; > - clocks = <&infracfg CLK_INFRA_M4U>; > - clock-names = "bclk"; > - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; > - #iommu-cells = <1>; > - }; > - > -Example for a client device: > - display { > - compatible = "mediatek,mt8173-disp"; > - iommus = <&iommu M4U_PORT_DISP_OVL0>, > - <&iommu M4U_PORT_DISP_RDMA0>; > - ... > - }; > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > new file mode 100644 > index 000000000000..d7b31bda3e35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek IOMMU Architecture Implementation > + > +maintainers: > + - Yong Wu > + - Chao Hao > + > +description: |+ > + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and > + this M4U have two generations of HW architecture. Generation one uses flat > + pagetable, and only supports 4K size page mapping. Generation two uses the > + ARM Short-Descriptor translation table format for address translation. > + > + About the M4U Hardware Block Diagram, please check below: > + > + EMI (External Memory Interface) > + | > + m4u (Multimedia Memory Management Unit) > + | > + +--------+ > + | | > + gals0-rx gals1-rx (Global Async Local Sync rx) > + | | > + | | > + gals0-tx gals1-tx (Global Async Local Sync tx) > + | | Some SoCs may have GALS. > + +--------+ > + | > + SMI Common(Smart Multimedia Interface Common) > + | > + +----------------+------- > + | | > + | gals-rx There may be GALS in some larbs. > + | | > + | | > + | gals-tx > + | | > + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > + (display) (vdec) > + | | > + | | > + +-----+-----+ +----+----+ > + | | | | | | > + | | |... | | | ... There are different ports in each larb. > + | | | | | | > + OVL0 RDMA0 WDMA0 MC PP VLD > + > + As above, The Multimedia HW will go through SMI and M4U while it > + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > + smi local arbiter and smi common. It will control whether the Multimedia > + HW should go though the m4u for translation or bypass it and talk > + directly with EMI. And also SMI help control the power domain and clocks for > + each local arbiter. > + > + Normally we specify a local arbiter(larb) for each multimedia HW > + like display, video decode, and camera. And there are different ports > + in each larb. Take a example, There are many ports like MC, PP, VLD in the > + video decode local arbiter, all these ports are according to the video HW. > + > + In some SoCs, there may be a GALS(Global Async Local Sync) module between > + smi-common and m4u, and additional GALS module between smi-larb and > + smi-common. GALS can been seen as a "asynchronous fifo" which could help > + synchronize for the modules in different clock frequency. > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-m4u #mt2701 generation one HW > + - mediatek,mt2712-m4u #mt2712 generation two HW > + - mediatek,mt6779-m4u #mt6779 generation two HW > + - mediatek,mt7623-m4u, mediatek,mt2701-m4u #mt7623 generation one HW This is not right. items: - const: mediatek,mt7623-m4u - const: mediatek,mt2701-m4u And that has to be under a 'oneOf' with the rest of this. > + - mediatek,mt8173-m4u #mt8173 generation two HW > + - mediatek,mt8183-m4u #mt8183 generation two HW > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + description: | > + bclk is optional. here is the list which require this bclk: > + mt2701, mt2712, mt7623 and mt8173. > + M4U will use the EMI clock which always has been enabled before > + kernel if there is no this bclk. > + items: > + - description: bclk is the block clock. > + > + clock-names: > + items: > + - const: bclk > + > + mediatek,larbs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle to the local arbiters in the current Socs. > + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort > + according to the local arbiter index, like larb0, larb1, larb2... > + > + '#iommu-cells': > + const: 1 > + description: | > + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as > + defined in > + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, > + dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > + dt-binding/memory/mt8173-larb-port.h for mt8173, > + dt-binding/memory/mt8183-larb-port.h for mt8183. > + > +required: > + - compatible > + - reg > + - interrupts > + - mediatek,larbs > + - '#iommu-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + iommu: iommu@10205000 { > + compatible = "mediatek,mt8173-m4u"; > + reg = <0x10205000 0x1000>; > + interrupts = ; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2 > + &larb3 &larb4 &larb5>; > + #iommu-cells = <1>; > + }; > + > + - | > + #include > + > + /* Example for a client device */ > + display { > + compatible = "mediatek,mt8173-disp"; > + iommus = <&iommu M4U_PORT_DISP_OVL0>, > + <&iommu M4U_PORT_DISP_RDMA0>; > + }; > -- > 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64F01C43461 for ; Mon, 14 Sep 2020 23:24:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4DCF20936 for ; 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Mon, 14 Sep 2020 16:22:06 -0700 (PDT) Received: from xps15 ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id i9sm4129664ilj.71.2020.09.14.16.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 16:22:05 -0700 (PDT) Received: (nullmailer pid 465226 invoked by uid 1000); Mon, 14 Sep 2020 23:22:04 -0000 Date: Mon, 14 Sep 2020 17:22:04 -0600 From: Rob Herring To: Yong Wu Subject: Re: [PATCH v2 01/23] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Message-ID: <20200914232204.GA457962@bogus> References: <20200905080920.13396-1-yong.wu@mediatek.com> <20200905080920.13396-2-yong.wu@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200905080920.13396-2-yong.wu@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200914_192207_562797_7E44B22B X-CRM114-Status: GOOD ( 34.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , Joerg Roedel , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Sep 05, 2020 at 04:08:58PM +0800, Yong Wu wrote: > Convert MediaTek IOMMU to DT schema. > > Signed-off-by: Yong Wu > --- > .../bindings/iommu/mediatek,iommu.txt | 103 ------------ > .../bindings/iommu/mediatek,iommu.yaml | 150 ++++++++++++++++++ > 2 files changed, 150 insertions(+), 103 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > deleted file mode 100644 > index c1ccd8582eb2..000000000000 > --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > +++ /dev/null > @@ -1,103 +0,0 @@ > -* Mediatek IOMMU Architecture Implementation > - > - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and > -this M4U have two generations of HW architecture. Generation one uses flat > -pagetable, and only supports 4K size page mapping. Generation two uses the > -ARM Short-Descriptor translation table format for address translation. > - > - About the M4U Hardware Block Diagram, please check below: > - > - EMI (External Memory Interface) > - | > - m4u (Multimedia Memory Management Unit) > - | > - +--------+ > - | | > - gals0-rx gals1-rx (Global Async Local Sync rx) > - | | > - | | > - gals0-tx gals1-tx (Global Async Local Sync tx) > - | | Some SoCs may have GALS. > - +--------+ > - | > - SMI Common(Smart Multimedia Interface Common) > - | > - +----------------+------- > - | | > - | gals-rx There may be GALS in some larbs. > - | | > - | | > - | gals-tx > - | | > - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > - (display) (vdec) > - | | > - | | > - +-----+-----+ +----+----+ > - | | | | | | > - | | |... | | | ... There are different ports in each larb. > - | | | | | | > -OVL0 RDMA0 WDMA0 MC PP VLD > - > - As above, The Multimedia HW will go through SMI and M4U while it > -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > -smi local arbiter and smi common. It will control whether the Multimedia > -HW should go though the m4u for translation or bypass it and talk > -directly with EMI. And also SMI help control the power domain and clocks for > -each local arbiter. > - Normally we specify a local arbiter(larb) for each multimedia HW > -like display, video decode, and camera. And there are different ports > -in each larb. Take a example, There are many ports like MC, PP, VLD in the > -video decode local arbiter, all these ports are according to the video HW. > - In some SoCs, there may be a GALS(Global Async Local Sync) module between > -smi-common and m4u, and additional GALS module between smi-larb and > -smi-common. GALS can been seen as a "asynchronous fifo" which could help > -synchronize for the modules in different clock frequency. > - > -Required properties: > -- compatible : must be one of the following string: > - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. > - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. > - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. > - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses > - generation one m4u HW. > - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. > - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. > -- reg : m4u register base and size. > -- interrupts : the interrupt of m4u. > -- clocks : must contain one entry for each clock-names. > -- clock-names : Only 1 optional clock: > - - "bclk": the block clock of m4u. > - Here is the list which require this "bclk": > - - mt2701, mt2712, mt7623 and mt8173. > - Note that m4u use the EMI clock which always has been enabled before kernel > - if there is no this "bclk". > -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. > - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort > - according to the local arbiter index, like larb0, larb1, larb2... > -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. > - Specifies the mtk_m4u_id as defined in > - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 > - dt-binding/memory/mt2712-larb-port.h for mt2712, > - dt-binding/memory/mt6779-larb-port.h for mt6779, > - dt-binding/memory/mt8173-larb-port.h for mt8173, and > - dt-binding/memory/mt8183-larb-port.h for mt8183. > - > -Example: > - iommu: iommu@10205000 { > - compatible = "mediatek,mt8173-m4u"; > - reg = <0 0x10205000 0 0x1000>; > - interrupts = ; > - clocks = <&infracfg CLK_INFRA_M4U>; > - clock-names = "bclk"; > - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; > - #iommu-cells = <1>; > - }; > - > -Example for a client device: > - display { > - compatible = "mediatek,mt8173-disp"; > - iommus = <&iommu M4U_PORT_DISP_OVL0>, > - <&iommu M4U_PORT_DISP_RDMA0>; > - ... > - }; > diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > new file mode 100644 > index 000000000000..d7b31bda3e35 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek IOMMU Architecture Implementation > + > +maintainers: > + - Yong Wu > + - Chao Hao > + > +description: |+ > + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and > + this M4U have two generations of HW architecture. Generation one uses flat > + pagetable, and only supports 4K size page mapping. Generation two uses the > + ARM Short-Descriptor translation table format for address translation. > + > + About the M4U Hardware Block Diagram, please check below: > + > + EMI (External Memory Interface) > + | > + m4u (Multimedia Memory Management Unit) > + | > + +--------+ > + | | > + gals0-rx gals1-rx (Global Async Local Sync rx) > + | | > + | | > + gals0-tx gals1-tx (Global Async Local Sync tx) > + | | Some SoCs may have GALS. > + +--------+ > + | > + SMI Common(Smart Multimedia Interface Common) > + | > + +----------------+------- > + | | > + | gals-rx There may be GALS in some larbs. > + | | > + | | > + | gals-tx > + | | > + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). > + (display) (vdec) > + | | > + | | > + +-----+-----+ +----+----+ > + | | | | | | > + | | |... | | | ... There are different ports in each larb. > + | | | | | | > + OVL0 RDMA0 WDMA0 MC PP VLD > + > + As above, The Multimedia HW will go through SMI and M4U while it > + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain > + smi local arbiter and smi common. It will control whether the Multimedia > + HW should go though the m4u for translation or bypass it and talk > + directly with EMI. And also SMI help control the power domain and clocks for > + each local arbiter. > + > + Normally we specify a local arbiter(larb) for each multimedia HW > + like display, video decode, and camera. And there are different ports > + in each larb. Take a example, There are many ports like MC, PP, VLD in the > + video decode local arbiter, all these ports are according to the video HW. > + > + In some SoCs, there may be a GALS(Global Async Local Sync) module between > + smi-common and m4u, and additional GALS module between smi-larb and > + smi-common. GALS can been seen as a "asynchronous fifo" which could help > + synchronize for the modules in different clock frequency. > + > +properties: > + compatible: > + enum: > + - mediatek,mt2701-m4u #mt2701 generation one HW > + - mediatek,mt2712-m4u #mt2712 generation two HW > + - mediatek,mt6779-m4u #mt6779 generation two HW > + - mediatek,mt7623-m4u, mediatek,mt2701-m4u #mt7623 generation one HW This is not right. items: - const: mediatek,mt7623-m4u - const: mediatek,mt2701-m4u And that has to be under a 'oneOf' with the rest of this. > + - mediatek,mt8173-m4u #mt8173 generation two HW > + - mediatek,mt8183-m4u #mt8183 generation two HW > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + description: | > + bclk is optional. here is the list which require this bclk: > + mt2701, mt2712, mt7623 and mt8173. > + M4U will use the EMI clock which always has been enabled before > + kernel if there is no this bclk. > + items: > + - description: bclk is the block clock. > + > + clock-names: > + items: > + - const: bclk > + > + mediatek,larbs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: | > + List of phandle to the local arbiters in the current Socs. > + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort > + according to the local arbiter index, like larb0, larb1, larb2... > + > + '#iommu-cells': > + const: 1 > + description: | > + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as > + defined in > + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, > + dt-binding/memory/mt2712-larb-port.h for mt2712, > + dt-binding/memory/mt6779-larb-port.h for mt6779, > + dt-binding/memory/mt8173-larb-port.h for mt8173, > + dt-binding/memory/mt8183-larb-port.h for mt8183. > + > +required: > + - compatible > + - reg > + - interrupts > + - mediatek,larbs > + - '#iommu-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + > + iommu: iommu@10205000 { > + compatible = "mediatek,mt8173-m4u"; > + reg = <0x10205000 0x1000>; > + interrupts = ; > + clocks = <&infracfg CLK_INFRA_M4U>; > + clock-names = "bclk"; > + mediatek,larbs = <&larb0 &larb1 &larb2 > + &larb3 &larb4 &larb5>; > + #iommu-cells = <1>; > + }; > + > + - | > + #include > + > + /* Example for a client device */ > + display { > + compatible = "mediatek,mt8173-disp"; > + iommus = <&iommu M4U_PORT_DISP_OVL0>, > + <&iommu M4U_PORT_DISP_RDMA0>; > + }; > -- > 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel