From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13D67C433E2 for ; Thu, 17 Sep 2020 07:56:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F170221E8 for ; Thu, 17 Sep 2020 07:56:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alien8.de header.i=@alien8.de header.b="jahzhXRj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726347AbgIQH4O (ORCPT ); Thu, 17 Sep 2020 03:56:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726280AbgIQHys (ORCPT ); Thu, 17 Sep 2020 03:54:48 -0400 Received: from mail.skyhub.de (mail.skyhub.de [IPv6:2a01:4f8:190:11c2::b:1457]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDBEBC061788 for ; Thu, 17 Sep 2020 00:54:12 -0700 (PDT) Received: from zn.tnic (p200300ec2f1053007b81a97eebdb4df7.dip0.t-ipconnect.de [IPv6:2003:ec:2f10:5300:7b81:a97e:ebdb:4df7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.skyhub.de (SuperMail on ZX Spectrum 128k) with ESMTPSA id F19EE1EC0286; Thu, 17 Sep 2020 09:53:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1600329226; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=ewrYTBLqmR0WdfUwbHvpOSzEiXe9R9x+7NtUrZAyuck=; b=jahzhXRj6VqJO/u8dRJrB6L/MOuZjY9smlFNVagk55dbglzgn9wOm6eYabLOPPJHzddEKe iw9Bp6bs5HWH6CcFiM3g9kuEjxizytl3FF/vT+ANglOWtc1wSI/mN0xJGGZcIFfERAJbhE 5xkQQU1Cfslq+Fh+Pl2qMf7FlJXmsIQ= Date: Thu, 17 Sep 2020 09:53:38 +0200 From: Borislav Petkov To: Fenghua Yu Cc: Thomas Gleixner , Ingo Molnar , H Peter Anvin , Andy Lutomirski , Jean-Philippe Brucker , Christoph Hellwig , Peter Zijlstra , David Woodhouse , Lu Baolu , Dave Hansen , Tony Luck , Randy Dunlap , Ashok Raj , Jacob Jun Pan , Dave Jiang , Sohil Mehta , Ravi V Shankar , linux-kernel , x86 , iommu@lists.linux-foundation.org Subject: Re: [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing) Message-ID: <20200917075338.GC31960@zn.tnic> References: <1600187413-163670-1-git-send-email-fenghua.yu@intel.com> <1600187413-163670-4-git-send-email-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1600187413-163670-4-git-send-email-fenghua.yu@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 15, 2020 at 09:30:07AM -0700, Fenghua Yu wrote: > +Background > +========== > + > +Shared Virtual Addressing (SVA) allows the processor and device to use the > +same virtual addresses avoiding the need for software to translate virtual > +addresses to physical addresses. SVA is what PCIe calls Shared Virtual > +Memory (SVM). > + > +In addition to the convenience of using application virtual addresses > +by the device, it also doesn't require pinning pages for DMA. > +PCIe Address Translation Services (ATS) along with Page Request Interface > +(PRI) allow devices to function much the same way as the CPU handling > +application page-faults. For more information please refer to the PCIe > +specification Chapter 10: ATS Specification. > + > +Use of SVA requires IOMMU support in the platform. IOMMU also is required > +to support PCIe features ATS and PRI. ATS allows devices to cache > +translations for virtual addresses. The IOMMU driver uses the mmu_notifier() > +support to keep the device TLB cache and the CPU cache in sync. PRI allows > +the device to request paging the virtual address by using the CPU page tables > +before accessing the address. That still reads funny, the "the device to request paging the virtual address" part. Do you mean that per chance here: "Before the device can access that address, the device uses the PRI in order to request the virtual address to be paged in into the CPU page tables." ? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E253C43461 for ; Thu, 17 Sep 2020 07:53:56 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 79D0F21D7F for ; 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Thu, 17 Sep 2020 09:53:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alien8.de; s=dkim; t=1600329226; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:in-reply-to:in-reply-to: references:references; bh=ewrYTBLqmR0WdfUwbHvpOSzEiXe9R9x+7NtUrZAyuck=; b=jahzhXRj6VqJO/u8dRJrB6L/MOuZjY9smlFNVagk55dbglzgn9wOm6eYabLOPPJHzddEKe iw9Bp6bs5HWH6CcFiM3g9kuEjxizytl3FF/vT+ANglOWtc1wSI/mN0xJGGZcIFfERAJbhE 5xkQQU1Cfslq+Fh+Pl2qMf7FlJXmsIQ= Date: Thu, 17 Sep 2020 09:53:38 +0200 From: Borislav Petkov To: Fenghua Yu Subject: Re: [PATCH v8 3/9] Documentation/x86: Add documentation for SVA (Shared Virtual Addressing) Message-ID: <20200917075338.GC31960@zn.tnic> References: <1600187413-163670-1-git-send-email-fenghua.yu@intel.com> <1600187413-163670-4-git-send-email-fenghua.yu@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1600187413-163670-4-git-send-email-fenghua.yu@intel.com> Cc: Jean-Philippe Brucker , Tony Luck , Dave Jiang , Ashok Raj , Ravi V Shankar , Peter Zijlstra , Randy Dunlap , linux-kernel , Christoph Hellwig , Dave Hansen , iommu@lists.linux-foundation.org, Ingo Molnar , Jacob Jun Pan , Andy Lutomirski , H Peter Anvin , Thomas Gleixner , David Woodhouse , x86 X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" On Tue, Sep 15, 2020 at 09:30:07AM -0700, Fenghua Yu wrote: > +Background > +========== > + > +Shared Virtual Addressing (SVA) allows the processor and device to use the > +same virtual addresses avoiding the need for software to translate virtual > +addresses to physical addresses. SVA is what PCIe calls Shared Virtual > +Memory (SVM). > + > +In addition to the convenience of using application virtual addresses > +by the device, it also doesn't require pinning pages for DMA. > +PCIe Address Translation Services (ATS) along with Page Request Interface > +(PRI) allow devices to function much the same way as the CPU handling > +application page-faults. For more information please refer to the PCIe > +specification Chapter 10: ATS Specification. > + > +Use of SVA requires IOMMU support in the platform. IOMMU also is required > +to support PCIe features ATS and PRI. ATS allows devices to cache > +translations for virtual addresses. The IOMMU driver uses the mmu_notifier() > +support to keep the device TLB cache and the CPU cache in sync. PRI allows > +the device to request paging the virtual address by using the CPU page tables > +before accessing the address. That still reads funny, the "the device to request paging the virtual address" part. Do you mean that per chance here: "Before the device can access that address, the device uses the PRI in order to request the virtual address to be paged in into the CPU page tables." ? -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu