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From: Krish Sadhukhan <krish.sadhukhan@oracle.com>
To: kvm@vger.kernel.org
Cc: pbonzini@redhat.com, jmattson@google.com, tglx@linutronix.de,
	mingo@redhat.com, bp@alien8.de, x86@kernel.org,
	sean.j.christopherson@intel.com, vkuznets@redhat.com,
	wanpengli@tencent.com, joro@8bytes.org,
	dave.hansen@linux.intel.com, luto@kernel.org,
	peterz@infradead.org, linux-kernel@vger.kernel.org,
	hpa@zytor.com
Subject: [PATCH 2/3 v4] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domnains
Date: Thu, 17 Sep 2020 21:20:37 +0000	[thread overview]
Message-ID: <20200917212038.5090-3-krish.sadhukhan@oracle.com> (raw)
In-Reply-To: <20200917212038.5090-1-krish.sadhukhan@oracle.com>

In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page is enforced. In such a system,
it is not required for software to flush the page from all CPU caches in the
system prior to changing the value of the C-bit for the page.

Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
---
 arch/x86/mm/pat/set_memory.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index d1b2a889f035..40baa90e74f4 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -1999,7 +1999,7 @@ static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
 	/*
 	 * Before changing the encryption attribute, we need to flush caches.
 	 */
-	cpa_flush(&cpa, 1);
+	cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));
 
 	ret = __change_page_attr_set_clr(&cpa, 1);
 
-- 
2.18.4


  parent reply	other threads:[~2020-09-17 21:25 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-17 21:20 [PATCH 0/3 v4] x86: AMD: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-17 21:20 ` [PATCH 1/3 v4] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature Krish Sadhukhan
2020-09-18  7:58   ` [tip: x86/cpu] x86/cpu: " tip-bot2 for Krish Sadhukhan
2020-09-18  9:03   ` tip-bot2 for Krish Sadhukhan
2020-09-17 21:20 ` Krish Sadhukhan [this message]
2020-09-18  7:58   ` [tip: x86/cpu] x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains tip-bot2 for Krish Sadhukhan
2020-09-18  9:03   ` tip-bot2 for Krish Sadhukhan
2020-09-17 21:20 ` [PATCH 3/3 v4] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains Krish Sadhukhan
2020-09-18  7:56   ` Borislav Petkov
2020-09-19 15:18     ` Paolo Bonzini
2020-09-19 18:57   ` [tip: x86/cpu] " tip-bot2 for Krish Sadhukhan

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