From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B978C43463 for ; Fri, 18 Sep 2020 12:03:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 017C821582 for ; Fri, 18 Sep 2020 12:03:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 017C821582 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1861E6EC89; Fri, 18 Sep 2020 12:03:52 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC7B76EC89; Fri, 18 Sep 2020 12:03:50 +0000 (UTC) IronPort-SDR: jn2ihLM4Zqrx3EZeF45Aexs5k3YD1yzJUrVZIKKNyxQ2ctliw/kkL9o5C+gcnkcm5Y/r6EIGMD GP3OU401IpPA== X-IronPort-AV: E=McAfee;i="6000,8403,9747"; a="157307842" X-IronPort-AV: E=Sophos;i="5.77,274,1596524400"; d="scan'208";a="157307842" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2020 05:03:50 -0700 IronPort-SDR: dmjHVOI8ElHNttPpX1vhbWH6APMuxOYJ/DQlJdr2fy/auWfhP8Ly/l892HvnJmhz+6fvoesAfB 8e/dAUOrirnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,274,1596524400"; d="scan'208";a="344723037" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 18 Sep 2020 05:03:46 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 18 Sep 2020 15:03:45 +0300 Date: Fri, 18 Sep 2020 15:03:45 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Karthik B S Subject: Re: [PATCH v9 8/8] drm/i915: Enable async flips in i915 Message-ID: <20200918120345.GM6112@intel.com> References: <20200916150824.15749-1-karthik.b.s@intel.com> <20200916150824.15749-9-karthik.b.s@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200916150824.15749-9-karthik.b.s@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, nicholas.kazlauskas@amd.com, vandita.kulkarni@intel.com, uma.shankar@intel.com, daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Sep 16, 2020 at 08:38:24PM +0530, Karthik B S wrote: > Enable asynchronous flips in i915 for gen9+ platforms. > = > v2: -Async flip enablement should be a stand alone patch (Paulo) > = > v3: -Move the patch to the end of the series (Paulo) > = > v4: -Rebased. > = > v5: -Rebased. > = > v6: -Rebased. > = > v7: -Rebased. > = > v8: -Rebased. > = > v9: -Rebased. > = > Signed-off-by: Karthik B S > Signed-off-by: Vandita Kulkarni > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/d= rm/i915/display/intel_display.c > index 6f6edc581e14..e31abf5f1a9d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -18021,6 +18021,9 @@ static void intel_mode_config_init(struct drm_i91= 5_private *i915) > = > mode_config->funcs =3D &intel_mode_funcs; > = > + if (INTEL_GEN(i915) >=3D 9) > + mode_config->async_page_flip =3D true; > + Should have all we need for those platforms I think. Reviewed-by: Ville Syrj=E4l=E4 The followup to enable it for ilk+ would require a slight change to bump X-tiled surface alignment to 256KiB. Apart from the actual regiser smashing part that should be all we need really. Oh, and the double buffer bit w/a will also be needed on bdw. I've now tested snb/ivb/hsw/bdw and only bdw needs it. I guess that's not entirely unsurpising since bdw did introduce one other fail for the flip done interrupt (the interupt fires immediately = when the plane was disabled, so can't use flip done to determine when the plane has actually become visible). Fortunately that other fail should have no impact on using it for async flip completion. > /* > * Maximum framebuffer dimensions, chosen to match > * the maximum render engine surface size on gen4+. > -- = > 2.22.0 -- = Ville Syrj=E4l=E4 Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 537DDC43464 for ; Fri, 18 Sep 2020 12:03:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E2E0D21582 for ; Fri, 18 Sep 2020 12:03:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E2E0D21582 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8DB226ECE0; Fri, 18 Sep 2020 12:03:52 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC7B76EC89; Fri, 18 Sep 2020 12:03:50 +0000 (UTC) IronPort-SDR: jn2ihLM4Zqrx3EZeF45Aexs5k3YD1yzJUrVZIKKNyxQ2ctliw/kkL9o5C+gcnkcm5Y/r6EIGMD GP3OU401IpPA== X-IronPort-AV: E=McAfee;i="6000,8403,9747"; a="157307842" X-IronPort-AV: E=Sophos;i="5.77,274,1596524400"; d="scan'208";a="157307842" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2020 05:03:50 -0700 IronPort-SDR: dmjHVOI8ElHNttPpX1vhbWH6APMuxOYJ/DQlJdr2fy/auWfhP8Ly/l892HvnJmhz+6fvoesAfB 8e/dAUOrirnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,274,1596524400"; d="scan'208";a="344723037" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by FMSMGA003.fm.intel.com with SMTP; 18 Sep 2020 05:03:46 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 18 Sep 2020 15:03:45 +0300 Date: Fri, 18 Sep 2020 15:03:45 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Karthik B S Message-ID: <20200918120345.GM6112@intel.com> References: <20200916150824.15749-1-karthik.b.s@intel.com> <20200916150824.15749-9-karthik.b.s@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200916150824.15749-9-karthik.b.s@intel.com> X-Patchwork-Hint: comment User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH v9 8/8] drm/i915: Enable async flips in i915 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: paulo.r.zanoni@intel.com, michel@daenzer.net, dri-devel@lists.freedesktop.org, nicholas.kazlauskas@amd.com, daniel.vetter@intel.com, harry.wentland@amd.com, intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Wed, Sep 16, 2020 at 08:38:24PM +0530, Karthik B S wrote: > Enable asynchronous flips in i915 for gen9+ platforms. > = > v2: -Async flip enablement should be a stand alone patch (Paulo) > = > v3: -Move the patch to the end of the series (Paulo) > = > v4: -Rebased. > = > v5: -Rebased. > = > v6: -Rebased. > = > v7: -Rebased. > = > v8: -Rebased. > = > v9: -Rebased. > = > Signed-off-by: Karthik B S > Signed-off-by: Vandita Kulkarni > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/d= rm/i915/display/intel_display.c > index 6f6edc581e14..e31abf5f1a9d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -18021,6 +18021,9 @@ static void intel_mode_config_init(struct drm_i91= 5_private *i915) > = > mode_config->funcs =3D &intel_mode_funcs; > = > + if (INTEL_GEN(i915) >=3D 9) > + mode_config->async_page_flip =3D true; > + Should have all we need for those platforms I think. Reviewed-by: Ville Syrj=E4l=E4 The followup to enable it for ilk+ would require a slight change to bump X-tiled surface alignment to 256KiB. Apart from the actual regiser smashing part that should be all we need really. Oh, and the double buffer bit w/a will also be needed on bdw. I've now tested snb/ivb/hsw/bdw and only bdw needs it. I guess that's not entirely unsurpising since bdw did introduce one other fail for the flip done interrupt (the interupt fires immediately = when the plane was disabled, so can't use flip done to determine when the plane has actually become visible). Fortunately that other fail should have no impact on using it for async flip completion. > /* > * Maximum framebuffer dimensions, chosen to match > * the maximum render engine surface size on gen4+. > -- = > 2.22.0 -- = Ville Syrj=E4l=E4 Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx