From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96239C4727D for ; Tue, 22 Sep 2020 21:05:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F2F9206FB for ; Tue, 22 Sep 2020 21:05:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="k001Em5k" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726760AbgIVVE5 (ORCPT ); Tue, 22 Sep 2020 17:04:57 -0400 Received: from o1.b.az.sendgrid.net ([208.117.55.133]:30301 "EHLO o1.b.az.sendgrid.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726589AbgIVVEq (ORCPT ); Tue, 22 Sep 2020 17:04:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:in-reply-to:references:to:cc:content-type: content-transfer-encoding; s=001; bh=nAJZakghzr7JwdXt31dydBHC6AGXJnAIYTAyCKaQf5U=; b=k001Em5ks9QORaRnjuI7yiSHD0/K7UZjxrqC2pFrVS53JDxPnzNWRsmThLp6bLEI5Mca 4/YYJ3pSZWPpmjsq++O7csSSsVrXfwPxk6s6GROYAFs0jzpk8avKUk0attNcbEfCuKtVOy Rvf3iXzsfMQ90j9qaOtz6SSInjIV3f5rc= Received: by filterdrecv-p3las1-6f66587546-tf6q5 with SMTP id filterdrecv-p3las1-6f66587546-tf6q5-19-5F6A65BD-57 2020-09-22 20:59:42.035583574 +0000 UTC m=+82869.342859397 Received: from bionic.localdomain (unknown) by ismtpd0007p1lon1.sendgrid.net (SG) with ESMTP id L7ZyU879SjKUF6bCxXobkA Tue, 22 Sep 2020 20:59:41.567 +0000 (UTC) From: Jonas Karlman Subject: [PATCH v3 5/6] phy/rockchip: inno-hdmi: force set_rate on power_on Date: Tue, 22 Sep 2020 20:59:42 +0000 (UTC) Message-Id: <20200922205933.5540-6-jonas@kwiboo.se> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200922205933.5540-1-jonas@kwiboo.se> References: <20200108210740.28769-1-jonas@kwiboo.se> <20200922205933.5540-1-jonas@kwiboo.se> X-SG-EID: =?us-ascii?Q?TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxA?= =?us-ascii?Q?fZekEeQsTe+RrMu3cja6a0hwQH6xSmNBdIGRg9J?= =?us-ascii?Q?GdwnPbEq7RtjOs9+cav6Qmt6JmuUxSaXmS=2FBi9v?= =?us-ascii?Q?lihhpM20HgDQ24mV8MCNBrC8Tp6RDyAdAUJU2bW?= =?us-ascii?Q?6F3W9uivb7FSvjjBrta+O+uMQECNI0MJyNd8saW?= =?us-ascii?Q?SzrTlci9IPpova7CVktQHvzZA8L9dXDTaXkDzKd?= =?us-ascii?Q?Fb6B7DJ3Ut8zblB+0p5HA=3D=3D?= To: Kishon Vijay Abraham I , Heiko Stuebner Cc: Jonas Karlman , Vinod Koul , Zheng Yang , Algea Cao , Huicong Xu , linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Huicong Xu Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and not in pixel clock rate. When the hdmiphy clock is configured with the same pixel clock rate using clk_set_rate() the clock framework do not signal the hdmi phy driver to set_rate when switching between 8-bit and Deep Color. This result in pre/post pll not being re-configured when switching between regular 8-bit and Deep Color video formats. Fix this by calling set_rate in power_on to force pre pll re-configuration. Signed-off-by: Huicong Xu Signed-off-by: Jonas Karlman --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c index 3a59a6da0440..3719309ad0d0 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -245,6 +245,7 @@ struct inno_hdmi_phy { struct clk_hw hw; struct clk *phyclk; unsigned long pixclock; + unsigned long tmdsclock; }; struct pre_pll_config { @@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); + inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); + ret = clk_prepare_enable(inno->phyclk); if (ret) return ret; @@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) clk_disable_unprepare(inno->phyclk); + inno->tmdsclock = 0; + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); return 0; @@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", __func__, rate, tmdsclock); + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, } inno->pixclock = rate; + inno->tmdsclock = tmdsclock; return 0; } @@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", __func__, rate, tmdsclock); + if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) + return 0; + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); if (IS_ERR(cfg)) return PTR_ERR(cfg); @@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, } inno->pixclock = rate; + inno->tmdsclock = tmdsclock; return 0; } -- 2.17.1