From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0A2DC2D0E2 for ; Tue, 22 Sep 2020 21:42:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EE3122262 for ; Tue, 22 Sep 2020 21:42:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TeAda9wb" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726674AbgIVVmM (ORCPT ); Tue, 22 Sep 2020 17:42:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726448AbgIVVmM (ORCPT ); Tue, 22 Sep 2020 17:42:12 -0400 Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D44CC061755 for ; Tue, 22 Sep 2020 14:42:12 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id k133so8301022pgc.7 for ; Tue, 22 Sep 2020 14:42:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=OLJ5KR/1OxxJLJPx9bmAWykzUWCEGcGqJ6T8OeFg4qg=; b=TeAda9wbKUarg6AQ6DsJqpj2GKzAMfWMWQU1opYINCKwlR956JkFbl3jaV36Sv8fYa IdyA6z2LIGve7/m0QXhLfDB24/oxvs4Hik0VjD7M0x5HkvP3qbDRhSdc1y7OKAD4XqrR hKE4BCgq+dxhWQfwUbjQ3hYdN4tN5MfCT66UDiwTIIy+Gt9xkjh5AWmlZDN01PUR8gL3 ptSW0t4qUqydF9H2qDArrdGObj9ahuH+fMsN5gvdcyZfYGMVj0ngzbH6RJT3QhawezZQ mxvXVWpup87RSEvkkPt/SqlwYZ5Rgzfa79JO0jE45U/WA+NzoX+BxSCPZKmnkAUvPAeR db1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=OLJ5KR/1OxxJLJPx9bmAWykzUWCEGcGqJ6T8OeFg4qg=; b=MWuRJA/6YyFAwguOcJ530bYESqmGxhgsTfQlxnoHoG5gtFB+dP3OQgaH4+gehKG6uf g/SmMOZFpqDxyK7IA9YOAiuPvqAN8+n3IyFjtwGOPxuD7up46paw6wfEqpk3EXPCaAfe TxghwLE8Ub9a7R0McQQ3thawsPFUM1E1DL4lhrpZjEVn68mE0qnPSWiIVXL2W0rmvIQo vZvPcXrm+8RYINIvdwo1g+W0BJoloBm0gTyEYOAj/eXf/jWmxAaJt1wVa44otea9VZzq XC19JvPWq9h8h+qsJVzZTXZGVfRVQmTawTBJ9+LoBxObGef5zrdXwJLbo1LyvI1sZhk1 uIpQ== X-Gm-Message-State: AOAM531sD8okNuoQ4JsNhDp433x2O/kLnTc1aIbgWEOhteZqZcSGQy9V J554fqo85jJro6qEVXKEtM5NUw== X-Google-Smtp-Source: ABdhPJy8HWX1HLFHXlOa4c9lcmZ9xlC8C4JzdSMlpLH/Yvzq5e+GeNjNaQ80dys1ZoYUInijwIyqqQ== X-Received: by 2002:aa7:9518:0:b029:142:2501:35e3 with SMTP id b24-20020aa795180000b0290142250135e3mr5739712pfp.67.1600810931477; Tue, 22 Sep 2020 14:42:11 -0700 (PDT) Received: from xps15 (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id m14sm15373857pfo.202.2020.09.22.14.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2020 14:42:10 -0700 (PDT) Date: Tue, 22 Sep 2020 15:42:08 -0600 From: Mathieu Poirier To: Tingwei Zhang Cc: Suzuki K Poulose , Alexander Shishkin , Mike Leach , Kim Phillips , Greg Kroah-Hartman , Leo Yan , Randy Dunlap , Russell King , Mian Yousaf Kaukab , tsoni@codeaurora.org, Sai Prakash Ranjan , Mao Jinlong , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v11 09/24] coresight: etm3x: allow etm3x to be built as a module Message-ID: <20200922214208.GA933713@xps15> References: <20200915104116.16789-1-tingwei@codeaurora.org> <20200915104116.16789-10-tingwei@codeaurora.org> <20200915180918.GA3665622@xps15> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200915180918.GA3665622@xps15> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 15, 2020 at 12:09:18PM -0600, Mathieu Poirier wrote: > On Tue, Sep 15, 2020 at 06:41:01PM +0800, Tingwei Zhang wrote: > > From: Kim Phillips > > > > Allow to build coresight-etm3x as a module, for ease of development. > > > > - Kconfig becomes a tristate, to allow =m > > - append -core to source file name to allow module to > > be called coresight-etm3x by the Makefile > > - add an etm_remove function, for module unload > > - add a MODULE_DEVICE_TABLE for autoloading on boot > > - delay advertising the per-cpu etmdrvdata > > - protect etmdrvdata[] by modifying it on relevant CPU > > > > Cc: Mathieu Poirier > > Cc: Leo Yan > > Cc: Alexander Shishkin > > Cc: Randy Dunlap > > Cc: Suzuki K Poulose > > Cc: Greg Kroah-Hartman > > Cc: Russell King > > Signed-off-by: Kim Phillips > > Signed-off-by: Tingwei Zhang > > Reviewed-by: Mike Leach > > --- > > drivers/hwtracing/coresight/Kconfig | 5 +- > > drivers/hwtracing/coresight/Makefile | 5 +- > > ...resight-etm3x.c => coresight-etm3x-core.c} | 148 ++++++++++++++---- > > 3 files changed, 122 insertions(+), 36 deletions(-) > > rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (90%) > > I got tired of waiting for a V12 and Mike has based his work on complex configuration on your patchset. So I did the corrections and applied this set to my tree. With a little luck Greg won't mind the late submission and things will work out fine. You owe me a beer. If Greg accepts my pull request, you owe him one too. Mathieu > > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > > index 6433f835fc97..8fd9fd139cf3 100644 > > --- a/drivers/hwtracing/coresight/Kconfig > > +++ b/drivers/hwtracing/coresight/Kconfig > > @@ -65,7 +65,7 @@ config CORESIGHT_SINK_ETBV10 > > special enhancement or added features. > > > > config CORESIGHT_SOURCE_ETM3X > > - bool "CoreSight Embedded Trace Macrocell 3.x driver" > > + tristate "CoreSight Embedded Trace Macrocell 3.x driver" > > depends on !ARM64 > > select CORESIGHT_LINKS_AND_SINKS > > help > > @@ -74,6 +74,9 @@ config CORESIGHT_SOURCE_ETM3X > > This is primarily useful for instruction level tracing. Depending > > the ETM version data tracing may also be available. > > > > + To compile this driver as a module, choose M here: the > > + module will be called coresight-etm3x. > > + > > config CORESIGHT_SOURCE_ETM4X > > bool "CoreSight Embedded Trace Macrocell 4.x driver" > > depends on ARM64 > > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > > index 19497d1d92bf..86b4648844b4 100644 > > --- a/drivers/hwtracing/coresight/Makefile > > +++ b/drivers/hwtracing/coresight/Makefile > > @@ -11,8 +11,9 @@ obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o > > obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o > > obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ > > coresight-replicator.o > > -obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \ > > - coresight-etm3x-sysfs.o > > +obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o > > +coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \ > > + coresight-etm3x-sysfs.o > > obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ > > coresight-etm4x-sysfs.o > > obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o > > diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > > similarity index 90% > > rename from drivers/hwtracing/coresight/coresight-etm3x.c > > rename to drivers/hwtracing/coresight/coresight-etm3x-core.c > > index bf22dcfd3327..56eba0b5c71f 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm3x.c > > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > > @@ -782,6 +782,42 @@ static void etm_init_trace_id(struct etm_drvdata *drvdata) > > drvdata->traceid = coresight_get_trace_id(drvdata->cpu); > > } > > > > +static int __init etm_hp_setup(void) > > +{ > > + int ret; > > + > > + ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, > > + "arm/coresight:starting", > > + etm_starting_cpu, etm_dying_cpu); > > Indentation problem. > > > + > > + if (ret) > > + return ret; > > + > > + ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, > > + "arm/coresight:online", > > + etm_online_cpu, NULL); > > + > > + /* HP dyn state ID returned in ret on success */ > > + if (ret > 0) { > > + hp_online = ret; > > + return 0; > > + } > > + > > + /* failed dyn state - remove others */ > > + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); > > + > > + return ret; > > +} > > + > > +static void etm_hp_clear(void) > > +{ > > + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); > > + if (hp_online) { > > + cpuhp_remove_state_nocalls(hp_online); > > + hp_online = 0; > > + } > > +} > > + > > static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > { > > int ret; > > @@ -824,38 +860,23 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > return -ENOMEM; > > > > cpus_read_lock(); > > Locking is no longer needed. > > > - etmdrvdata[drvdata->cpu] = drvdata; > > > > if (smp_call_function_single(drvdata->cpu, > > etm_init_arch_data, drvdata, 1)) > > dev_err(dev, "ETM arch init failed\n"); > > > > - if (!etm_count++) { > > - cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, > > - "arm/coresight:starting", > > - etm_starting_cpu, etm_dying_cpu); > > - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, > > - "arm/coresight:online", > > - etm_online_cpu, NULL); > > - if (ret < 0) > > - goto err_arch_supported; > > - hp_online = ret; > > - } > > cpus_read_unlock(); > > > > - if (etm_arch_supported(drvdata->arch) == false) { > > - ret = -EINVAL; > > - goto err_arch_supported; > > - } > > + if (etm_arch_supported(drvdata->arch) == false) > > + return -EINVAL; > > > > etm_init_trace_id(drvdata); > > etm_set_default(&drvdata->config); > > > > pdata = coresight_get_platform_data(dev); > > - if (IS_ERR(pdata)) { > > - ret = PTR_ERR(pdata); > > - goto err_arch_supported; > > - } > > + if (IS_ERR(pdata)) > > + return PTR_ERR(pdata); > > + > > adev->dev.platform_data = pdata; > > > > desc.type = CORESIGHT_DEV_TYPE_SOURCE; > > @@ -865,17 +886,17 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > desc.dev = dev; > > desc.groups = coresight_etm_groups; > > drvdata->csdev = coresight_register(&desc); > > - if (IS_ERR(drvdata->csdev)) { > > - ret = PTR_ERR(drvdata->csdev); > > - goto err_arch_supported; > > - } > > + if (IS_ERR(drvdata->csdev)) > > + return PTR_ERR(drvdata->csdev); > > > > ret = etm_perf_symlink(drvdata->csdev, true); > > if (ret) { > > coresight_unregister(drvdata->csdev); > > - goto err_arch_supported; > > + return ret; > > } > > > > + etmdrvdata[drvdata->cpu] = drvdata; > > + > > pm_runtime_put(&adev->dev); > > dev_info(&drvdata->csdev->dev, > > "%s initialized\n", (char *)coresight_get_uci_data(id)); > > @@ -885,14 +906,40 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > } > > > > return 0; > > +} > > > > -err_arch_supported: > > - if (--etm_count == 0) { > > - cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); > > - if (hp_online) > > - cpuhp_remove_state_nocalls(hp_online); > > - } > > - return ret; > > +static void __exit clear_etmdrvdata(void *info) > > +{ > > + int cpu = *(int *)info; > > + > > + etmdrvdata[cpu] = NULL; > > +} > > + > > +static int __exit etm_remove(struct amba_device *adev) > > +{ > > + struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > > + > > + etm_perf_symlink(drvdata->csdev, false); > > + > > + /* > > + * Taking hotplug lock here to avoid racing between etm_remove and > > + * CPU hotplug call backs. > > + */ > > + cpus_read_lock(); > > + /* > > + * The readers for etmdrvdata[] are CPU hotplug call backs > > + * and PM notification call backs. Change etmdrvdata[i] on > > + * CPU i ensures these call backs has consistent view > > + * inside one call back function. > > + */ > > + if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) > > + etmdrvdata[drvdata->cpu] = NULL; > > + > > + cpus_read_unlock(); > > + > > + coresight_unregister(drvdata->csdev); > > + > > + return 0; > > } > > > > #ifdef CONFIG_PM > > @@ -937,6 +984,8 @@ static const struct amba_id etm_ids[] = { > > { 0, 0}, > > }; > > > > +MODULE_DEVICE_TABLE(amba, etm_ids); > > + > > static struct amba_driver etm_driver = { > > .drv = { > > .name = "coresight-etm3x", > > @@ -945,6 +994,39 @@ static struct amba_driver etm_driver = { > > .suppress_bind_attrs = true, > > }, > > .probe = etm_probe, > > + .remove = etm_remove, > > .id_table = etm_ids, > > }; > > -builtin_amba_driver(etm_driver); > > + > > +static int __init etm_init(void) > > +{ > > + int ret; > > + > > + ret = etm_hp_setup(); > > + > > + /* etm_pm_setup() does its own cleanup - exit on error */ > > Copy/paste error --> s/etm_pm_setup/etm_hp_setup > > > + if (ret) > > + return ret; > > + > > + ret = amba_driver_register(&etm_driver); > > + if (ret) { > > + pr_err("Error registering etm3x driver\n"); > > + etm_hp_clear(); > > + } > > + > > + return ret; > > +} > > + > > +static void __exit etm_exit(void) > > +{ > > + amba_driver_unregister(&etm_driver); > > + etm_hp_clear(); > > +} > > + > > +module_init(etm_init); > > +module_exit(etm_exit); > > + > > +MODULE_AUTHOR("Pratik Patel "); > > +MODULE_AUTHOR("Mathieu Poirier "); > > +MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver"); > > +MODULE_LICENSE("GPL v2"); > > -- > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > > a Linux Foundation Collaborative Project > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4784FC2D0E2 for ; Tue, 22 Sep 2020 21:44:25 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D5AF522262 for ; Tue, 22 Sep 2020 21:44:24 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="1ZqzeGJC"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TeAda9wb" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D5AF522262 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=P4ec9CJuzLRf8POX5wn6ZQa8l5YbbBTRXbnfKh2fglQ=; b=1ZqzeGJCCGS15RBcOkUsHDeGj 7mNuXR5ZbsS2egjep5EptrGmA/1rUudrbu033JWVIS8xRjR6kDeWdJJziw2UBKWkEh3kfHqo8jaGY i5g/3JRcBHCzxDkV1AAo3klzsx0gC1CZZ7fZrFfvWLvbevUcC7zivzcRALSZCxY9/BHo8wFoynPFF jq1ymCaguhtXwcZWRL1lhzjmt1dKvVsInhUb2OpP16jkplO4TjDkJYIpLWvcU1FgnthZ2O3R+YA0C FGo+mqSE2a0n8otS7dzxjM/GyyaI5aGc+bDe/sE7e4E+It4D6ILL1ZQGK/cpxokZSdh6CZqroRu5N en/0AhQdg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKq3G-0004a4-0v; Tue, 22 Sep 2020 21:42:18 +0000 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kKq3D-0004Z9-G8 for linux-arm-kernel@lists.infradead.org; Tue, 22 Sep 2020 21:42:16 +0000 Received: by mail-pg1-x541.google.com with SMTP id u24so2242421pgi.1 for ; Tue, 22 Sep 2020 14:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=OLJ5KR/1OxxJLJPx9bmAWykzUWCEGcGqJ6T8OeFg4qg=; b=TeAda9wbKUarg6AQ6DsJqpj2GKzAMfWMWQU1opYINCKwlR956JkFbl3jaV36Sv8fYa IdyA6z2LIGve7/m0QXhLfDB24/oxvs4Hik0VjD7M0x5HkvP3qbDRhSdc1y7OKAD4XqrR hKE4BCgq+dxhWQfwUbjQ3hYdN4tN5MfCT66UDiwTIIy+Gt9xkjh5AWmlZDN01PUR8gL3 ptSW0t4qUqydF9H2qDArrdGObj9ahuH+fMsN5gvdcyZfYGMVj0ngzbH6RJT3QhawezZQ mxvXVWpup87RSEvkkPt/SqlwYZ5Rgzfa79JO0jE45U/WA+NzoX+BxSCPZKmnkAUvPAeR db1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=OLJ5KR/1OxxJLJPx9bmAWykzUWCEGcGqJ6T8OeFg4qg=; b=b/Lxhu5qDxJnroIGLqp9w7yLFHkbPIkDBZjZ+xGu3P3XgeK8eP4kwWEMk4CAnQ60hw nGwnLfYlxQnvcgk22BmbT7IdcI2BNy77p+YUzyFKpXquA7fzs6Do+Tua4dok2HqpJhHy oy7k481zGjZqF3nBKmR9IOtoMZVhvNPmbddVrU1oWhCWuy0cXuM+0t6aC4RckRIH+EB0 tyjd7qxNdyN85zf1k5Y2c2hpfJ5uLFuLAtvzgP8GNzpDFDehNhcohbFrIFsVNiKDI9GV yEb0PVwGo/l6ZeX2cwjV9wkIevQ7C4d6N1XjVjF/51CxsmA00dedfYcpsH3bkndS4K6d eGHg== X-Gm-Message-State: AOAM531IywtS5Lxthyda4WobffiB91tMw6R2nzeNwHSnv3gI7KucDbnC fQmlzy2W9Z7A2KqqaLasTVthmw== X-Google-Smtp-Source: ABdhPJy8HWX1HLFHXlOa4c9lcmZ9xlC8C4JzdSMlpLH/Yvzq5e+GeNjNaQ80dys1ZoYUInijwIyqqQ== X-Received: by 2002:aa7:9518:0:b029:142:2501:35e3 with SMTP id b24-20020aa795180000b0290142250135e3mr5739712pfp.67.1600810931477; Tue, 22 Sep 2020 14:42:11 -0700 (PDT) Received: from xps15 (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id m14sm15373857pfo.202.2020.09.22.14.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2020 14:42:10 -0700 (PDT) Date: Tue, 22 Sep 2020 15:42:08 -0600 From: Mathieu Poirier To: Tingwei Zhang Subject: Re: [PATCH v11 09/24] coresight: etm3x: allow etm3x to be built as a module Message-ID: <20200922214208.GA933713@xps15> References: <20200915104116.16789-1-tingwei@codeaurora.org> <20200915104116.16789-10-tingwei@codeaurora.org> <20200915180918.GA3665622@xps15> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200915180918.GA3665622@xps15> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200922_174215_558640_DFEC991A X-CRM114-Status: GOOD ( 36.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tsoni@codeaurora.org, Sai Prakash Ranjan , Kim Phillips , Mao Jinlong , Suzuki K Poulose , Alexander Shishkin , Greg Kroah-Hartman , coresight@lists.linaro.org, Randy Dunlap , Mian Yousaf Kaukab , Russell King , linux-kernel@vger.kernel.org, Leo Yan , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 15, 2020 at 12:09:18PM -0600, Mathieu Poirier wrote: > On Tue, Sep 15, 2020 at 06:41:01PM +0800, Tingwei Zhang wrote: > > From: Kim Phillips > > > > Allow to build coresight-etm3x as a module, for ease of development. > > > > - Kconfig becomes a tristate, to allow =m > > - append -core to source file name to allow module to > > be called coresight-etm3x by the Makefile > > - add an etm_remove function, for module unload > > - add a MODULE_DEVICE_TABLE for autoloading on boot > > - delay advertising the per-cpu etmdrvdata > > - protect etmdrvdata[] by modifying it on relevant CPU > > > > Cc: Mathieu Poirier > > Cc: Leo Yan > > Cc: Alexander Shishkin > > Cc: Randy Dunlap > > Cc: Suzuki K Poulose > > Cc: Greg Kroah-Hartman > > Cc: Russell King > > Signed-off-by: Kim Phillips > > Signed-off-by: Tingwei Zhang > > Reviewed-by: Mike Leach > > --- > > drivers/hwtracing/coresight/Kconfig | 5 +- > > drivers/hwtracing/coresight/Makefile | 5 +- > > ...resight-etm3x.c => coresight-etm3x-core.c} | 148 ++++++++++++++---- > > 3 files changed, 122 insertions(+), 36 deletions(-) > > rename drivers/hwtracing/coresight/{coresight-etm3x.c => coresight-etm3x-core.c} (90%) > > I got tired of waiting for a V12 and Mike has based his work on complex configuration on your patchset. So I did the corrections and applied this set to my tree. With a little luck Greg won't mind the late submission and things will work out fine. You owe me a beer. If Greg accepts my pull request, you owe him one too. Mathieu > > diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig > > index 6433f835fc97..8fd9fd139cf3 100644 > > --- a/drivers/hwtracing/coresight/Kconfig > > +++ b/drivers/hwtracing/coresight/Kconfig > > @@ -65,7 +65,7 @@ config CORESIGHT_SINK_ETBV10 > > special enhancement or added features. > > > > config CORESIGHT_SOURCE_ETM3X > > - bool "CoreSight Embedded Trace Macrocell 3.x driver" > > + tristate "CoreSight Embedded Trace Macrocell 3.x driver" > > depends on !ARM64 > > select CORESIGHT_LINKS_AND_SINKS > > help > > @@ -74,6 +74,9 @@ config CORESIGHT_SOURCE_ETM3X > > This is primarily useful for instruction level tracing. Depending > > the ETM version data tracing may also be available. > > > > + To compile this driver as a module, choose M here: the > > + module will be called coresight-etm3x. > > + > > config CORESIGHT_SOURCE_ETM4X > > bool "CoreSight Embedded Trace Macrocell 4.x driver" > > depends on ARM64 > > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > > index 19497d1d92bf..86b4648844b4 100644 > > --- a/drivers/hwtracing/coresight/Makefile > > +++ b/drivers/hwtracing/coresight/Makefile > > @@ -11,8 +11,9 @@ obj-$(CONFIG_CORESIGHT_SINK_TPIU) += coresight-tpiu.o > > obj-$(CONFIG_CORESIGHT_SINK_ETBV10) += coresight-etb10.o > > obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-funnel.o \ > > coresight-replicator.o > > -obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o coresight-etm-cp14.o \ > > - coresight-etm3x-sysfs.o > > +obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) += coresight-etm3x.o > > +coresight-etm3x-y := coresight-etm3x-core.o coresight-etm-cp14.o \ > > + coresight-etm3x-sysfs.o > > obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \ > > coresight-etm4x-sysfs.o > > obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o > > diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > > similarity index 90% > > rename from drivers/hwtracing/coresight/coresight-etm3x.c > > rename to drivers/hwtracing/coresight/coresight-etm3x-core.c > > index bf22dcfd3327..56eba0b5c71f 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm3x.c > > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > > @@ -782,6 +782,42 @@ static void etm_init_trace_id(struct etm_drvdata *drvdata) > > drvdata->traceid = coresight_get_trace_id(drvdata->cpu); > > } > > > > +static int __init etm_hp_setup(void) > > +{ > > + int ret; > > + > > + ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, > > + "arm/coresight:starting", > > + etm_starting_cpu, etm_dying_cpu); > > Indentation problem. > > > + > > + if (ret) > > + return ret; > > + > > + ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, > > + "arm/coresight:online", > > + etm_online_cpu, NULL); > > + > > + /* HP dyn state ID returned in ret on success */ > > + if (ret > 0) { > > + hp_online = ret; > > + return 0; > > + } > > + > > + /* failed dyn state - remove others */ > > + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); > > + > > + return ret; > > +} > > + > > +static void etm_hp_clear(void) > > +{ > > + cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); > > + if (hp_online) { > > + cpuhp_remove_state_nocalls(hp_online); > > + hp_online = 0; > > + } > > +} > > + > > static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > { > > int ret; > > @@ -824,38 +860,23 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > return -ENOMEM; > > > > cpus_read_lock(); > > Locking is no longer needed. > > > - etmdrvdata[drvdata->cpu] = drvdata; > > > > if (smp_call_function_single(drvdata->cpu, > > etm_init_arch_data, drvdata, 1)) > > dev_err(dev, "ETM arch init failed\n"); > > > > - if (!etm_count++) { > > - cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING, > > - "arm/coresight:starting", > > - etm_starting_cpu, etm_dying_cpu); > > - ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN, > > - "arm/coresight:online", > > - etm_online_cpu, NULL); > > - if (ret < 0) > > - goto err_arch_supported; > > - hp_online = ret; > > - } > > cpus_read_unlock(); > > > > - if (etm_arch_supported(drvdata->arch) == false) { > > - ret = -EINVAL; > > - goto err_arch_supported; > > - } > > + if (etm_arch_supported(drvdata->arch) == false) > > + return -EINVAL; > > > > etm_init_trace_id(drvdata); > > etm_set_default(&drvdata->config); > > > > pdata = coresight_get_platform_data(dev); > > - if (IS_ERR(pdata)) { > > - ret = PTR_ERR(pdata); > > - goto err_arch_supported; > > - } > > + if (IS_ERR(pdata)) > > + return PTR_ERR(pdata); > > + > > adev->dev.platform_data = pdata; > > > > desc.type = CORESIGHT_DEV_TYPE_SOURCE; > > @@ -865,17 +886,17 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > desc.dev = dev; > > desc.groups = coresight_etm_groups; > > drvdata->csdev = coresight_register(&desc); > > - if (IS_ERR(drvdata->csdev)) { > > - ret = PTR_ERR(drvdata->csdev); > > - goto err_arch_supported; > > - } > > + if (IS_ERR(drvdata->csdev)) > > + return PTR_ERR(drvdata->csdev); > > > > ret = etm_perf_symlink(drvdata->csdev, true); > > if (ret) { > > coresight_unregister(drvdata->csdev); > > - goto err_arch_supported; > > + return ret; > > } > > > > + etmdrvdata[drvdata->cpu] = drvdata; > > + > > pm_runtime_put(&adev->dev); > > dev_info(&drvdata->csdev->dev, > > "%s initialized\n", (char *)coresight_get_uci_data(id)); > > @@ -885,14 +906,40 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > > } > > > > return 0; > > +} > > > > -err_arch_supported: > > - if (--etm_count == 0) { > > - cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); > > - if (hp_online) > > - cpuhp_remove_state_nocalls(hp_online); > > - } > > - return ret; > > +static void __exit clear_etmdrvdata(void *info) > > +{ > > + int cpu = *(int *)info; > > + > > + etmdrvdata[cpu] = NULL; > > +} > > + > > +static int __exit etm_remove(struct amba_device *adev) > > +{ > > + struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev); > > + > > + etm_perf_symlink(drvdata->csdev, false); > > + > > + /* > > + * Taking hotplug lock here to avoid racing between etm_remove and > > + * CPU hotplug call backs. > > + */ > > + cpus_read_lock(); > > + /* > > + * The readers for etmdrvdata[] are CPU hotplug call backs > > + * and PM notification call backs. Change etmdrvdata[i] on > > + * CPU i ensures these call backs has consistent view > > + * inside one call back function. > > + */ > > + if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) > > + etmdrvdata[drvdata->cpu] = NULL; > > + > > + cpus_read_unlock(); > > + > > + coresight_unregister(drvdata->csdev); > > + > > + return 0; > > } > > > > #ifdef CONFIG_PM > > @@ -937,6 +984,8 @@ static const struct amba_id etm_ids[] = { > > { 0, 0}, > > }; > > > > +MODULE_DEVICE_TABLE(amba, etm_ids); > > + > > static struct amba_driver etm_driver = { > > .drv = { > > .name = "coresight-etm3x", > > @@ -945,6 +994,39 @@ static struct amba_driver etm_driver = { > > .suppress_bind_attrs = true, > > }, > > .probe = etm_probe, > > + .remove = etm_remove, > > .id_table = etm_ids, > > }; > > -builtin_amba_driver(etm_driver); > > + > > +static int __init etm_init(void) > > +{ > > + int ret; > > + > > + ret = etm_hp_setup(); > > + > > + /* etm_pm_setup() does its own cleanup - exit on error */ > > Copy/paste error --> s/etm_pm_setup/etm_hp_setup > > > + if (ret) > > + return ret; > > + > > + ret = amba_driver_register(&etm_driver); > > + if (ret) { > > + pr_err("Error registering etm3x driver\n"); > > + etm_hp_clear(); > > + } > > + > > + return ret; > > +} > > + > > +static void __exit etm_exit(void) > > +{ > > + amba_driver_unregister(&etm_driver); > > + etm_hp_clear(); > > +} > > + > > +module_init(etm_init); > > +module_exit(etm_exit); > > + > > +MODULE_AUTHOR("Pratik Patel "); > > +MODULE_AUTHOR("Mathieu Poirier "); > > +MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver"); > > +MODULE_LICENSE("GPL v2"); > > -- > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > > a Linux Foundation Collaborative Project > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel