From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org
Cc: ak@linux.intel.com, asit.k.mallick@intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH 3/3] perf/x86/intel/uncore: Reduce the number of CBOX counters
Date: Fri, 25 Sep 2020 06:49:05 -0700 [thread overview]
Message-ID: <20200925134905.8839-3-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20200925134905.8839-1-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
An oops is triggered by the fuzzy test.
[ 327.853081] unchecked MSR access error: RDMSR from 0x70c at rIP:
0xffffffffc082c820 (uncore_msr_read_counter+0x10/0x50 [intel_uncore])
[ 327.853083] Call Trace:
[ 327.853085] <IRQ>
[ 327.853089] uncore_pmu_event_start+0x85/0x170 [intel_uncore]
[ 327.853093] uncore_pmu_event_add+0x1a4/0x410 [intel_uncore]
[ 327.853097] ? event_sched_in.isra.118+0xca/0x240
There are 2 GP counters for each CBOX, but the current code claims 4
counters. Accessing the invalid registers triggers the oops.
Fixes: 6e394376ee89 ("perf/x86/intel/uncore: Add Intel Icelake uncore support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/uncore_snb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index 2bdfcf80b434..de3d9621b694 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -325,7 +325,7 @@ static struct intel_uncore_ops icl_uncore_msr_ops = {
static struct intel_uncore_type icl_uncore_cbox = {
.name = "cbox",
- .num_counters = 4,
+ .num_counters = 2,
.perf_ctr_bits = 44,
.perf_ctr = ICL_UNC_CBO_0_PER_CTR0,
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
--
2.17.1
next prev parent reply other threads:[~2020-09-25 13:50 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-25 13:49 [PATCH 1/3] perf/x86/intel/uncore: Split the Ice Lake and Tiger Lake MSR uncore support kan.liang
2020-09-25 13:49 ` [PATCH 2/3] perf/x86/intel/uncore: Update Ice Lake uncore units kan.liang
2020-09-30 18:58 ` [tip: perf/core] " tip-bot2 for Kan Liang
2020-09-25 13:49 ` kan.liang [this message]
2020-09-30 18:58 ` [tip: perf/core] perf/x86/intel/uncore: Reduce the number of CBOX counters tip-bot2 for Kan Liang
2020-09-30 18:58 ` [tip: perf/core] perf/x86/intel/uncore: Split the Ice Lake and Tiger Lake MSR uncore support tip-bot2 for Kan Liang
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