From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B328C2D0A8 for ; Sat, 26 Sep 2020 13:46:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00DBB21527 for ; Sat, 26 Sep 2020 13:46:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726183AbgIZNqs (ORCPT ); Sat, 26 Sep 2020 09:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725208AbgIZNqs (ORCPT ); Sat, 26 Sep 2020 09:46:48 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1050AC0613CE for ; Sat, 26 Sep 2020 06:46:48 -0700 (PDT) Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kMAXC-0001gX-AZ; Sat, 26 Sep 2020 15:46:42 +0200 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1kMAXB-00020o-8F; Sat, 26 Sep 2020 15:46:41 +0200 Date: Sat, 26 Sep 2020 15:46:41 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Marco Felsch Cc: thierry.reding@gmail.com, lee.jones@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, Anson.Huang@nxp.com, michal.vokac@ysoft.com, l.majewski@majess.pl, linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@pengutronix.de Subject: Re: [PATCH v2 2/5] pwm: imx27: move constant PWMCR register values into probe Message-ID: <20200926134641.fkqhoez4j3fktbnh@pengutronix.de> References: <20200925155330.32301-1-m.felsch@pengutronix.de> <20200925155330.32301-3-m.felsch@pengutronix.de> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="wnokfvuhnuqgefeb" Content-Disposition: inline In-Reply-To: <20200925155330.32301-3-m.felsch@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-pwm@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org --wnokfvuhnuqgefeb Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 25, 2020 at 05:53:27PM +0200, Marco Felsch wrote: > The STOPEN, DOZEN, WAITEN, DBGEN and the CLKSRC bit values never change. > So it should be safe to move this bit settings into probe() and change > only the necessary bits during apply(). Therefore I added the > pwm_imx27_update_bits() helper. >=20 > Signed-off-by: Marco Felsch > --- > v2: > - drop software reset from the logic > - fix setting STOPEN, DOZEN, WAITEN and DBGEN bits in case the pwm is > already enabled >=20 > drivers/pwm/pwm-imx27.c | 37 ++++++++++++++++++++++++++++--------- > 1 file changed, 28 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c > index 7edac4ac6395..b761764b8375 100644 > --- a/drivers/pwm/pwm-imx27.c > +++ b/drivers/pwm/pwm-imx27.c > @@ -96,6 +96,16 @@ struct pwm_imx27_chip { > =20 > #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip= , chip) > =20 > +static void pwm_imx27_update_bits(void __iomem *reg, u32 mask, u32 val) > +{ > + u32 tmp; > + > + tmp =3D readl(reg); > + tmp &=3D ~mask; > + tmp |=3D val & mask; > + return writel(tmp, reg); > +} > + > static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx) > { > int ret; > @@ -221,7 +231,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, > unsigned long long c; > unsigned long long clkrate; > int ret; > - u32 cr; > + u32 cr, mask; > =20 > ret =3D pwm_imx27_clk_prepare_enable(imx); > if (ret) > @@ -267,10 +277,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, > */ > imx->duty_cycle =3D duty_cycles; > =20 > - cr =3D MX3_PWMCR_PRESCALER_SET(prescale) | > - MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | > - FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) | > - MX3_PWMCR_DBGEN; > + cr =3D MX3_PWMCR_PRESCALER_SET(prescale); > =20 > if (state->polarity =3D=3D PWM_POLARITY_INVERSED) > cr |=3D FIELD_PREP(MX3_PWMCR_POUTC, > @@ -279,7 +286,9 @@ static int pwm_imx27_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, > if (state->enabled) > cr |=3D MX3_PWMCR_EN; > =20 > - writel(cr, imx->mmio_base + MX3_PWMCR); > + mask =3D MX3_PWMCR_PRESCALER | MX3_PWMCR_POUTC | MX3_PWMCR_EN; > + > + pwm_imx27_update_bits(imx->mmio_base + MX3_PWMCR, mask, cr); > =20 > if (imx->enabled !=3D state->enabled) { > if (state->enabled) { > @@ -314,7 +323,7 @@ static int pwm_imx27_probe(struct platform_device *pd= ev) > { > struct pwm_imx27_chip *imx; > int ret; > - u32 pwmcr; > + u32 pwmcr, mask; > =20 > imx =3D devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); > if (imx =3D=3D NULL) > @@ -361,10 +370,20 @@ static int pwm_imx27_probe(struct platform_device *= pdev) > if (ret) > return ret; > =20 > - /* keep clks on if pwm is running */ > + mask =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | > + MX3_PWMCR_DBGEN; > + pwmcr =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | > + MX3_PWMCR_DBGEN; > + pwm_imx27_update_bits(imx->mmio_base + MX3_PWMCR, mask, pwmcr); > + > + /* keep clks on and clk settings unchanged if pwm is running */ > pwmcr =3D readl(imx->mmio_base + MX3_PWMCR); > - if (!(pwmcr & MX3_PWMCR_EN)) > + if (!(pwmcr & MX3_PWMCR_EN)) { > + mask =3D MX3_PWMCR_CLKSRC; > + pwmcr =3D FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH); > + pwm_imx27_update_bits(imx->mmio_base + MX3_PWMCR, mask, pwmcr); > pwm_imx27_clk_disable_unprepare(imx); > + } You're doing more register accesses here than necessary, that is 3 reads and two writes while one read and (maybe) one write would be enough. (Though this doesn't work if you want to use the pwm_imx27_update_bits helper.) You'd need to do something like: val =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | MX3_PWMCR_= DBGEN; mask =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | MX3_PWMCR= _DBGEN; pwmcr =3D readl(imx->mmio_base + MX3_PWMCR); if (pwmcr & MX3_PWMCR_EN) { imx->enabled =3D true; } else { val |=3D FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH); mask |=3D MX3_PWMCR_CLKSRC; } pwmcr_new =3D (pwmcr & ~mask) | val; if (pwmcr_new !=3D val) writel(imx->mmio_base + MX3_PWMCR, pwmcr_new); if (!imx->enabled) pwm_imx27_clk_disable_unprepare(imx); Hmm, not sure this is pretty enough to actually recommend this. I let you decide. > return pwmchip_add(&imx->chip); Best regards Uwe --=20 Pengutronix e.K. | Uwe Kleine-K=F6nig | Industrial Linux Solutions | https://www.pengutronix.de/ | --wnokfvuhnuqgefeb Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEfnIqFpAYrP8+dKQLwfwUeK3K7AkFAl9vRj4ACgkQwfwUeK3K 7AlJ4wf/RIgOfPRFMYAH2/MrBtl5qs1r5EsPm7rr2ilfHM7zjsyqkgwuwirRJj9+ yXBQtvdCMeJclVo6QuGOnmepX7PsBHX6TYN+WEqjxtOg6FOOQESq95Ba3BJ3gsTO mTgEE4ZmWZmUwiD/uew7MFpVLfCdzMT3+6sLxGLhT3Ob6HCDUNMp/jZ51qNhDW3Q ivlLvvyuYGuM4oYk4l2iOFLoye6ohsi+Ud0gjcrwA2in1v5p/0bPpdx42cez8Gj5 vAqSdT9fE0Ksi5MD4nKdPkTXpa6WVsGhWdr4IVVGzrNYDTMvwQoH/KStUMimWSXe Mi6OCpV8hbGjz2MA6LwIUeuioilaJQ== =uNjC -----END PGP SIGNATURE----- --wnokfvuhnuqgefeb-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CF06C2D0A8 for ; Sat, 26 Sep 2020 13:48:17 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 23E1921527 for ; Sat, 26 Sep 2020 13:48:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="e/Fo8Wcg" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23E1921527 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type:Cc: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BkWTwN1OMlr3nILdWpplJ8gyMQA7UVhiswNuGyR5lD8=; b=e/Fo8WcgObm1arSoywkN2vwU0 8lNcIZ9zXhQuglwigBLoP1n4xZyChKDa1Jz/+QdqcNe9evigjfUicchEMQ9iLdBlOecli1+n8e/wq szN6OgfBsA1/Z5u4S2apBFC3gi546oJBQajSbCctzyKhSLAeIp1KtP6356cjz70my+Dg+q4SrLVPm 0J0ymmyeKiJ/JRS3cWCH8ffL+AW2WHM6Fh83w2NgaJtYBnWbYtaYu4oXS9wB+A3xUjAx6vLSWGcKv P07o7BAX7w6aTGV9XIj48TQNIplbEExlkMwyHWWR6RmKl9cyqjxf4O2mshP27bRWqCd6J7fxwbxTe y6R3Irbsw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kMAXL-0004bb-Sl; Sat, 26 Sep 2020 13:46:51 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kMAXJ-0004av-C5 for linux-arm-kernel@lists.infradead.org; Sat, 26 Sep 2020 13:46:50 +0000 Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kMAXC-0001gX-AZ; Sat, 26 Sep 2020 15:46:42 +0200 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1kMAXB-00020o-8F; Sat, 26 Sep 2020 15:46:41 +0200 Date: Sat, 26 Sep 2020 15:46:41 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Marco Felsch Subject: Re: [PATCH v2 2/5] pwm: imx27: move constant PWMCR register values into probe Message-ID: <20200926134641.fkqhoez4j3fktbnh@pengutronix.de> References: <20200925155330.32301-1-m.felsch@pengutronix.de> <20200925155330.32301-3-m.felsch@pengutronix.de> MIME-Version: 1.0 In-Reply-To: <20200925155330.32301-3-m.felsch@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200926_094649_463264_AFEADCBB X-CRM114-Status: GOOD ( 28.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, michal.vokac@ysoft.com, kernel@pengutronix.de, Anson.Huang@nxp.com, lee.jones@linaro.org, s.hauer@pengutronix.de, thierry.reding@gmail.com, linux-imx@nxp.com, festevam@gmail.com, shawnguo@kernel.org, l.majewski@majess.pl, linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============3058668625470356829==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============3058668625470356829== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="wnokfvuhnuqgefeb" Content-Disposition: inline --wnokfvuhnuqgefeb Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 25, 2020 at 05:53:27PM +0200, Marco Felsch wrote: > The STOPEN, DOZEN, WAITEN, DBGEN and the CLKSRC bit values never change. > So it should be safe to move this bit settings into probe() and change > only the necessary bits during apply(). Therefore I added the > pwm_imx27_update_bits() helper. >=20 > Signed-off-by: Marco Felsch > --- > v2: > - drop software reset from the logic > - fix setting STOPEN, DOZEN, WAITEN and DBGEN bits in case the pwm is > already enabled >=20 > drivers/pwm/pwm-imx27.c | 37 ++++++++++++++++++++++++++++--------- > 1 file changed, 28 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-imx27.c b/drivers/pwm/pwm-imx27.c > index 7edac4ac6395..b761764b8375 100644 > --- a/drivers/pwm/pwm-imx27.c > +++ b/drivers/pwm/pwm-imx27.c > @@ -96,6 +96,16 @@ struct pwm_imx27_chip { > =20 > #define to_pwm_imx27_chip(chip) container_of(chip, struct pwm_imx27_chip= , chip) > =20 > +static void pwm_imx27_update_bits(void __iomem *reg, u32 mask, u32 val) > +{ > + u32 tmp; > + > + tmp =3D readl(reg); > + tmp &=3D ~mask; > + tmp |=3D val & mask; > + return writel(tmp, reg); > +} > + > static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx) > { > int ret; > @@ -221,7 +231,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, > unsigned long long c; > unsigned long long clkrate; > int ret; > - u32 cr; > + u32 cr, mask; > =20 > ret =3D pwm_imx27_clk_prepare_enable(imx); > if (ret) > @@ -267,10 +277,7 @@ static int pwm_imx27_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, > */ > imx->duty_cycle =3D duty_cycles; > =20 > - cr =3D MX3_PWMCR_PRESCALER_SET(prescale) | > - MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | > - FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) | > - MX3_PWMCR_DBGEN; > + cr =3D MX3_PWMCR_PRESCALER_SET(prescale); > =20 > if (state->polarity =3D=3D PWM_POLARITY_INVERSED) > cr |=3D FIELD_PREP(MX3_PWMCR_POUTC, > @@ -279,7 +286,9 @@ static int pwm_imx27_apply(struct pwm_chip *chip, str= uct pwm_device *pwm, > if (state->enabled) > cr |=3D MX3_PWMCR_EN; > =20 > - writel(cr, imx->mmio_base + MX3_PWMCR); > + mask =3D MX3_PWMCR_PRESCALER | MX3_PWMCR_POUTC | MX3_PWMCR_EN; > + > + pwm_imx27_update_bits(imx->mmio_base + MX3_PWMCR, mask, cr); > =20 > if (imx->enabled !=3D state->enabled) { > if (state->enabled) { > @@ -314,7 +323,7 @@ static int pwm_imx27_probe(struct platform_device *pd= ev) > { > struct pwm_imx27_chip *imx; > int ret; > - u32 pwmcr; > + u32 pwmcr, mask; > =20 > imx =3D devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL); > if (imx =3D=3D NULL) > @@ -361,10 +370,20 @@ static int pwm_imx27_probe(struct platform_device *= pdev) > if (ret) > return ret; > =20 > - /* keep clks on if pwm is running */ > + mask =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | > + MX3_PWMCR_DBGEN; > + pwmcr =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | > + MX3_PWMCR_DBGEN; > + pwm_imx27_update_bits(imx->mmio_base + MX3_PWMCR, mask, pwmcr); > + > + /* keep clks on and clk settings unchanged if pwm is running */ > pwmcr =3D readl(imx->mmio_base + MX3_PWMCR); > - if (!(pwmcr & MX3_PWMCR_EN)) > + if (!(pwmcr & MX3_PWMCR_EN)) { > + mask =3D MX3_PWMCR_CLKSRC; > + pwmcr =3D FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH); > + pwm_imx27_update_bits(imx->mmio_base + MX3_PWMCR, mask, pwmcr); > pwm_imx27_clk_disable_unprepare(imx); > + } You're doing more register accesses here than necessary, that is 3 reads and two writes while one read and (maybe) one write would be enough. (Though this doesn't work if you want to use the pwm_imx27_update_bits helper.) You'd need to do something like: val =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | MX3_PWMCR_= DBGEN; mask =3D MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | MX3_PWMCR= _DBGEN; pwmcr =3D readl(imx->mmio_base + MX3_PWMCR); if (pwmcr & MX3_PWMCR_EN) { imx->enabled =3D true; } else { val |=3D FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH); mask |=3D MX3_PWMCR_CLKSRC; } pwmcr_new =3D (pwmcr & ~mask) | val; if (pwmcr_new !=3D val) writel(imx->mmio_base + MX3_PWMCR, pwmcr_new); if (!imx->enabled) pwm_imx27_clk_disable_unprepare(imx); Hmm, not sure this is pretty enough to actually recommend this. I let you decide. > return pwmchip_add(&imx->chip); Best regards Uwe --=20 Pengutronix e.K. | Uwe Kleine-K=F6nig | Industrial Linux Solutions | https://www.pengutronix.de/ | --wnokfvuhnuqgefeb Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEfnIqFpAYrP8+dKQLwfwUeK3K7AkFAl9vRj4ACgkQwfwUeK3K 7AlJ4wf/RIgOfPRFMYAH2/MrBtl5qs1r5EsPm7rr2ilfHM7zjsyqkgwuwirRJj9+ yXBQtvdCMeJclVo6QuGOnmepX7PsBHX6TYN+WEqjxtOg6FOOQESq95Ba3BJ3gsTO mTgEE4ZmWZmUwiD/uew7MFpVLfCdzMT3+6sLxGLhT3Ob6HCDUNMp/jZ51qNhDW3Q ivlLvvyuYGuM4oYk4l2iOFLoye6ohsi+Ud0gjcrwA2in1v5p/0bPpdx42cez8Gj5 vAqSdT9fE0Ksi5MD4nKdPkTXpa6WVsGhWdr4IVVGzrNYDTMvwQoH/KStUMimWSXe Mi6OCpV8hbGjz2MA6LwIUeuioilaJQ== =uNjC -----END PGP SIGNATURE----- --wnokfvuhnuqgefeb-- --===============3058668625470356829== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============3058668625470356829==--