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* [PATCH 0/2] drm/i915/jsl: Update JasperLake Voltage swing table
@ 2020-09-28  8:09 ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

Patch series covers following things:

1. Split and differentiate between EhlkhartLake and
   JasperLake platfrom
2. Update voltage swing table for eDP on JasperLake platform
BSpec: 21257

Tejas Upadhyay (2):
  drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  drm/i915/edp/jsl: Update vswing table for HBR and HBR2

 drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h          |  4 +-
 drivers/gpu/drm/i915/i915_pci.c          |  9 ++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 include/drm/i915_pciids.h                |  9 ++--
 6 files changed, 84 insertions(+), 7 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 58+ messages in thread
* [PATCH 0/2] drm/i915/jsl: Update JasperLake Voltage swing table
@ 2020-09-28  8:09 ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

Patch series covers following things:

1. Split and differentiate between EhlkhartLake and
   JasperLake platfrom
2. Update voltage swing table for eDP on JasperLake platform
BSpec: 21257

Tejas Upadhyay (2):
  drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  drm/i915/edp/jsl: Update vswing table for HBR and HBR2

 drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h          |  4 +-
 drivers/gpu/drm/i915/i915_pci.c          |  9 ++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 include/drm/i915_pciids.h                |  9 ++--
 6 files changed, 84 insertions(+), 7 deletions(-)

-- 
2.25.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* [Intel-gfx] [PATCH 0/2] drm/i915/jsl: Update JasperLake Voltage swing table
@ 2020-09-28  8:09 ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

Patch series covers following things:

1. Split and differentiate between EhlkhartLake and
   JasperLake platfrom
2. Update voltage swing table for eDP on JasperLake platform
BSpec: 21257

Tejas Upadhyay (2):
  drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  drm/i915/edp/jsl: Update vswing table for HBR and HBR2

 drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h          |  4 +-
 drivers/gpu/drm/i915/i915_pci.c          |  9 ++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 include/drm/i915_pciids.h                |  9 ++--
 6 files changed, 84 insertions(+), 7 deletions(-)

-- 
2.25.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28  8:09 ` Tejas Upadhyay
  (?)
@ 2020-09-28  8:09   ` Tejas Upadhyay
  -1 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

Split the basic platform definition, macros, and PCI IDs to
differentiate between EHL and JSL platforms.

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 include/drm/i915_pciids.h                | 9 ++++++---
 5 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72a9449b674e..4f20acebb038 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
+				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
+#define IS_JASPERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 366ddfc8df6b..8690b69fcf33 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
 	.ppgtt_size = 36,
 };
 
+static const struct intel_device_info jsl_info = {
+	GEN11_FEATURES,
+	PLATFORM(INTEL_JASPERLAKE),
+	.require_force_probe = 1,
+	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
+	.ppgtt_size = 36,
+};
+
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
@@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CNL_IDS(&cnl_info),
 	INTEL_ICL_11_IDS(&icl_info),
 	INTEL_EHL_IDS(&ehl_info),
+	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
 	{0, 0, 0}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index adc836f15fde..e67cec8fa2aa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -62,6 +62,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(CANNONLAKE),
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
+	PLATFORM_NAME(JASPERLAKE),
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6a3d607218aa..d92fa041c700 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -79,6 +79,7 @@ enum intel_platform {
 	/* gen11 */
 	INTEL_ICELAKE,
 	INTEL_ELKHARTLAKE,
+	INTEL_JASPERLAKE,
 	/* gen12 */
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..1b5e09cfa11e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -579,15 +579,18 @@
 	INTEL_VGA_DEVICE(0x8A51, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info)
 
-/* EHL/JSL */
+/* EHL */
 #define INTEL_EHL_IDS(info) \
 	INTEL_VGA_DEVICE(0x4500, info),	\
 	INTEL_VGA_DEVICE(0x4571, info), \
 	INTEL_VGA_DEVICE(0x4551, info), \
 	INTEL_VGA_DEVICE(0x4541, info), \
-	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4557, info), \
-	INTEL_VGA_DEVICE(0x4555, info), \
+	INTEL_VGA_DEVICE(0x4555, info)
+
+/* JSL */
+#define INTEL_JSL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4E61, info), \
 	INTEL_VGA_DEVICE(0x4E57, info), \
 	INTEL_VGA_DEVICE(0x4E55, info), \
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 58+ messages in thread
* [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28  8:09   ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

Split the basic platform definition, macros, and PCI IDs to
differentiate between EHL and JSL platforms.

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 include/drm/i915_pciids.h                | 9 ++++++---
 5 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72a9449b674e..4f20acebb038 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
+				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
+#define IS_JASPERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 366ddfc8df6b..8690b69fcf33 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
 	.ppgtt_size = 36,
 };
 
+static const struct intel_device_info jsl_info = {
+	GEN11_FEATURES,
+	PLATFORM(INTEL_JASPERLAKE),
+	.require_force_probe = 1,
+	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
+	.ppgtt_size = 36,
+};
+
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
@@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CNL_IDS(&cnl_info),
 	INTEL_ICL_11_IDS(&icl_info),
 	INTEL_EHL_IDS(&ehl_info),
+	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
 	{0, 0, 0}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index adc836f15fde..e67cec8fa2aa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -62,6 +62,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(CANNONLAKE),
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
+	PLATFORM_NAME(JASPERLAKE),
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6a3d607218aa..d92fa041c700 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -79,6 +79,7 @@ enum intel_platform {
 	/* gen11 */
 	INTEL_ICELAKE,
 	INTEL_ELKHARTLAKE,
+	INTEL_JASPERLAKE,
 	/* gen12 */
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..1b5e09cfa11e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -579,15 +579,18 @@
 	INTEL_VGA_DEVICE(0x8A51, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info)
 
-/* EHL/JSL */
+/* EHL */
 #define INTEL_EHL_IDS(info) \
 	INTEL_VGA_DEVICE(0x4500, info),	\
 	INTEL_VGA_DEVICE(0x4571, info), \
 	INTEL_VGA_DEVICE(0x4551, info), \
 	INTEL_VGA_DEVICE(0x4541, info), \
-	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4557, info), \
-	INTEL_VGA_DEVICE(0x4555, info), \
+	INTEL_VGA_DEVICE(0x4555, info)
+
+/* JSL */
+#define INTEL_JSL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4E61, info), \
 	INTEL_VGA_DEVICE(0x4E57, info), \
 	INTEL_VGA_DEVICE(0x4E55, info), \
-- 
2.25.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 58+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28  8:09   ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

Split the basic platform definition, macros, and PCI IDs to
differentiate between EHL and JSL platforms.

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
 drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 include/drm/i915_pciids.h                | 9 ++++++---
 5 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 72a9449b674e..4f20acebb038 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
 #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
+#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
+				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
+#define IS_JASPERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
 #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
 #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
 #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 366ddfc8df6b..8690b69fcf33 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
 	.ppgtt_size = 36,
 };
 
+static const struct intel_device_info jsl_info = {
+	GEN11_FEATURES,
+	PLATFORM(INTEL_JASPERLAKE),
+	.require_force_probe = 1,
+	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
+	.ppgtt_size = 36,
+};
+
 #define GEN12_FEATURES \
 	GEN11_FEATURES, \
 	GEN(12), \
@@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CNL_IDS(&cnl_info),
 	INTEL_ICL_11_IDS(&icl_info),
 	INTEL_EHL_IDS(&ehl_info),
+	INTEL_JSL_IDS(&jsl_info),
 	INTEL_TGL_12_IDS(&tgl_info),
 	INTEL_RKL_IDS(&rkl_info),
 	{0, 0, 0}
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index adc836f15fde..e67cec8fa2aa 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -62,6 +62,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(CANNONLAKE),
 	PLATFORM_NAME(ICELAKE),
 	PLATFORM_NAME(ELKHARTLAKE),
+	PLATFORM_NAME(JASPERLAKE),
 	PLATFORM_NAME(TIGERLAKE),
 	PLATFORM_NAME(ROCKETLAKE),
 	PLATFORM_NAME(DG1),
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 6a3d607218aa..d92fa041c700 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -79,6 +79,7 @@ enum intel_platform {
 	/* gen11 */
 	INTEL_ICELAKE,
 	INTEL_ELKHARTLAKE,
+	INTEL_JASPERLAKE,
 	/* gen12 */
 	INTEL_TIGERLAKE,
 	INTEL_ROCKETLAKE,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 7eeecb07c9a1..1b5e09cfa11e 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -579,15 +579,18 @@
 	INTEL_VGA_DEVICE(0x8A51, info), \
 	INTEL_VGA_DEVICE(0x8A5D, info)
 
-/* EHL/JSL */
+/* EHL */
 #define INTEL_EHL_IDS(info) \
 	INTEL_VGA_DEVICE(0x4500, info),	\
 	INTEL_VGA_DEVICE(0x4571, info), \
 	INTEL_VGA_DEVICE(0x4551, info), \
 	INTEL_VGA_DEVICE(0x4541, info), \
-	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4557, info), \
-	INTEL_VGA_DEVICE(0x4555, info), \
+	INTEL_VGA_DEVICE(0x4555, info)
+
+/* JSL */
+#define INTEL_JSL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4E61, info), \
 	INTEL_VGA_DEVICE(0x4E57, info), \
 	INTEL_VGA_DEVICE(0x4E55, info), \
-- 
2.25.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 58+ messages in thread
* [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28  8:09 ` Tejas Upadhyay
  (?)
@ 2020-09-28  8:09   ` Tejas Upadhyay
  -1 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

JSL has update in vswing table for eDP

BSpec: 21257
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
 1 file changed, 64 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4d06178cd76c..fa08463bcf2e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
 };
 
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
+						/* NT mV Trans mV db    */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
+	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
+	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
+	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
+	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
+	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
+	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+};
+
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
+						/* NT mV Trans mV db    */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
+	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
+	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
+	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+};
+
 struct icl_mg_phy_ddi_buf_trans {
 	u32 cri_txdeemph_override_11_6;
 	u32 cri_txdeemph_override_5_0;
@@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
 	return icl_mg_phy_ddi_translations_rbr_hbr;
 }
-
 static const struct cnl_ddi_buf_trans *
 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
@@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	}
 }
 
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+			int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	switch (type) {
+	case INTEL_OUTPUT_HDMI:
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+		return icl_combo_phy_ddi_translations_hdmi;
+	case INTEL_OUTPUT_EDP:
+		if (dev_priv->vbt.edp.low_vswing) {
+			if (rate > 270000) {
+				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
+				return jsl_combo_phy_ddi_translations_edp_hbr2;
+			} else {
+				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
+				return jsl_combo_phy_ddi_translations_edp_hbr;
+			}
+		}
+		/* fall through */
+	default:
+		/* All combo DP and eDP ports that do not support low_vswing */
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+		return icl_combo_phy_ddi_translations_dp_hbr2;
+	}
+}
+
 static const struct cnl_ddi_buf_trans *
 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
@@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 			tgl_get_dkl_buf_trans(encoder, encoder->type,
 					      intel_dp->link_rate, &n_entries);
 	} else if (INTEL_GEN(dev_priv) == 11) {
-		if (IS_ELKHARTLAKE(dev_priv))
+		if (IS_JASPERLAKE(dev_priv))
+			jsl_get_combo_buf_trans(encoder, encoder->type,
+					intel_dp->link_rate, &n_entries);
+		else if (IS_ELKHARTLAKE(dev_priv))
 			ehl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+					intel_dp->link_rate, &n_entries);
 		else if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(encoder, encoder->type,
 						intel_dp->link_rate, &n_entries);
@@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	if (INTEL_GEN(dev_priv) >= 12)
 		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
 							   &n_entries);
+	else if (IS_JASPERLAKE(dev_priv))
+		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
+							   &n_entries);
 	else if (IS_ELKHARTLAKE(dev_priv))
 		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
 							   &n_entries);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 58+ messages in thread
* [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28  8:09   ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

JSL has update in vswing table for eDP

BSpec: 21257
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
 1 file changed, 64 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4d06178cd76c..fa08463bcf2e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
 };
 
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
+						/* NT mV Trans mV db    */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
+	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
+	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
+	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
+	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
+	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
+	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+};
+
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
+						/* NT mV Trans mV db    */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
+	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
+	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
+	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+};
+
 struct icl_mg_phy_ddi_buf_trans {
 	u32 cri_txdeemph_override_11_6;
 	u32 cri_txdeemph_override_5_0;
@@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
 	return icl_mg_phy_ddi_translations_rbr_hbr;
 }
-
 static const struct cnl_ddi_buf_trans *
 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
@@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	}
 }
 
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+			int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	switch (type) {
+	case INTEL_OUTPUT_HDMI:
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+		return icl_combo_phy_ddi_translations_hdmi;
+	case INTEL_OUTPUT_EDP:
+		if (dev_priv->vbt.edp.low_vswing) {
+			if (rate > 270000) {
+				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
+				return jsl_combo_phy_ddi_translations_edp_hbr2;
+			} else {
+				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
+				return jsl_combo_phy_ddi_translations_edp_hbr;
+			}
+		}
+		/* fall through */
+	default:
+		/* All combo DP and eDP ports that do not support low_vswing */
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+		return icl_combo_phy_ddi_translations_dp_hbr2;
+	}
+}
+
 static const struct cnl_ddi_buf_trans *
 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
@@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 			tgl_get_dkl_buf_trans(encoder, encoder->type,
 					      intel_dp->link_rate, &n_entries);
 	} else if (INTEL_GEN(dev_priv) == 11) {
-		if (IS_ELKHARTLAKE(dev_priv))
+		if (IS_JASPERLAKE(dev_priv))
+			jsl_get_combo_buf_trans(encoder, encoder->type,
+					intel_dp->link_rate, &n_entries);
+		else if (IS_ELKHARTLAKE(dev_priv))
 			ehl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+					intel_dp->link_rate, &n_entries);
 		else if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(encoder, encoder->type,
 						intel_dp->link_rate, &n_entries);
@@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	if (INTEL_GEN(dev_priv) >= 12)
 		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
 							   &n_entries);
+	else if (IS_JASPERLAKE(dev_priv))
+		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
+							   &n_entries);
 	else if (IS_ELKHARTLAKE(dev_priv))
 		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
 							   &n_entries);
-- 
2.25.1

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 58+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28  8:09   ` Tejas Upadhyay
  0 siblings, 0 replies; 58+ messages in thread
From: Tejas Upadhyay @ 2020-09-28  8:09 UTC (permalink / raw)
  To: rodrigo.vivi, airlied, daniel, intel-gfx, dri-devel,
	linux-kernel, james.ausmus, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

JSL has update in vswing table for eDP

BSpec: 21257
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
 1 file changed, 64 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4d06178cd76c..fa08463bcf2e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
 };
 
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
+						/* NT mV Trans mV db    */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
+	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
+	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
+	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
+	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
+	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
+	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+};
+
+static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
+						/* NT mV Trans mV db    */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
+	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
+	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
+	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
+	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
+	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
+	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
+};
+
 struct icl_mg_phy_ddi_buf_trans {
 	u32 cri_txdeemph_override_11_6;
 	u32 cri_txdeemph_override_5_0;
@@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
 	return icl_mg_phy_ddi_translations_rbr_hbr;
 }
-
 static const struct cnl_ddi_buf_trans *
 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
@@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 	}
 }
 
+static const struct cnl_ddi_buf_trans *
+jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
+			int *n_entries)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+	switch (type) {
+	case INTEL_OUTPUT_HDMI:
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
+		return icl_combo_phy_ddi_translations_hdmi;
+	case INTEL_OUTPUT_EDP:
+		if (dev_priv->vbt.edp.low_vswing) {
+			if (rate > 270000) {
+				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
+				return jsl_combo_phy_ddi_translations_edp_hbr2;
+			} else {
+				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
+				return jsl_combo_phy_ddi_translations_edp_hbr;
+			}
+		}
+		/* fall through */
+	default:
+		/* All combo DP and eDP ports that do not support low_vswing */
+		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
+		return icl_combo_phy_ddi_translations_dp_hbr2;
+	}
+}
+
 static const struct cnl_ddi_buf_trans *
 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
 			int *n_entries)
@@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
 			tgl_get_dkl_buf_trans(encoder, encoder->type,
 					      intel_dp->link_rate, &n_entries);
 	} else if (INTEL_GEN(dev_priv) == 11) {
-		if (IS_ELKHARTLAKE(dev_priv))
+		if (IS_JASPERLAKE(dev_priv))
+			jsl_get_combo_buf_trans(encoder, encoder->type,
+					intel_dp->link_rate, &n_entries);
+		else if (IS_ELKHARTLAKE(dev_priv))
 			ehl_get_combo_buf_trans(encoder, encoder->type,
-						intel_dp->link_rate, &n_entries);
+					intel_dp->link_rate, &n_entries);
 		else if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(encoder, encoder->type,
 						intel_dp->link_rate, &n_entries);
@@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
 	if (INTEL_GEN(dev_priv) >= 12)
 		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
 							   &n_entries);
+	else if (IS_JASPERLAKE(dev_priv))
+		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
+							   &n_entries);
 	else if (IS_ELKHARTLAKE(dev_priv))
 		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
 							   &n_entries);
-- 
2.25.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 58+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/jsl: Update JasperLake Voltage swing table
  2020-09-28  8:09 ` Tejas Upadhyay
                   ` (3 preceding siblings ...)
  (?)
@ 2020-09-28  8:51 ` Patchwork
  -1 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2020-09-28  8:51 UTC (permalink / raw)
  To: Tejas Upadhyay; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/jsl: Update JasperLake Voltage swing table
URL   : https://patchwork.freedesktop.org/series/82150/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7785c9b4e203 drm/i915/jsl: Split EHL/JSL platform info and PCI ids
-:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#20: FILE: drivers/gpu/drm/i915/i915_drv.h:1420:
+#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
+				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))

-:98: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#98: FILE: include/drm/i915_pciids.h:592:
+#define INTEL_JSL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4E61, info), \
 	INTEL_VGA_DEVICE(0x4E57, info), \
 	INTEL_VGA_DEVICE(0x4E55, info), \

-:98: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#98: FILE: include/drm/i915_pciids.h:592:
+#define INTEL_JSL_IDS(info) \
+	INTEL_VGA_DEVICE(0x4E71, info), \
 	INTEL_VGA_DEVICE(0x4E61, info), \
 	INTEL_VGA_DEVICE(0x4E57, info), \
 	INTEL_VGA_DEVICE(0x4E55, info), \

total: 1 errors, 0 warnings, 2 checks, 66 lines checked
07ca5d2ec781 drm/i915/edp/jsl: Update vswing table for HBR and HBR2
-:77: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#77: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1143:
+				return jsl_combo_phy_ddi_translations_edp_hbr2;
+			} else {

-:82: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#82: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1148:
+		/* fall through */

-:100: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#100: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:2325:
+			jsl_get_combo_buf_trans(encoder, encoder->type,
+					intel_dp->link_rate, &n_entries);

total: 0 errors, 2 warnings, 1 checks, 98 lines checked


_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/jsl: Update JasperLake Voltage swing table
  2020-09-28  8:09 ` Tejas Upadhyay
                   ` (4 preceding siblings ...)
  (?)
@ 2020-09-28  8:52 ` Patchwork
  -1 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2020-09-28  8:52 UTC (permalink / raw)
  To: Tejas Upadhyay; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/jsl: Update JasperLake Voltage swing table
URL   : https://patchwork.freedesktop.org/series/82150/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1311:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/jsl: Update JasperLake Voltage swing table
  2020-09-28  8:09 ` Tejas Upadhyay
                   ` (5 preceding siblings ...)
  (?)
@ 2020-09-28  9:13 ` Patchwork
  -1 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2020-09-28  9:13 UTC (permalink / raw)
  To: Tejas Upadhyay; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 5831 bytes --]

== Series Details ==

Series: drm/i915/jsl: Update JasperLake Voltage swing table
URL   : https://patchwork.freedesktop.org/series/82150/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_9061 -> Patchwork_18580
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/index.html

Known issues
------------

  Here are the changes found in Patchwork_18580 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-tgl-u2:          [PASS][1] -> [DMESG-WARN][2] ([i915#1982] / [k.org#205379])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-tgl-u2/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-tgl-u2/igt@i915_module_load@reload.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-icl-u2:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - {fi-tgl-dsi}:       [DMESG-WARN][5] ([i915#1982] / [k.org#205379]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-tgl-dsi/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-tgl-dsi/igt@i915_module_load@reload.html

  * igt@kms_busy@basic@flip:
    - fi-kbl-x1275:       [DMESG-WARN][7] ([i915#62] / [i915#92] / [i915#95]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-kbl-x1275/igt@kms_busy@basic@flip.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-kbl-x1275/igt@kms_busy@basic@flip.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-byt-j1900:       [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-icl-u2:          [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - {fi-tgl-dsi}:       [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-tgl-dsi/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-tgl-dsi/igt@kms_pipe_crc_basic@read-crc-pipe-b.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [DMESG-FAIL][15] ([i915#62] / [i915#95]) -> [DMESG-FAIL][16] ([i915#62])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - fi-kbl-x1275:       [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-kbl-x1275/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-kbl-x1275:       [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +5 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/fi-kbl-x1275/igt@prime_vgem@basic-fence-flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [k.org#205379]: https://bugzilla.kernel.org/show_bug.cgi?id=205379


Participating hosts (44 -> 39)
------------------------------

  Additional (1): fi-snb-2600 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_9061 -> Patchwork_18580

  CI-20190529: 20190529
  CI_DRM_9061: 1c67148ce7e9b054e6f312e898066a69b86c9edd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5789: ebc9ca51848b368170d3f76acce0c23bff84581f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18580: 07ca5d2ec781925718c727a6ed70da4954e1083a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

07ca5d2ec781 drm/i915/edp/jsl: Update vswing table for HBR and HBR2
7785c9b4e203 drm/i915/jsl: Split EHL/JSL platform info and PCI ids

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/index.html

[-- Attachment #1.2: Type: text/html, Size: 7864 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/jsl: Update JasperLake Voltage swing table
  2020-09-28  8:09 ` Tejas Upadhyay
                   ` (6 preceding siblings ...)
  (?)
@ 2020-09-28 12:14 ` Patchwork
  -1 siblings, 0 replies; 58+ messages in thread
From: Patchwork @ 2020-09-28 12:14 UTC (permalink / raw)
  To: Tejas Upadhyay; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 17718 bytes --]

== Series Details ==

Series: drm/i915/jsl: Update JasperLake Voltage swing table
URL   : https://patchwork.freedesktop.org/series/82150/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_9061_full -> Patchwork_18580_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_18580_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_18580_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18580_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_userptr_blits@process-exit-busy:
    - shard-skl:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl2/igt@gem_userptr_blits@process-exit-busy.html

  
#### Warnings ####

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@gtt:
    - shard-glk:          [INCOMPLETE][2] ([i915#95]) -> [INCOMPLETE][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-glk3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@gtt.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-glk3/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@gtt.html

  
Known issues
------------

  Here are the changes found in Patchwork_18580_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +5 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_ctx_persistence@engines-hostile-preempt@vecs0:
    - shard-kbl:          [PASS][6] -> [DMESG-WARN][7] ([i915#1982])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-kbl7/igt@gem_ctx_persistence@engines-hostile-preempt@vecs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-kbl1/igt@gem_ctx_persistence@engines-hostile-preempt@vecs0.html

  * igt@i915_selftest@mock@contexts:
    - shard-apl:          [PASS][8] -> [INCOMPLETE][9] ([i915#1635] / [i915#2278])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-apl2/igt@i915_selftest@mock@contexts.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-apl7/igt@i915_selftest@mock@contexts.html

  * igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge:
    - shard-glk:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-64x64-bottom-edge.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [PASS][12] -> [FAIL][13] ([i915#2346]) +1 similar issue
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
    - shard-skl:          [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +6 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl10/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl10/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - shard-hsw:          [PASS][16] -> [INCOMPLETE][17] ([i915#2055])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-hsw7/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
    - shard-skl:          [PASS][18] -> [FAIL][19] ([i915#2122])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
    - shard-tglb:         [PASS][20] -> [DMESG-WARN][21] ([i915#1982]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#1188])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [PASS][24] -> [SKIP][25] ([fdo#109441])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@engines-hostile-preempt@vecs0:
    - shard-skl:          [DMESG-WARN][26] ([i915#1982]) -> [PASS][27] +2 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl6/igt@gem_ctx_persistence@engines-hostile-preempt@vecs0.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl1/igt@gem_ctx_persistence@engines-hostile-preempt@vecs0.html

  * igt@i915_suspend@sysfs-reader:
    - shard-kbl:          [DMESG-WARN][28] ([i915#180]) -> [PASS][29] +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-kbl2/igt@i915_suspend@sysfs-reader.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-kbl1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-skl:          [INCOMPLETE][30] ([i915#300]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2:
    - shard-glk:          [FAIL][32] ([i915#79]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-kbl:          [DMESG-WARN][34] ([i915#1982]) -> [PASS][35] +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
    - shard-skl:          [FAIL][36] ([i915#49]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl6/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-tglb:         [DMESG-WARN][38] ([i915#1982]) -> [PASS][39] +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-tglb8/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-tglb6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - shard-skl:          [FAIL][40] ([i915#53]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl6/igt@kms_pipe_crc_basic@read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [DMESG-FAIL][42] ([fdo#108145] / [i915#1982]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][44] ([fdo#108145] / [i915#265]) -> [PASS][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_mmap_cpu:
    - shard-iclb:         [SKIP][46] ([fdo#109441]) -> [PASS][47] +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_cpu.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html

  
#### Warnings ####

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-tglb:         [DMESG-WARN][48] ([i915#1982] / [i915#2411]) -> [DMESG-WARN][49] ([i915#2411])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-tglb8/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-tglb8/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [DMESG-WARN][50] ([i915#180]) -> [DMESG-WARN][51] ([i915#165])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [DMESG-WARN][52] ([i915#1982]) -> [DMESG-FAIL][53] ([i915#1982])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][54] ([fdo#108145] / [i915#265]) -> [DMESG-WARN][55] ([i915#1982])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@runner@aborted:
    - shard-skl:          ([FAIL][56], [FAIL][57], [FAIL][58], [FAIL][59], [FAIL][60], [FAIL][61], [FAIL][62], [FAIL][63], [FAIL][64], [FAIL][65], [FAIL][66], [FAIL][67], [FAIL][68], [FAIL][69], [FAIL][70]) ([i915#1436] / [i915#1611] / [i915#2439]) -> ([FAIL][71], [FAIL][72], [FAIL][73], [FAIL][74], [FAIL][75], [FAIL][76], [FAIL][77], [FAIL][78], [FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85], [FAIL][86], [FAIL][87]) ([i915#1436] / [i915#1611] / [i915#1814] / [i915#2029] / [i915#2439])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@runner@aborted.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl3/igt@runner@aborted.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@runner@aborted.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@runner@aborted.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl2/igt@runner@aborted.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl3/igt@runner@aborted.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl2/igt@runner@aborted.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl6/igt@runner@aborted.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl8/igt@runner@aborted.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl7/igt@runner@aborted.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl5/igt@runner@aborted.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl10/igt@runner@aborted.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl8/igt@runner@aborted.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl9/igt@runner@aborted.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9061/shard-skl3/igt@runner@aborted.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl7/igt@runner@aborted.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl6/igt@runner@aborted.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl7/igt@runner@aborted.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl10/igt@runner@aborted.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl10/igt@runner@aborted.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl4/igt@runner@aborted.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl9/igt@runner@aborted.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl1/igt@runner@aborted.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl8/igt@runner@aborted.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl2/igt@runner@aborted.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl5/igt@runner@aborted.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl3/igt@runner@aborted.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl7/igt@runner@aborted.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl5/igt@runner@aborted.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl8/igt@runner@aborted.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl4/igt@runner@aborted.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/shard-skl4/igt@runner@aborted.html

  
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2278]: https://gitlab.freedesktop.org/drm/intel/issues/2278
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_9061 -> Patchwork_18580

  CI-20190529: 20190529
  CI_DRM_9061: 1c67148ce7e9b054e6f312e898066a69b86c9edd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5789: ebc9ca51848b368170d3f76acce0c23bff84581f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18580: 07ca5d2ec781925718c727a6ed70da4954e1083a @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18580/index.html

[-- Attachment #1.2: Type: text/html, Size: 20633 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28  8:09   ` Tejas Upadhyay
  (?)
@ 2020-09-28 13:37     ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 13:37 UTC (permalink / raw)
  To: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, james.ausmus, matthew.d.roper,
	jose.souza, ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> Split the basic platform definition, macros, and PCI IDs to
> differentiate between EHL and JSL platforms.
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  include/drm/i915_pciids.h                | 9 ++++++---
>  5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72a9449b674e..4f20acebb038 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>  #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>  #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> +				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> +#define IS_JASPERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)

I think we've learned from history that we want the platform checks to
be independent. I.e. if you need to split ELK and JSP, you need to make
IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().

We've been here before, and we've thought before that we can get by with
the minimal change. It's just postponing the inevitable and generates
confusion.

BR,
Jani.


>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 366ddfc8df6b..8690b69fcf33 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>  	.ppgtt_size = 36,
>  };
>  
> +static const struct intel_device_info jsl_info = {
> +	GEN11_FEATURES,
> +	PLATFORM(INTEL_JASPERLAKE),
> +	.require_force_probe = 1,
> +	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> +	.ppgtt_size = 36,
> +};
> +
>  #define GEN12_FEATURES \
>  	GEN11_FEATURES, \
>  	GEN(12), \
> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CNL_IDS(&cnl_info),
>  	INTEL_ICL_11_IDS(&icl_info),
>  	INTEL_EHL_IDS(&ehl_info),
> +	INTEL_JSL_IDS(&jsl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
>  	INTEL_RKL_IDS(&rkl_info),
>  	{0, 0, 0}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index adc836f15fde..e67cec8fa2aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(CANNONLAKE),
>  	PLATFORM_NAME(ICELAKE),
>  	PLATFORM_NAME(ELKHARTLAKE),
> +	PLATFORM_NAME(JASPERLAKE),
>  	PLATFORM_NAME(TIGERLAKE),
>  	PLATFORM_NAME(ROCKETLAKE),
>  	PLATFORM_NAME(DG1),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6a3d607218aa..d92fa041c700 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -79,6 +79,7 @@ enum intel_platform {
>  	/* gen11 */
>  	INTEL_ICELAKE,
>  	INTEL_ELKHARTLAKE,
> +	INTEL_JASPERLAKE,
>  	/* gen12 */
>  	INTEL_TIGERLAKE,
>  	INTEL_ROCKETLAKE,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 7eeecb07c9a1..1b5e09cfa11e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -579,15 +579,18 @@
>  	INTEL_VGA_DEVICE(0x8A51, info), \
>  	INTEL_VGA_DEVICE(0x8A5D, info)
>  
> -/* EHL/JSL */
> +/* EHL */
>  #define INTEL_EHL_IDS(info) \
>  	INTEL_VGA_DEVICE(0x4500, info),	\
>  	INTEL_VGA_DEVICE(0x4571, info), \
>  	INTEL_VGA_DEVICE(0x4551, info), \
>  	INTEL_VGA_DEVICE(0x4541, info), \
> -	INTEL_VGA_DEVICE(0x4E71, info), \
>  	INTEL_VGA_DEVICE(0x4557, info), \
> -	INTEL_VGA_DEVICE(0x4555, info), \
> +	INTEL_VGA_DEVICE(0x4555, info)
> +
> +/* JSL */
> +#define INTEL_JSL_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4E71, info), \
>  	INTEL_VGA_DEVICE(0x4E61, info), \
>  	INTEL_VGA_DEVICE(0x4E57, info), \
>  	INTEL_VGA_DEVICE(0x4E55, info), \

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 13:37     ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 13:37 UTC (permalink / raw)
  To: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, james.ausmus, matthew.d.roper,
	jose.souza, ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> Split the basic platform definition, macros, and PCI IDs to
> differentiate between EHL and JSL platforms.
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  include/drm/i915_pciids.h                | 9 ++++++---
>  5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72a9449b674e..4f20acebb038 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>  #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>  #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> +				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> +#define IS_JASPERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)

I think we've learned from history that we want the platform checks to
be independent. I.e. if you need to split ELK and JSP, you need to make
IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().

We've been here before, and we've thought before that we can get by with
the minimal change. It's just postponing the inevitable and generates
confusion.

BR,
Jani.


>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 366ddfc8df6b..8690b69fcf33 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>  	.ppgtt_size = 36,
>  };
>  
> +static const struct intel_device_info jsl_info = {
> +	GEN11_FEATURES,
> +	PLATFORM(INTEL_JASPERLAKE),
> +	.require_force_probe = 1,
> +	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> +	.ppgtt_size = 36,
> +};
> +
>  #define GEN12_FEATURES \
>  	GEN11_FEATURES, \
>  	GEN(12), \
> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CNL_IDS(&cnl_info),
>  	INTEL_ICL_11_IDS(&icl_info),
>  	INTEL_EHL_IDS(&ehl_info),
> +	INTEL_JSL_IDS(&jsl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
>  	INTEL_RKL_IDS(&rkl_info),
>  	{0, 0, 0}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index adc836f15fde..e67cec8fa2aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(CANNONLAKE),
>  	PLATFORM_NAME(ICELAKE),
>  	PLATFORM_NAME(ELKHARTLAKE),
> +	PLATFORM_NAME(JASPERLAKE),
>  	PLATFORM_NAME(TIGERLAKE),
>  	PLATFORM_NAME(ROCKETLAKE),
>  	PLATFORM_NAME(DG1),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6a3d607218aa..d92fa041c700 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -79,6 +79,7 @@ enum intel_platform {
>  	/* gen11 */
>  	INTEL_ICELAKE,
>  	INTEL_ELKHARTLAKE,
> +	INTEL_JASPERLAKE,
>  	/* gen12 */
>  	INTEL_TIGERLAKE,
>  	INTEL_ROCKETLAKE,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 7eeecb07c9a1..1b5e09cfa11e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -579,15 +579,18 @@
>  	INTEL_VGA_DEVICE(0x8A51, info), \
>  	INTEL_VGA_DEVICE(0x8A5D, info)
>  
> -/* EHL/JSL */
> +/* EHL */
>  #define INTEL_EHL_IDS(info) \
>  	INTEL_VGA_DEVICE(0x4500, info),	\
>  	INTEL_VGA_DEVICE(0x4571, info), \
>  	INTEL_VGA_DEVICE(0x4551, info), \
>  	INTEL_VGA_DEVICE(0x4541, info), \
> -	INTEL_VGA_DEVICE(0x4E71, info), \
>  	INTEL_VGA_DEVICE(0x4557, info), \
> -	INTEL_VGA_DEVICE(0x4555, info), \
> +	INTEL_VGA_DEVICE(0x4555, info)
> +
> +/* JSL */
> +#define INTEL_JSL_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4E71, info), \
>  	INTEL_VGA_DEVICE(0x4E61, info), \
>  	INTEL_VGA_DEVICE(0x4E57, info), \
>  	INTEL_VGA_DEVICE(0x4E55, info), \

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 13:37     ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 13:37 UTC (permalink / raw)
  To: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, james.ausmus, matthew.d.roper,
	jose.souza, ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> Split the basic platform definition, macros, and PCI IDs to
> differentiate between EHL and JSL platforms.
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  include/drm/i915_pciids.h                | 9 ++++++---
>  5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72a9449b674e..4f20acebb038 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>  #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>  #define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_ELKHARTLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> +				IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> +#define IS_JASPERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)

I think we've learned from history that we want the platform checks to
be independent. I.e. if you need to split ELK and JSP, you need to make
IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().

We've been here before, and we've thought before that we can get by with
the minimal change. It's just postponing the inevitable and generates
confusion.

BR,
Jani.


>  #define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 366ddfc8df6b..8690b69fcf33 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>  	.ppgtt_size = 36,
>  };
>  
> +static const struct intel_device_info jsl_info = {
> +	GEN11_FEATURES,
> +	PLATFORM(INTEL_JASPERLAKE),
> +	.require_force_probe = 1,
> +	.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> +	.ppgtt_size = 36,
> +};
> +
>  #define GEN12_FEATURES \
>  	GEN11_FEATURES, \
>  	GEN(12), \
> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CNL_IDS(&cnl_info),
>  	INTEL_ICL_11_IDS(&icl_info),
>  	INTEL_EHL_IDS(&ehl_info),
> +	INTEL_JSL_IDS(&jsl_info),
>  	INTEL_TGL_12_IDS(&tgl_info),
>  	INTEL_RKL_IDS(&rkl_info),
>  	{0, 0, 0}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index adc836f15fde..e67cec8fa2aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>  	PLATFORM_NAME(CANNONLAKE),
>  	PLATFORM_NAME(ICELAKE),
>  	PLATFORM_NAME(ELKHARTLAKE),
> +	PLATFORM_NAME(JASPERLAKE),
>  	PLATFORM_NAME(TIGERLAKE),
>  	PLATFORM_NAME(ROCKETLAKE),
>  	PLATFORM_NAME(DG1),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6a3d607218aa..d92fa041c700 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -79,6 +79,7 @@ enum intel_platform {
>  	/* gen11 */
>  	INTEL_ICELAKE,
>  	INTEL_ELKHARTLAKE,
> +	INTEL_JASPERLAKE,
>  	/* gen12 */
>  	INTEL_TIGERLAKE,
>  	INTEL_ROCKETLAKE,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 7eeecb07c9a1..1b5e09cfa11e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -579,15 +579,18 @@
>  	INTEL_VGA_DEVICE(0x8A51, info), \
>  	INTEL_VGA_DEVICE(0x8A5D, info)
>  
> -/* EHL/JSL */
> +/* EHL */
>  #define INTEL_EHL_IDS(info) \
>  	INTEL_VGA_DEVICE(0x4500, info),	\
>  	INTEL_VGA_DEVICE(0x4571, info), \
>  	INTEL_VGA_DEVICE(0x4551, info), \
>  	INTEL_VGA_DEVICE(0x4541, info), \
> -	INTEL_VGA_DEVICE(0x4E71, info), \
>  	INTEL_VGA_DEVICE(0x4557, info), \
> -	INTEL_VGA_DEVICE(0x4555, info), \
> +	INTEL_VGA_DEVICE(0x4555, info)
> +
> +/* JSL */
> +#define INTEL_JSL_IDS(info) \
> +	INTEL_VGA_DEVICE(0x4E71, info), \
>  	INTEL_VGA_DEVICE(0x4E61, info), \
>  	INTEL_VGA_DEVICE(0x4E57, info), \
>  	INTEL_VGA_DEVICE(0x4E55, info), \

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28  8:09   ` Tejas Upadhyay
  (?)
@ 2020-09-28 13:43     ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 13:43 UTC (permalink / raw)
  To: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, james.ausmus, matthew.d.roper,
	jose.souza, ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> JSL has update in vswing table for eDP

I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
PCH_JSP for Jasper Lake PCH.

>
> BSpec: 21257
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
>  1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..fa08463bcf2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>  };
>  
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
> +	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
> +	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
> +	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
> +	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
> +	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>  	u32 cri_txdeemph_override_11_6;
>  	u32 cri_txdeemph_override_5_0;
> @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
>  	return icl_mg_phy_ddi_translations_rbr_hbr;
>  }
> -
>  static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
> @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	}
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +			int *n_entries)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	switch (type) {
> +	case INTEL_OUTPUT_HDMI:
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +		return icl_combo_phy_ddi_translations_hdmi;
> +	case INTEL_OUTPUT_EDP:
> +		if (dev_priv->vbt.edp.low_vswing) {
> +			if (rate > 270000) {
> +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> +				return jsl_combo_phy_ddi_translations_edp_hbr2;
> +			} else {
> +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> +				return jsl_combo_phy_ddi_translations_edp_hbr;
> +			}
> +		}
> +		/* fall through */
> +	default:
> +		/* All combo DP and eDP ports that do not support low_vswing */
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> +		return icl_combo_phy_ddi_translations_dp_hbr2;
> +	}
> +}
> +
>  static const struct cnl_ddi_buf_trans *
>  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
> @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>  			tgl_get_dkl_buf_trans(encoder, encoder->type,
>  					      intel_dp->link_rate, &n_entries);
>  	} else if (INTEL_GEN(dev_priv) == 11) {
> -		if (IS_ELKHARTLAKE(dev_priv))
> +		if (IS_JASPERLAKE(dev_priv))
> +			jsl_get_combo_buf_trans(encoder, encoder->type,
> +					intel_dp->link_rate, &n_entries);
> +		else if (IS_ELKHARTLAKE(dev_priv))
>  			ehl_get_combo_buf_trans(encoder, encoder->type,
> -						intel_dp->link_rate, &n_entries);
> +					intel_dp->link_rate, &n_entries);

This is a good example of a potential trap that having IS_ELKHARTLAKE()
cover both ELK and JSP creates. An unsuspecting coder might change the
if ladder to have IS_ELKHARTLAKE() first, and the subsequent
IS_JASPERLAKE() branch would never be taken.

BR,
Jani.

>  		else if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(encoder, encoder->type,
>  						intel_dp->link_rate, &n_entries);
> @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
>  							   &n_entries);
> +	else if (IS_JASPERLAKE(dev_priv))
> +		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> +							   &n_entries);
>  	else if (IS_ELKHARTLAKE(dev_priv))
>  		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
>  							   &n_entries);

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 13:43     ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 13:43 UTC (permalink / raw)
  To: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, james.ausmus, matthew.d.roper,
	jose.souza, ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> JSL has update in vswing table for eDP

I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
PCH_JSP for Jasper Lake PCH.

>
> BSpec: 21257
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
>  1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..fa08463bcf2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>  };
>  
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
> +	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
> +	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
> +	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
> +	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
> +	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>  	u32 cri_txdeemph_override_11_6;
>  	u32 cri_txdeemph_override_5_0;
> @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
>  	return icl_mg_phy_ddi_translations_rbr_hbr;
>  }
> -
>  static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
> @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	}
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +			int *n_entries)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	switch (type) {
> +	case INTEL_OUTPUT_HDMI:
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +		return icl_combo_phy_ddi_translations_hdmi;
> +	case INTEL_OUTPUT_EDP:
> +		if (dev_priv->vbt.edp.low_vswing) {
> +			if (rate > 270000) {
> +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> +				return jsl_combo_phy_ddi_translations_edp_hbr2;
> +			} else {
> +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> +				return jsl_combo_phy_ddi_translations_edp_hbr;
> +			}
> +		}
> +		/* fall through */
> +	default:
> +		/* All combo DP and eDP ports that do not support low_vswing */
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> +		return icl_combo_phy_ddi_translations_dp_hbr2;
> +	}
> +}
> +
>  static const struct cnl_ddi_buf_trans *
>  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
> @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>  			tgl_get_dkl_buf_trans(encoder, encoder->type,
>  					      intel_dp->link_rate, &n_entries);
>  	} else if (INTEL_GEN(dev_priv) == 11) {
> -		if (IS_ELKHARTLAKE(dev_priv))
> +		if (IS_JASPERLAKE(dev_priv))
> +			jsl_get_combo_buf_trans(encoder, encoder->type,
> +					intel_dp->link_rate, &n_entries);
> +		else if (IS_ELKHARTLAKE(dev_priv))
>  			ehl_get_combo_buf_trans(encoder, encoder->type,
> -						intel_dp->link_rate, &n_entries);
> +					intel_dp->link_rate, &n_entries);

This is a good example of a potential trap that having IS_ELKHARTLAKE()
cover both ELK and JSP creates. An unsuspecting coder might change the
if ladder to have IS_ELKHARTLAKE() first, and the subsequent
IS_JASPERLAKE() branch would never be taken.

BR,
Jani.

>  		else if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(encoder, encoder->type,
>  						intel_dp->link_rate, &n_entries);
> @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
>  							   &n_entries);
> +	else if (IS_JASPERLAKE(dev_priv))
> +		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> +							   &n_entries);
>  	else if (IS_ELKHARTLAKE(dev_priv))
>  		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
>  							   &n_entries);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 13:43     ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 13:43 UTC (permalink / raw)
  To: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, james.ausmus, matthew.d.roper,
	jose.souza, ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> JSL has update in vswing table for eDP

I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
PCH_JSP for Jasper Lake PCH.

>
> BSpec: 21257
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
>  1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..fa08463bcf2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>  };
>  
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
> +	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
> +	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
> +	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
> +	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
> +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
> +	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
> +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>  	u32 cri_txdeemph_override_11_6;
>  	u32 cri_txdeemph_override_5_0;
> @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
>  	return icl_mg_phy_ddi_translations_rbr_hbr;
>  }
> -
>  static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
> @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	}
>  }
>  
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +			int *n_entries)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +	switch (type) {
> +	case INTEL_OUTPUT_HDMI:
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +		return icl_combo_phy_ddi_translations_hdmi;
> +	case INTEL_OUTPUT_EDP:
> +		if (dev_priv->vbt.edp.low_vswing) {
> +			if (rate > 270000) {
> +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> +				return jsl_combo_phy_ddi_translations_edp_hbr2;
> +			} else {
> +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> +				return jsl_combo_phy_ddi_translations_edp_hbr;
> +			}
> +		}
> +		/* fall through */
> +	default:
> +		/* All combo DP and eDP ports that do not support low_vswing */
> +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> +		return icl_combo_phy_ddi_translations_dp_hbr2;
> +	}
> +}
> +
>  static const struct cnl_ddi_buf_trans *
>  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  			int *n_entries)
> @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>  			tgl_get_dkl_buf_trans(encoder, encoder->type,
>  					      intel_dp->link_rate, &n_entries);
>  	} else if (INTEL_GEN(dev_priv) == 11) {
> -		if (IS_ELKHARTLAKE(dev_priv))
> +		if (IS_JASPERLAKE(dev_priv))
> +			jsl_get_combo_buf_trans(encoder, encoder->type,
> +					intel_dp->link_rate, &n_entries);
> +		else if (IS_ELKHARTLAKE(dev_priv))
>  			ehl_get_combo_buf_trans(encoder, encoder->type,
> -						intel_dp->link_rate, &n_entries);
> +					intel_dp->link_rate, &n_entries);

This is a good example of a potential trap that having IS_ELKHARTLAKE()
cover both ELK and JSP creates. An unsuspecting coder might change the
if ladder to have IS_ELKHARTLAKE() first, and the subsequent
IS_JASPERLAKE() branch would never be taken.

BR,
Jani.

>  		else if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(encoder, encoder->type,
>  						intel_dp->link_rate, &n_entries);
> @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>  	if (INTEL_GEN(dev_priv) >= 12)
>  		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
>  							   &n_entries);
> +	else if (IS_JASPERLAKE(dev_priv))
> +		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> +							   &n_entries);
>  	else if (IS_ELKHARTLAKE(dev_priv))
>  		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
>  							   &n_entries);

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 13:43     ` Jani Nikula
  (?)
@ 2020-09-28 14:15       ` James Ausmus
  -1 siblings, 0 replies; 58+ messages in thread
From: James Ausmus @ 2020-09-28 14:15 UTC (permalink / raw)
  To: Jani Nikula
  Cc: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, matthew.d.roper, jose.souza,
	ville.syrjala, lucas.demarchi, hariom.pandey

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > JSL has update in vswing table for eDP
> 
> I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> PCH_JSP for Jasper Lake PCH.

JSP == Point (the PCH), JSL == Lake

-James

> 
> >
> > BSpec: 21257
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
> >  1 file changed, 64 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4d06178cd76c..fa08463bcf2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> >  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> >  };
> >  
> > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> > +						/* NT mV Trans mV db    */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> > +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
> > +	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
> > +	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> > +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
> > +	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> > +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> > +};
> > +
> > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> > +						/* NT mV Trans mV db    */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
> > +	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
> > +	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> > +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> > +};
> > +
> >  struct icl_mg_phy_ddi_buf_trans {
> >  	u32 cri_txdeemph_override_11_6;
> >  	u32 cri_txdeemph_override_5_0;
> > @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
> >  	return icl_mg_phy_ddi_translations_rbr_hbr;
> >  }
> > -
> >  static const struct cnl_ddi_buf_trans *
> >  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  			int *n_entries)
> > @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  	}
> >  }
> >  
> > +static const struct cnl_ddi_buf_trans *
> > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > +			int *n_entries)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > +	switch (type) {
> > +	case INTEL_OUTPUT_HDMI:
> > +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > +		return icl_combo_phy_ddi_translations_hdmi;
> > +	case INTEL_OUTPUT_EDP:
> > +		if (dev_priv->vbt.edp.low_vswing) {
> > +			if (rate > 270000) {
> > +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> > +				return jsl_combo_phy_ddi_translations_edp_hbr2;
> > +			} else {
> > +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> > +				return jsl_combo_phy_ddi_translations_edp_hbr;
> > +			}
> > +		}
> > +		/* fall through */
> > +	default:
> > +		/* All combo DP and eDP ports that do not support low_vswing */
> > +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> > +		return icl_combo_phy_ddi_translations_dp_hbr2;
> > +	}
> > +}
> > +
> >  static const struct cnl_ddi_buf_trans *
> >  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  			int *n_entries)
> > @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> >  			tgl_get_dkl_buf_trans(encoder, encoder->type,
> >  					      intel_dp->link_rate, &n_entries);
> >  	} else if (INTEL_GEN(dev_priv) == 11) {
> > -		if (IS_ELKHARTLAKE(dev_priv))
> > +		if (IS_JASPERLAKE(dev_priv))
> > +			jsl_get_combo_buf_trans(encoder, encoder->type,
> > +					intel_dp->link_rate, &n_entries);
> > +		else if (IS_ELKHARTLAKE(dev_priv))
> >  			ehl_get_combo_buf_trans(encoder, encoder->type,
> > -						intel_dp->link_rate, &n_entries);
> > +					intel_dp->link_rate, &n_entries);
> 
> This is a good example of a potential trap that having IS_ELKHARTLAKE()
> cover both ELK and JSP creates. An unsuspecting coder might change the
> if ladder to have IS_ELKHARTLAKE() first, and the subsequent
> IS_JASPERLAKE() branch would never be taken.
> 
> BR,
> Jani.
> 
> >  		else if (intel_phy_is_combo(dev_priv, phy))
> >  			icl_get_combo_buf_trans(encoder, encoder->type,
> >  						intel_dp->link_rate, &n_entries);
> > @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	if (INTEL_GEN(dev_priv) >= 12)
> >  		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
> >  							   &n_entries);
> > +	else if (IS_JASPERLAKE(dev_priv))
> > +		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> > +							   &n_entries);
> >  	else if (IS_ELKHARTLAKE(dev_priv))
> >  		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
> >  							   &n_entries);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 14:15       ` James Ausmus
  0 siblings, 0 replies; 58+ messages in thread
From: James Ausmus @ 2020-09-28 14:15 UTC (permalink / raw)
  To: Jani Nikula
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel, jose.souza, rodrigo.vivi, Tejas Upadhyay

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > JSL has update in vswing table for eDP
> 
> I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> PCH_JSP for Jasper Lake PCH.

JSP == Point (the PCH), JSL == Lake

-James

> 
> >
> > BSpec: 21257
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
> >  1 file changed, 64 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4d06178cd76c..fa08463bcf2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> >  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> >  };
> >  
> > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> > +						/* NT mV Trans mV db    */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> > +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
> > +	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
> > +	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> > +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
> > +	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> > +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> > +};
> > +
> > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> > +						/* NT mV Trans mV db    */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
> > +	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
> > +	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> > +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> > +};
> > +
> >  struct icl_mg_phy_ddi_buf_trans {
> >  	u32 cri_txdeemph_override_11_6;
> >  	u32 cri_txdeemph_override_5_0;
> > @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
> >  	return icl_mg_phy_ddi_translations_rbr_hbr;
> >  }
> > -
> >  static const struct cnl_ddi_buf_trans *
> >  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  			int *n_entries)
> > @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  	}
> >  }
> >  
> > +static const struct cnl_ddi_buf_trans *
> > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > +			int *n_entries)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > +	switch (type) {
> > +	case INTEL_OUTPUT_HDMI:
> > +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > +		return icl_combo_phy_ddi_translations_hdmi;
> > +	case INTEL_OUTPUT_EDP:
> > +		if (dev_priv->vbt.edp.low_vswing) {
> > +			if (rate > 270000) {
> > +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> > +				return jsl_combo_phy_ddi_translations_edp_hbr2;
> > +			} else {
> > +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> > +				return jsl_combo_phy_ddi_translations_edp_hbr;
> > +			}
> > +		}
> > +		/* fall through */
> > +	default:
> > +		/* All combo DP and eDP ports that do not support low_vswing */
> > +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> > +		return icl_combo_phy_ddi_translations_dp_hbr2;
> > +	}
> > +}
> > +
> >  static const struct cnl_ddi_buf_trans *
> >  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  			int *n_entries)
> > @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> >  			tgl_get_dkl_buf_trans(encoder, encoder->type,
> >  					      intel_dp->link_rate, &n_entries);
> >  	} else if (INTEL_GEN(dev_priv) == 11) {
> > -		if (IS_ELKHARTLAKE(dev_priv))
> > +		if (IS_JASPERLAKE(dev_priv))
> > +			jsl_get_combo_buf_trans(encoder, encoder->type,
> > +					intel_dp->link_rate, &n_entries);
> > +		else if (IS_ELKHARTLAKE(dev_priv))
> >  			ehl_get_combo_buf_trans(encoder, encoder->type,
> > -						intel_dp->link_rate, &n_entries);
> > +					intel_dp->link_rate, &n_entries);
> 
> This is a good example of a potential trap that having IS_ELKHARTLAKE()
> cover both ELK and JSP creates. An unsuspecting coder might change the
> if ladder to have IS_ELKHARTLAKE() first, and the subsequent
> IS_JASPERLAKE() branch would never be taken.
> 
> BR,
> Jani.
> 
> >  		else if (intel_phy_is_combo(dev_priv, phy))
> >  			icl_get_combo_buf_trans(encoder, encoder->type,
> >  						intel_dp->link_rate, &n_entries);
> > @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	if (INTEL_GEN(dev_priv) >= 12)
> >  		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
> >  							   &n_entries);
> > +	else if (IS_JASPERLAKE(dev_priv))
> > +		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> > +							   &n_entries);
> >  	else if (IS_ELKHARTLAKE(dev_priv))
> >  		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
> >  							   &n_entries);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 14:15       ` James Ausmus
  0 siblings, 0 replies; 58+ messages in thread
From: James Ausmus @ 2020-09-28 14:15 UTC (permalink / raw)
  To: Jani Nikula
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > JSL has update in vswing table for eDP
> 
> I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> PCH_JSP for Jasper Lake PCH.

JSP == Point (the PCH), JSL == Lake

-James

> 
> >
> > BSpec: 21257
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
> >  1 file changed, 64 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 4d06178cd76c..fa08463bcf2e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
> >  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> >  };
> >  
> > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> > +						/* NT mV Trans mV db    */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> > +	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 200   250      1.9   */
> > +	{ 0x1, 0x7F, 0x33, 0x00, 0x0C },	/* 200   300      3.5   */
> > +	{ 0xA, 0x35, 0x36, 0x00, 0x09 },	/* 200   350      4.9   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> > +	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 250   300      1.6   */
> > +	{ 0xA, 0x35, 0x35, 0x00, 0x0A },	/* 250   350      2.9   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> > +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> > +};
> > +
> > +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> > +						/* NT mV Trans mV db    */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   200      0.0   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 200   250      1.9   */
> > +	{ 0x1, 0x7F, 0x3D, 0x00, 0x02 },	/* 200   300      3.5   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 200   350      4.9   */
> > +	{ 0x8, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   250      0.0   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 250   300      1.6   */
> > +	{ 0xA, 0x35, 0x3A, 0x00, 0x05 },	/* 250   350      2.9   */
> > +	{ 0x1, 0x7F, 0x3F, 0x00, 0x00 },	/* 300   300      0.0   */
> > +	{ 0xA, 0x35, 0x38, 0x00, 0x07 },	/* 300   350      1.3   */
> > +	{ 0xA, 0x35, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> > +};
> > +
> >  struct icl_mg_phy_ddi_buf_trans {
> >  	u32 cri_txdeemph_override_11_6;
> >  	u32 cri_txdeemph_override_5_0;
> > @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  	*n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
> >  	return icl_mg_phy_ddi_translations_rbr_hbr;
> >  }
> > -
> >  static const struct cnl_ddi_buf_trans *
> >  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  			int *n_entries)
> > @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  	}
> >  }
> >  
> > +static const struct cnl_ddi_buf_trans *
> > +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> > +			int *n_entries)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > +
> > +	switch (type) {
> > +	case INTEL_OUTPUT_HDMI:
> > +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> > +		return icl_combo_phy_ddi_translations_hdmi;
> > +	case INTEL_OUTPUT_EDP:
> > +		if (dev_priv->vbt.edp.low_vswing) {
> > +			if (rate > 270000) {
> > +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> > +				return jsl_combo_phy_ddi_translations_edp_hbr2;
> > +			} else {
> > +				*n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> > +				return jsl_combo_phy_ddi_translations_edp_hbr;
> > +			}
> > +		}
> > +		/* fall through */
> > +	default:
> > +		/* All combo DP and eDP ports that do not support low_vswing */
> > +		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> > +		return icl_combo_phy_ddi_translations_dp_hbr2;
> > +	}
> > +}
> > +
> >  static const struct cnl_ddi_buf_trans *
> >  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> >  			int *n_entries)
> > @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
> >  			tgl_get_dkl_buf_trans(encoder, encoder->type,
> >  					      intel_dp->link_rate, &n_entries);
> >  	} else if (INTEL_GEN(dev_priv) == 11) {
> > -		if (IS_ELKHARTLAKE(dev_priv))
> > +		if (IS_JASPERLAKE(dev_priv))
> > +			jsl_get_combo_buf_trans(encoder, encoder->type,
> > +					intel_dp->link_rate, &n_entries);
> > +		else if (IS_ELKHARTLAKE(dev_priv))
> >  			ehl_get_combo_buf_trans(encoder, encoder->type,
> > -						intel_dp->link_rate, &n_entries);
> > +					intel_dp->link_rate, &n_entries);
> 
> This is a good example of a potential trap that having IS_ELKHARTLAKE()
> cover both ELK and JSP creates. An unsuspecting coder might change the
> if ladder to have IS_ELKHARTLAKE() first, and the subsequent
> IS_JASPERLAKE() branch would never be taken.
> 
> BR,
> Jani.
> 
> >  		else if (intel_phy_is_combo(dev_priv, phy))
> >  			icl_get_combo_buf_trans(encoder, encoder->type,
> >  						intel_dp->link_rate, &n_entries);
> > @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
> >  	if (INTEL_GEN(dev_priv) >= 12)
> >  		ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
> >  							   &n_entries);
> > +	else if (IS_JASPERLAKE(dev_priv))
> > +		ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> > +							   &n_entries);
> >  	else if (IS_ELKHARTLAKE(dev_priv))
> >  		ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
> >  							   &n_entries);
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 14:15       ` James Ausmus
  (?)
@ 2020-09-28 15:02         ` Ville Syrjälä
  -1 siblings, 0 replies; 58+ messages in thread
From: Ville Syrjälä @ 2020-09-28 15:02 UTC (permalink / raw)
  To: James Ausmus
  Cc: Jani Nikula, Tejas Upadhyay, rodrigo.vivi, airlied, daniel,
	intel-gfx, dri-devel, linux-kernel, matthew.d.roper, jose.souza,
	lucas.demarchi, hariom.pandey

On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > > JSL has update in vswing table for eDP
> > 
> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> > PCH_JSP for Jasper Lake PCH.
> 
> JSP == Point (the PCH), JSL == Lake

.PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 15:02         ` Ville Syrjälä
  0 siblings, 0 replies; 58+ messages in thread
From: Ville Syrjälä @ 2020-09-28 15:02 UTC (permalink / raw)
  To: James Ausmus
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel, rodrigo.vivi, jose.souza, Tejas Upadhyay

On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > > JSL has update in vswing table for eDP
> > 
> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> > PCH_JSP for Jasper Lake PCH.
> 
> JSP == Point (the PCH), JSL == Lake

.PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 15:02         ` Ville Syrjälä
  0 siblings, 0 replies; 58+ messages in thread
From: Ville Syrjälä @ 2020-09-28 15:02 UTC (permalink / raw)
  To: James Ausmus
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel

On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > > JSL has update in vswing table for eDP
> > 
> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> > PCH_JSP for Jasper Lake PCH.
> 
> JSP == Point (the PCH), JSL == Lake

.PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28 13:37     ` Jani Nikula
@ 2020-09-28 16:31       ` Surendrakumar Upadhyay, TejaskumarX
  -1 siblings, 0 replies; 58+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2020-09-28 16:31 UTC (permalink / raw)
  To: Jani Nikula, Vivi, Rodrigo, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, Ausmus, James, Roper, Matthew D, Souza,
	Jose, ville.syrjala, De Marchi, Lucas, Pandey, Hariom


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________________________________
From: Jani Nikula <jani.nikula@linux.intel.com>
Sent: Monday, September 28, 2020 7:07 PM
To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> Split the basic platform definition, macros, and PCI IDs to
> differentiate between EHL and JSL platforms.
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  include/drm/i915_pciids.h                | 9 ++++++---
>  5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72a9449b674e..4f20acebb038 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)

I think we've learned from history that we want the platform checks to
be independent. I.e. if you need to split ELK and JSP, you need to make
IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().

We've been here before, and we've thought before that we can get by with
the minimal change. It's just postponing the inevitable and generates
confusion.

BR,
Jani.

Tejas :  Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will make lot of changes at each place. To avoid huge change and to differentiate between platforms we have taken this way. Do you think we still change it everywhere? Do you have example where it can harm this change?

>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 366ddfc8df6b..8690b69fcf33 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>        .ppgtt_size = 36,
>  };
>
> +static const struct intel_device_info jsl_info = {
> +     GEN11_FEATURES,
> +     PLATFORM(INTEL_JASPERLAKE),
> +     .require_force_probe = 1,
> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> +     .ppgtt_size = 36,
> +};
> +
>  #define GEN12_FEATURES \
>        GEN11_FEATURES, \
>        GEN(12), \
> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>        INTEL_CNL_IDS(&cnl_info),
>        INTEL_ICL_11_IDS(&icl_info),
>        INTEL_EHL_IDS(&ehl_info),
> +     INTEL_JSL_IDS(&jsl_info),
>        INTEL_TGL_12_IDS(&tgl_info),
>        INTEL_RKL_IDS(&rkl_info),
>        {0, 0, 0}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index adc836f15fde..e67cec8fa2aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>        PLATFORM_NAME(CANNONLAKE),
>        PLATFORM_NAME(ICELAKE),
>        PLATFORM_NAME(ELKHARTLAKE),
> +     PLATFORM_NAME(JASPERLAKE),
>        PLATFORM_NAME(TIGERLAKE),
>        PLATFORM_NAME(ROCKETLAKE),
>        PLATFORM_NAME(DG1),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6a3d607218aa..d92fa041c700 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -79,6 +79,7 @@ enum intel_platform {
>        /* gen11 */
>        INTEL_ICELAKE,
>        INTEL_ELKHARTLAKE,
> +     INTEL_JASPERLAKE,
>        /* gen12 */
>        INTEL_TIGERLAKE,
>        INTEL_ROCKETLAKE,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 7eeecb07c9a1..1b5e09cfa11e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -579,15 +579,18 @@
>        INTEL_VGA_DEVICE(0x8A51, info), \
>        INTEL_VGA_DEVICE(0x8A5D, info)
>
> -/* EHL/JSL */
> +/* EHL */
>  #define INTEL_EHL_IDS(info) \
>        INTEL_VGA_DEVICE(0x4500, info), \
>        INTEL_VGA_DEVICE(0x4571, info), \
>        INTEL_VGA_DEVICE(0x4551, info), \
>        INTEL_VGA_DEVICE(0x4541, info), \
> -     INTEL_VGA_DEVICE(0x4E71, info), \
>        INTEL_VGA_DEVICE(0x4557, info), \
> -     INTEL_VGA_DEVICE(0x4555, info), \
> +     INTEL_VGA_DEVICE(0x4555, info)
> +
> +/* JSL */
> +#define INTEL_JSL_IDS(info) \
> +     INTEL_VGA_DEVICE(0x4E71, info), \
>        INTEL_VGA_DEVICE(0x4E61, info), \
>        INTEL_VGA_DEVICE(0x4E57, info), \
>        INTEL_VGA_DEVICE(0x4E55, info), \

--
Jani Nikula, Intel Open Source Graphics Center

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 16:31       ` Surendrakumar Upadhyay, TejaskumarX
  0 siblings, 0 replies; 58+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2020-09-28 16:31 UTC (permalink / raw)
  To: Jani Nikula, Vivi, Rodrigo, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, Ausmus, James, Roper, Matthew D, Souza,
	Jose, ville.syrjala, De Marchi, Lucas, Pandey, Hariom


[-- Attachment #1.1: Type: text/plain, Size: 6316 bytes --]



________________________________
From: Jani Nikula <jani.nikula@linux.intel.com>
Sent: Monday, September 28, 2020 7:07 PM
To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> Split the basic platform definition, macros, and PCI IDs to
> differentiate between EHL and JSL platforms.
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>  include/drm/i915_pciids.h                | 9 ++++++---
>  5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 72a9449b674e..4f20acebb038 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)

I think we've learned from history that we want the platform checks to
be independent. I.e. if you need to split ELK and JSP, you need to make
IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().

We've been here before, and we've thought before that we can get by with
the minimal change. It's just postponing the inevitable and generates
confusion.

BR,
Jani.

Tejas :  Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will make lot of changes at each place. To avoid huge change and to differentiate between platforms we have taken this way. Do you think we still change it everywhere? Do you have example where it can harm this change?

>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 366ddfc8df6b..8690b69fcf33 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>        .ppgtt_size = 36,
>  };
>
> +static const struct intel_device_info jsl_info = {
> +     GEN11_FEATURES,
> +     PLATFORM(INTEL_JASPERLAKE),
> +     .require_force_probe = 1,
> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> +     .ppgtt_size = 36,
> +};
> +
>  #define GEN12_FEATURES \
>        GEN11_FEATURES, \
>        GEN(12), \
> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>        INTEL_CNL_IDS(&cnl_info),
>        INTEL_ICL_11_IDS(&icl_info),
>        INTEL_EHL_IDS(&ehl_info),
> +     INTEL_JSL_IDS(&jsl_info),
>        INTEL_TGL_12_IDS(&tgl_info),
>        INTEL_RKL_IDS(&rkl_info),
>        {0, 0, 0}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index adc836f15fde..e67cec8fa2aa 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>        PLATFORM_NAME(CANNONLAKE),
>        PLATFORM_NAME(ICELAKE),
>        PLATFORM_NAME(ELKHARTLAKE),
> +     PLATFORM_NAME(JASPERLAKE),
>        PLATFORM_NAME(TIGERLAKE),
>        PLATFORM_NAME(ROCKETLAKE),
>        PLATFORM_NAME(DG1),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 6a3d607218aa..d92fa041c700 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -79,6 +79,7 @@ enum intel_platform {
>        /* gen11 */
>        INTEL_ICELAKE,
>        INTEL_ELKHARTLAKE,
> +     INTEL_JASPERLAKE,
>        /* gen12 */
>        INTEL_TIGERLAKE,
>        INTEL_ROCKETLAKE,
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 7eeecb07c9a1..1b5e09cfa11e 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -579,15 +579,18 @@
>        INTEL_VGA_DEVICE(0x8A51, info), \
>        INTEL_VGA_DEVICE(0x8A5D, info)
>
> -/* EHL/JSL */
> +/* EHL */
>  #define INTEL_EHL_IDS(info) \
>        INTEL_VGA_DEVICE(0x4500, info), \
>        INTEL_VGA_DEVICE(0x4571, info), \
>        INTEL_VGA_DEVICE(0x4551, info), \
>        INTEL_VGA_DEVICE(0x4541, info), \
> -     INTEL_VGA_DEVICE(0x4E71, info), \
>        INTEL_VGA_DEVICE(0x4557, info), \
> -     INTEL_VGA_DEVICE(0x4555, info), \
> +     INTEL_VGA_DEVICE(0x4555, info)
> +
> +/* JSL */
> +#define INTEL_JSL_IDS(info) \
> +     INTEL_VGA_DEVICE(0x4E71, info), \
>        INTEL_VGA_DEVICE(0x4E61, info), \
>        INTEL_VGA_DEVICE(0x4E57, info), \
>        INTEL_VGA_DEVICE(0x4E55, info), \

--
Jani Nikula, Intel Open Source Graphics Center

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 13:43     ` Jani Nikula
@ 2020-09-28 16:34       ` Surendrakumar Upadhyay, TejaskumarX
  -1 siblings, 0 replies; 58+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2020-09-28 16:34 UTC (permalink / raw)
  To: Jani Nikula, Vivi, Rodrigo, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, Ausmus, James, Roper, Matthew D, Souza,
	Jose, ville.syrjala, De Marchi, Lucas, Pandey, Hariom


[-- Attachment #1.1: Type: text/plain, Size: 7995 bytes --]



________________________________
From: Jani Nikula <jani.nikula@linux.intel.com>
Sent: Monday, September 28, 2020 7:13 PM
To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> JSL has update in vswing table for eDP

I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
PCH_JSP for Jasper Lake PCH.

>
> BSpec: 21257
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
>  1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..fa08463bcf2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>        { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
>  };
>
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> +                                             /* NT mV Trans mV db    */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
> +     { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
> +     { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
> +     { 0xA, 0x35, 0x36, 0x00, 0x09 },        /* 200   350      4.9   */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
> +     { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
> +     { 0xA, 0x35, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
> +     { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
> +     { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
> +     { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> +                                             /* NT mV Trans mV db    */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   250      1.9   */
> +     { 0x1, 0x7F, 0x3D, 0x00, 0x02 },        /* 200   300      3.5   */
> +     { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 200   350      4.9   */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
> +     { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   300      1.6   */
> +     { 0xA, 0x35, 0x3A, 0x00, 0x05 },        /* 250   350      2.9   */
> +     { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
> +     { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
> +     { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>        u32 cri_txdeemph_override_11_6;
>        u32 cri_txdeemph_override_5_0;
> @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
>        *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
>        return icl_mg_phy_ddi_translations_rbr_hbr;
>  }
> -
>  static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>                        int *n_entries)
> @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>        }
>  }
>
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +                     int *n_entries)
> +{
> +     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +     switch (type) {
> +     case INTEL_OUTPUT_HDMI:
> +             *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +             return icl_combo_phy_ddi_translations_hdmi;
> +     case INTEL_OUTPUT_EDP:
> +             if (dev_priv->vbt.edp.low_vswing) {
> +                     if (rate > 270000) {
> +                             *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> +                             return jsl_combo_phy_ddi_translations_edp_hbr2;
> +                     } else {
> +                             *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> +                             return jsl_combo_phy_ddi_translations_edp_hbr;
> +                     }
> +             }
> +             /* fall through */
> +     default:
> +             /* All combo DP and eDP ports that do not support low_vswing */
> +             *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> +             return icl_combo_phy_ddi_translations_dp_hbr2;
> +     }
> +}
> +
>  static const struct cnl_ddi_buf_trans *
>  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>                        int *n_entries)
> @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>                        tgl_get_dkl_buf_trans(encoder, encoder->type,
>                                              intel_dp->link_rate, &n_entries);
>        } else if (INTEL_GEN(dev_priv) == 11) {
> -             if (IS_ELKHARTLAKE(dev_priv))
> +             if (IS_JASPERLAKE(dev_priv))
> +                     jsl_get_combo_buf_trans(encoder, encoder->type,
> +                                     intel_dp->link_rate, &n_entries);
> +             else if (IS_ELKHARTLAKE(dev_priv))
>                        ehl_get_combo_buf_trans(encoder, encoder->type,
> -                                             intel_dp->link_rate, &n_entries);
> +                                     intel_dp->link_rate, &n_entries);

This is a good example of a potential trap that having IS_ELKHARTLAKE()
cover both ELK and JSP creates. An unsuspecting coder might change the
if ladder to have IS_ELKHARTLAKE() first, and the subsequent
IS_JASPERLAKE() branch would never be taken.

BR,
Jani.

Tejas : In that case I will put attention note in comment about platform checks such that ladder distrubance can be avoided. What you suggest?

>                else if (intel_phy_is_combo(dev_priv, phy))
>                        icl_get_combo_buf_trans(encoder, encoder->type,
>                                                intel_dp->link_rate, &n_entries);
> @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>        if (INTEL_GEN(dev_priv) >= 12)
>                ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
>                                                           &n_entries);
> +     else if (IS_JASPERLAKE(dev_priv))
> +             ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> +                                                        &n_entries);
>        else if (IS_ELKHARTLAKE(dev_priv))
>                ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
>                                                           &n_entries);

--
Jani Nikula, Intel Open Source Graphics Center

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 16:34       ` Surendrakumar Upadhyay, TejaskumarX
  0 siblings, 0 replies; 58+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2020-09-28 16:34 UTC (permalink / raw)
  To: Jani Nikula, Vivi, Rodrigo, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, Ausmus, James, Roper, Matthew D, Souza,
	Jose, ville.syrjala, De Marchi, Lucas, Pandey, Hariom


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________________________________
From: Jani Nikula <jani.nikula@linux.intel.com>
Sent: Monday, September 28, 2020 7:13 PM
To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> JSL has update in vswing table for eDP

I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
PCH_JSP for Jasper Lake PCH.

>
> BSpec: 21257
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 67 ++++++++++++++++++++++--
>  1 file changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4d06178cd76c..fa08463bcf2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>        { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
>  };
>
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr[] = {
> +                                             /* NT mV Trans mV db    */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
> +     { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
> +     { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
> +     { 0xA, 0x35, 0x36, 0x00, 0x09 },        /* 200   350      4.9   */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
> +     { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
> +     { 0xA, 0x35, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
> +     { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
> +     { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
> +     { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans jsl_combo_phy_ddi_translations_edp_hbr2[] = {
> +                                             /* NT mV Trans mV db    */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   250      1.9   */
> +     { 0x1, 0x7F, 0x3D, 0x00, 0x02 },        /* 200   300      3.5   */
> +     { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 200   350      4.9   */
> +     { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
> +     { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   300      1.6   */
> +     { 0xA, 0x35, 0x3A, 0x00, 0x05 },        /* 250   350      2.9   */
> +     { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
> +     { 0xA, 0x35, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
> +     { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>        u32 cri_txdeemph_override_11_6;
>        u32 cri_txdeemph_override_5_0;
> @@ -1069,7 +1097,6 @@ icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
>        *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
>        return icl_mg_phy_ddi_translations_rbr_hbr;
>  }
> -
>  static const struct cnl_ddi_buf_trans *
>  ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>                        int *n_entries)
> @@ -1098,6 +1125,34 @@ ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>        }
>  }
>
> +static const struct cnl_ddi_buf_trans *
> +jsl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
> +                     int *n_entries)
> +{
> +     struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +
> +     switch (type) {
> +     case INTEL_OUTPUT_HDMI:
> +             *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> +             return icl_combo_phy_ddi_translations_hdmi;
> +     case INTEL_OUTPUT_EDP:
> +             if (dev_priv->vbt.edp.low_vswing) {
> +                     if (rate > 270000) {
> +                             *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr2);
> +                             return jsl_combo_phy_ddi_translations_edp_hbr2;
> +                     } else {
> +                             *n_entries = ARRAY_SIZE(jsl_combo_phy_ddi_translations_edp_hbr);
> +                             return jsl_combo_phy_ddi_translations_edp_hbr;
> +                     }
> +             }
> +             /* fall through */
> +     default:
> +             /* All combo DP and eDP ports that do not support low_vswing */
> +             *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> +             return icl_combo_phy_ddi_translations_dp_hbr2;
> +     }
> +}
> +
>  static const struct cnl_ddi_buf_trans *
>  tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>                        int *n_entries)
> @@ -2265,9 +2320,12 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
>                        tgl_get_dkl_buf_trans(encoder, encoder->type,
>                                              intel_dp->link_rate, &n_entries);
>        } else if (INTEL_GEN(dev_priv) == 11) {
> -             if (IS_ELKHARTLAKE(dev_priv))
> +             if (IS_JASPERLAKE(dev_priv))
> +                     jsl_get_combo_buf_trans(encoder, encoder->type,
> +                                     intel_dp->link_rate, &n_entries);
> +             else if (IS_ELKHARTLAKE(dev_priv))
>                        ehl_get_combo_buf_trans(encoder, encoder->type,
> -                                             intel_dp->link_rate, &n_entries);
> +                                     intel_dp->link_rate, &n_entries);

This is a good example of a potential trap that having IS_ELKHARTLAKE()
cover both ELK and JSP creates. An unsuspecting coder might change the
if ladder to have IS_ELKHARTLAKE() first, and the subsequent
IS_JASPERLAKE() branch would never be taken.

BR,
Jani.

Tejas : In that case I will put attention note in comment about platform checks such that ladder distrubance can be avoided. What you suggest?

>                else if (intel_phy_is_combo(dev_priv, phy))
>                        icl_get_combo_buf_trans(encoder, encoder->type,
>                                                intel_dp->link_rate, &n_entries);
> @@ -2454,6 +2512,9 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
>        if (INTEL_GEN(dev_priv) >= 12)
>                ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
>                                                           &n_entries);
> +     else if (IS_JASPERLAKE(dev_priv))
> +             ddi_translations = jsl_get_combo_buf_trans(encoder, type, rate,
> +                                                        &n_entries);
>        else if (IS_ELKHARTLAKE(dev_priv))
>                ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
>                                                           &n_entries);

--
Jani Nikula, Intel Open Source Graphics Center

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28 16:31       ` [Intel-gfx] " Surendrakumar Upadhyay, TejaskumarX
  (?)
@ 2020-09-28 17:14         ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:14 UTC (permalink / raw)
  To: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, De Marchi, Lucas, Pandey,
	Hariom

On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> ________________________________
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, September 28, 2020 7:07 PM
> To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

Please fix your email quoting when interacting on the public lists.

>
> On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> Split the basic platform definition, macros, and PCI IDs to
>> differentiate between EHL and JSL platforms.
>>
>> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>  include/drm/i915_pciids.h                | 9 ++++++---
>>  5 files changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 72a9449b674e..4f20acebb038 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
>> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
>> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
>
> I think we've learned from history that we want the platform checks to
> be independent. I.e. if you need to split ELK and JSP, you need to make
> IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
>
> We've been here before, and we've thought before that we can get by with
> the minimal change. It's just postponing the inevitable and generates
> confusion.
>
> BR,
> Jani.
>
> Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> make lot of changes at each place. To avoid huge change and to
> differentiate between platforms we have taken this way. Do you think
> we still change it everywhere? Do you have example where it can harm
> this change?

If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
must mean only ELK and IS_JASPERLAKE() must mean only JSP.

It's non-negotiable. We've made the mistake before, we're not doing it
again.

There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
the alternative is worse.


BR,
Jani.


>
>>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 366ddfc8df6b..8690b69fcf33 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>>        .ppgtt_size = 36,
>>  };
>>
>> +static const struct intel_device_info jsl_info = {
>> +     GEN11_FEATURES,
>> +     PLATFORM(INTEL_JASPERLAKE),
>> +     .require_force_probe = 1,
>> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>> +     .ppgtt_size = 36,
>> +};
>> +
>>  #define GEN12_FEATURES \
>>        GEN11_FEATURES, \
>>        GEN(12), \
>> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>>        INTEL_CNL_IDS(&cnl_info),
>>        INTEL_ICL_11_IDS(&icl_info),
>>        INTEL_EHL_IDS(&ehl_info),
>> +     INTEL_JSL_IDS(&jsl_info),
>>        INTEL_TGL_12_IDS(&tgl_info),
>>        INTEL_RKL_IDS(&rkl_info),
>>        {0, 0, 0}
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index adc836f15fde..e67cec8fa2aa 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>>        PLATFORM_NAME(CANNONLAKE),
>>        PLATFORM_NAME(ICELAKE),
>>        PLATFORM_NAME(ELKHARTLAKE),
>> +     PLATFORM_NAME(JASPERLAKE),
>>        PLATFORM_NAME(TIGERLAKE),
>>        PLATFORM_NAME(ROCKETLAKE),
>>        PLATFORM_NAME(DG1),
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 6a3d607218aa..d92fa041c700 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -79,6 +79,7 @@ enum intel_platform {
>>        /* gen11 */
>>        INTEL_ICELAKE,
>>        INTEL_ELKHARTLAKE,
>> +     INTEL_JASPERLAKE,
>>        /* gen12 */
>>        INTEL_TIGERLAKE,
>>        INTEL_ROCKETLAKE,
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 7eeecb07c9a1..1b5e09cfa11e 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -579,15 +579,18 @@
>>        INTEL_VGA_DEVICE(0x8A51, info), \
>>        INTEL_VGA_DEVICE(0x8A5D, info)
>>
>> -/* EHL/JSL */
>> +/* EHL */
>>  #define INTEL_EHL_IDS(info) \
>>        INTEL_VGA_DEVICE(0x4500, info), \
>>        INTEL_VGA_DEVICE(0x4571, info), \
>>        INTEL_VGA_DEVICE(0x4551, info), \
>>        INTEL_VGA_DEVICE(0x4541, info), \
>> -     INTEL_VGA_DEVICE(0x4E71, info), \
>>        INTEL_VGA_DEVICE(0x4557, info), \
>> -     INTEL_VGA_DEVICE(0x4555, info), \
>> +     INTEL_VGA_DEVICE(0x4555, info)
>> +
>> +/* JSL */
>> +#define INTEL_JSL_IDS(info) \
>> +     INTEL_VGA_DEVICE(0x4E71, info), \
>>        INTEL_VGA_DEVICE(0x4E61, info), \
>>        INTEL_VGA_DEVICE(0x4E57, info), \
>>        INTEL_VGA_DEVICE(0x4E55, info), \
>
> --
> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:14         ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:14 UTC (permalink / raw)
  To: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, De Marchi, Lucas, Pandey,
	Hariom

On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> ________________________________
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, September 28, 2020 7:07 PM
> To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

Please fix your email quoting when interacting on the public lists.

>
> On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> Split the basic platform definition, macros, and PCI IDs to
>> differentiate between EHL and JSL platforms.
>>
>> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>  include/drm/i915_pciids.h                | 9 ++++++---
>>  5 files changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 72a9449b674e..4f20acebb038 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
>> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
>> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
>
> I think we've learned from history that we want the platform checks to
> be independent. I.e. if you need to split ELK and JSP, you need to make
> IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
>
> We've been here before, and we've thought before that we can get by with
> the minimal change. It's just postponing the inevitable and generates
> confusion.
>
> BR,
> Jani.
>
> Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> make lot of changes at each place. To avoid huge change and to
> differentiate between platforms we have taken this way. Do you think
> we still change it everywhere? Do you have example where it can harm
> this change?

If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
must mean only ELK and IS_JASPERLAKE() must mean only JSP.

It's non-negotiable. We've made the mistake before, we're not doing it
again.

There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
the alternative is worse.


BR,
Jani.


>
>>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 366ddfc8df6b..8690b69fcf33 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>>        .ppgtt_size = 36,
>>  };
>>
>> +static const struct intel_device_info jsl_info = {
>> +     GEN11_FEATURES,
>> +     PLATFORM(INTEL_JASPERLAKE),
>> +     .require_force_probe = 1,
>> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>> +     .ppgtt_size = 36,
>> +};
>> +
>>  #define GEN12_FEATURES \
>>        GEN11_FEATURES, \
>>        GEN(12), \
>> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>>        INTEL_CNL_IDS(&cnl_info),
>>        INTEL_ICL_11_IDS(&icl_info),
>>        INTEL_EHL_IDS(&ehl_info),
>> +     INTEL_JSL_IDS(&jsl_info),
>>        INTEL_TGL_12_IDS(&tgl_info),
>>        INTEL_RKL_IDS(&rkl_info),
>>        {0, 0, 0}
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index adc836f15fde..e67cec8fa2aa 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>>        PLATFORM_NAME(CANNONLAKE),
>>        PLATFORM_NAME(ICELAKE),
>>        PLATFORM_NAME(ELKHARTLAKE),
>> +     PLATFORM_NAME(JASPERLAKE),
>>        PLATFORM_NAME(TIGERLAKE),
>>        PLATFORM_NAME(ROCKETLAKE),
>>        PLATFORM_NAME(DG1),
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 6a3d607218aa..d92fa041c700 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -79,6 +79,7 @@ enum intel_platform {
>>        /* gen11 */
>>        INTEL_ICELAKE,
>>        INTEL_ELKHARTLAKE,
>> +     INTEL_JASPERLAKE,
>>        /* gen12 */
>>        INTEL_TIGERLAKE,
>>        INTEL_ROCKETLAKE,
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 7eeecb07c9a1..1b5e09cfa11e 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -579,15 +579,18 @@
>>        INTEL_VGA_DEVICE(0x8A51, info), \
>>        INTEL_VGA_DEVICE(0x8A5D, info)
>>
>> -/* EHL/JSL */
>> +/* EHL */
>>  #define INTEL_EHL_IDS(info) \
>>        INTEL_VGA_DEVICE(0x4500, info), \
>>        INTEL_VGA_DEVICE(0x4571, info), \
>>        INTEL_VGA_DEVICE(0x4551, info), \
>>        INTEL_VGA_DEVICE(0x4541, info), \
>> -     INTEL_VGA_DEVICE(0x4E71, info), \
>>        INTEL_VGA_DEVICE(0x4557, info), \
>> -     INTEL_VGA_DEVICE(0x4555, info), \
>> +     INTEL_VGA_DEVICE(0x4555, info)
>> +
>> +/* JSL */
>> +#define INTEL_JSL_IDS(info) \
>> +     INTEL_VGA_DEVICE(0x4E71, info), \
>>        INTEL_VGA_DEVICE(0x4E61, info), \
>>        INTEL_VGA_DEVICE(0x4E57, info), \
>>        INTEL_VGA_DEVICE(0x4E55, info), \
>
> --
> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:14         ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:14 UTC (permalink / raw)
  To: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, De Marchi, Lucas, Pandey,
	Hariom

On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> ________________________________
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, September 28, 2020 7:07 PM
> To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

Please fix your email quoting when interacting on the public lists.

>
> On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> Split the basic platform definition, macros, and PCI IDs to
>> differentiate between EHL and JSL platforms.
>>
>> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
>>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
>>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
>>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>  include/drm/i915_pciids.h                | 9 ++++++---
>>  5 files changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 72a9449b674e..4f20acebb038 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
>>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
>>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
>> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
>> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
>> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
>
> I think we've learned from history that we want the platform checks to
> be independent. I.e. if you need to split ELK and JSP, you need to make
> IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
>
> We've been here before, and we've thought before that we can get by with
> the minimal change. It's just postponing the inevitable and generates
> confusion.
>
> BR,
> Jani.
>
> Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> make lot of changes at each place. To avoid huge change and to
> differentiate between platforms we have taken this way. Do you think
> we still change it everywhere? Do you have example where it can harm
> this change?

If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
must mean only ELK and IS_JASPERLAKE() must mean only JSP.

It's non-negotiable. We've made the mistake before, we're not doing it
again.

There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
the alternative is worse.


BR,
Jani.


>
>>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
>>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
>>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 366ddfc8df6b..8690b69fcf33 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
>>        .ppgtt_size = 36,
>>  };
>>
>> +static const struct intel_device_info jsl_info = {
>> +     GEN11_FEATURES,
>> +     PLATFORM(INTEL_JASPERLAKE),
>> +     .require_force_probe = 1,
>> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
>> +     .ppgtt_size = 36,
>> +};
>> +
>>  #define GEN12_FEATURES \
>>        GEN11_FEATURES, \
>>        GEN(12), \
>> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
>>        INTEL_CNL_IDS(&cnl_info),
>>        INTEL_ICL_11_IDS(&icl_info),
>>        INTEL_EHL_IDS(&ehl_info),
>> +     INTEL_JSL_IDS(&jsl_info),
>>        INTEL_TGL_12_IDS(&tgl_info),
>>        INTEL_RKL_IDS(&rkl_info),
>>        {0, 0, 0}
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index adc836f15fde..e67cec8fa2aa 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
>>        PLATFORM_NAME(CANNONLAKE),
>>        PLATFORM_NAME(ICELAKE),
>>        PLATFORM_NAME(ELKHARTLAKE),
>> +     PLATFORM_NAME(JASPERLAKE),
>>        PLATFORM_NAME(TIGERLAKE),
>>        PLATFORM_NAME(ROCKETLAKE),
>>        PLATFORM_NAME(DG1),
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 6a3d607218aa..d92fa041c700 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -79,6 +79,7 @@ enum intel_platform {
>>        /* gen11 */
>>        INTEL_ICELAKE,
>>        INTEL_ELKHARTLAKE,
>> +     INTEL_JASPERLAKE,
>>        /* gen12 */
>>        INTEL_TIGERLAKE,
>>        INTEL_ROCKETLAKE,
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 7eeecb07c9a1..1b5e09cfa11e 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -579,15 +579,18 @@
>>        INTEL_VGA_DEVICE(0x8A51, info), \
>>        INTEL_VGA_DEVICE(0x8A5D, info)
>>
>> -/* EHL/JSL */
>> +/* EHL */
>>  #define INTEL_EHL_IDS(info) \
>>        INTEL_VGA_DEVICE(0x4500, info), \
>>        INTEL_VGA_DEVICE(0x4571, info), \
>>        INTEL_VGA_DEVICE(0x4551, info), \
>>        INTEL_VGA_DEVICE(0x4541, info), \
>> -     INTEL_VGA_DEVICE(0x4E71, info), \
>>        INTEL_VGA_DEVICE(0x4557, info), \
>> -     INTEL_VGA_DEVICE(0x4555, info), \
>> +     INTEL_VGA_DEVICE(0x4555, info)
>> +
>> +/* JSL */
>> +#define INTEL_JSL_IDS(info) \
>> +     INTEL_VGA_DEVICE(0x4E71, info), \
>>        INTEL_VGA_DEVICE(0x4E61, info), \
>>        INTEL_VGA_DEVICE(0x4E57, info), \
>>        INTEL_VGA_DEVICE(0x4E55, info), \
>
> --
> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 16:34       ` Surendrakumar Upadhyay, TejaskumarX
  (?)
@ 2020-09-28 17:15         ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:15 UTC (permalink / raw)
  To: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, De Marchi, Lucas, Pandey,
	Hariom

On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> This is a good example of a potential trap that having
> IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
> might change the if ladder to have IS_ELKHARTLAKE() first, and the
> subsequent IS_JASPERLAKE() branch would never be taken.
>
> BR,
> Jani.
>
> Tejas : In that case I will put attention note in comment about
> platform checks such that ladder distrubance can be avoided. What you
> suggest?

The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 17:15         ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:15 UTC (permalink / raw)
  To: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, De Marchi, Lucas, Pandey,
	Hariom

On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> This is a good example of a potential trap that having
> IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
> might change the if ladder to have IS_ELKHARTLAKE() first, and the
> subsequent IS_JASPERLAKE() branch would never be taken.
>
> BR,
> Jani.
>
> Tejas : In that case I will put attention note in comment about
> platform checks such that ladder distrubance can be avoided. What you
> suggest?

The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 17:15         ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:15 UTC (permalink / raw)
  To: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, De Marchi, Lucas, Pandey,
	Hariom

On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> This is a good example of a potential trap that having
> IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
> might change the if ladder to have IS_ELKHARTLAKE() first, and the
> subsequent IS_JASPERLAKE() branch would never be taken.
>
> BR,
> Jani.
>
> Tejas : In that case I will put attention note in comment about
> platform checks such that ladder distrubance can be avoided. What you
> suggest?

The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 15:02         ` Ville Syrjälä
  (?)
@ 2020-09-28 17:20           ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:20 UTC (permalink / raw)
  To: Ville Syrjälä, James Ausmus
  Cc: Tejas Upadhyay, rodrigo.vivi, airlied, daniel, intel-gfx,
	dri-devel, linux-kernel, matthew.d.roper, jose.souza,
	lucas.demarchi, hariom.pandey

On Mon, 28 Sep 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
>> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
>> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> > > JSL has update in vswing table for eDP
>> > 
>> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
>> > PCH_JSP for Jasper Lake PCH.
>> 
>> JSP == Point (the PCH), JSL == Lake
>
> .PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.

Yeah, nowadays it doesn't have "Point", however bspec agrees on the JSL
acronym for Jasper Lake.

Which means we should probably use PCH_JSL for Jasper Lake PCH as
well. Ugh.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 17:20           ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:20 UTC (permalink / raw)
  To: Ville Syrjälä, James Ausmus
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel, jose.souza, rodrigo.vivi, Tejas Upadhyay

On Mon, 28 Sep 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
>> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
>> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> > > JSL has update in vswing table for eDP
>> > 
>> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
>> > PCH_JSP for Jasper Lake PCH.
>> 
>> JSP == Point (the PCH), JSL == Lake
>
> .PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.

Yeah, nowadays it doesn't have "Point", however bspec agrees on the JSL
acronym for Jasper Lake.

Which means we should probably use PCH_JSL for Jasper Lake PCH as
well. Ugh.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 17:20           ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:20 UTC (permalink / raw)
  To: Ville Syrjälä, James Ausmus
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel

On Mon, 28 Sep 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
>> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
>> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> > > JSL has update in vswing table for eDP
>> > 
>> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
>> > PCH_JSP for Jasper Lake PCH.
>> 
>> JSP == Point (the PCH), JSL == Lake
>
> .PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.

Yeah, nowadays it doesn't have "Point", however bspec agrees on the JSL
acronym for Jasper Lake.

Which means we should probably use PCH_JSL for Jasper Lake PCH as
well. Ugh.


BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28 17:14         ` Jani Nikula
  (?)
@ 2020-09-28 17:24           ` Matt Roper
  -1 siblings, 0 replies; 58+ messages in thread
From: Matt Roper @ 2020-09-28 17:24 UTC (permalink / raw)
  To: Jani Nikula
  Cc: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Souza,
	Jose, ville.syrjala, De Marchi, Lucas, Pandey, Hariom

On Mon, Sep 28, 2020 at 08:14:02PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > ________________________________
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Monday, September 28, 2020 7:07 PM
> > To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> > Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
> 
> Please fix your email quoting when interacting on the public lists.
> 
> >
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> Split the basic platform definition, macros, and PCI IDs to
> >> differentiate between EHL and JSL platforms.
> >>
> >> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
> >>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
> >>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >>  include/drm/i915_pciids.h                | 9 ++++++---
> >>  5 files changed, 20 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 72a9449b674e..4f20acebb038 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> >>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> >>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> >> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> >> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> >> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> >> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
> >
> > I think we've learned from history that we want the platform checks to
> > be independent. I.e. if you need to split ELK and JSP, you need to make
> > IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> > IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
> >
> > We've been here before, and we've thought before that we can get by with
> > the minimal change. It's just postponing the inevitable and generates
> > confusion.
> >
> > BR,
> > Jani.
> >
> > Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> > make lot of changes at each place. To avoid huge change and to
> > differentiate between platforms we have taken this way. Do you think
> > we still change it everywhere? Do you have example where it can harm
> > this change?
> 
> If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
> must mean only ELK and IS_JASPERLAKE() must mean only JSP.
> 
> It's non-negotiable. We've made the mistake before, we're not doing it
> again.
> 
> There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
> the alternative is worse.

Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
same graphics IP, but are paired with different PCHs in the final SoCs,
which is what causes the minor differences in programming.  My
understanding is that the voltage programming differences are ultimately
due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
rather than using a platform test.


Matt

> 
> 
> BR,
> Jani.
> 
> 
> >
> >>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> >>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> >>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> >> index 366ddfc8df6b..8690b69fcf33 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
> >>        .ppgtt_size = 36,
> >>  };
> >>
> >> +static const struct intel_device_info jsl_info = {
> >> +     GEN11_FEATURES,
> >> +     PLATFORM(INTEL_JASPERLAKE),
> >> +     .require_force_probe = 1,
> >> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> >> +     .ppgtt_size = 36,
> >> +};
> >> +
> >>  #define GEN12_FEATURES \
> >>        GEN11_FEATURES, \
> >>        GEN(12), \
> >> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
> >>        INTEL_CNL_IDS(&cnl_info),
> >>        INTEL_ICL_11_IDS(&icl_info),
> >>        INTEL_EHL_IDS(&ehl_info),
> >> +     INTEL_JSL_IDS(&jsl_info),
> >>        INTEL_TGL_12_IDS(&tgl_info),
> >>        INTEL_RKL_IDS(&rkl_info),
> >>        {0, 0, 0}
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index adc836f15fde..e67cec8fa2aa 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
> >>        PLATFORM_NAME(CANNONLAKE),
> >>        PLATFORM_NAME(ICELAKE),
> >>        PLATFORM_NAME(ELKHARTLAKE),
> >> +     PLATFORM_NAME(JASPERLAKE),
> >>        PLATFORM_NAME(TIGERLAKE),
> >>        PLATFORM_NAME(ROCKETLAKE),
> >>        PLATFORM_NAME(DG1),
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index 6a3d607218aa..d92fa041c700 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -79,6 +79,7 @@ enum intel_platform {
> >>        /* gen11 */
> >>        INTEL_ICELAKE,
> >>        INTEL_ELKHARTLAKE,
> >> +     INTEL_JASPERLAKE,
> >>        /* gen12 */
> >>        INTEL_TIGERLAKE,
> >>        INTEL_ROCKETLAKE,
> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> >> index 7eeecb07c9a1..1b5e09cfa11e 100644
> >> --- a/include/drm/i915_pciids.h
> >> +++ b/include/drm/i915_pciids.h
> >> @@ -579,15 +579,18 @@
> >>        INTEL_VGA_DEVICE(0x8A51, info), \
> >>        INTEL_VGA_DEVICE(0x8A5D, info)
> >>
> >> -/* EHL/JSL */
> >> +/* EHL */
> >>  #define INTEL_EHL_IDS(info) \
> >>        INTEL_VGA_DEVICE(0x4500, info), \
> >>        INTEL_VGA_DEVICE(0x4571, info), \
> >>        INTEL_VGA_DEVICE(0x4551, info), \
> >>        INTEL_VGA_DEVICE(0x4541, info), \
> >> -     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4557, info), \
> >> -     INTEL_VGA_DEVICE(0x4555, info), \
> >> +     INTEL_VGA_DEVICE(0x4555, info)
> >> +
> >> +/* JSL */
> >> +#define INTEL_JSL_IDS(info) \
> >> +     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4E61, info), \
> >>        INTEL_VGA_DEVICE(0x4E57, info), \
> >>        INTEL_VGA_DEVICE(0x4E55, info), \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:24           ` Matt Roper
  0 siblings, 0 replies; 58+ messages in thread
From: Matt Roper @ 2020-09-28 17:24 UTC (permalink / raw)
  To: Jani Nikula
  Cc: Pandey, Hariom, Ausmus, James, airlied, intel-gfx, De Marchi,
	Lucas, linux-kernel, dri-devel, Souza, Jose, Vivi, Rodrigo,
	Surendrakumar Upadhyay, TejaskumarX

On Mon, Sep 28, 2020 at 08:14:02PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > ________________________________
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Monday, September 28, 2020 7:07 PM
> > To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> > Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
> 
> Please fix your email quoting when interacting on the public lists.
> 
> >
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> Split the basic platform definition, macros, and PCI IDs to
> >> differentiate between EHL and JSL platforms.
> >>
> >> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
> >>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
> >>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >>  include/drm/i915_pciids.h                | 9 ++++++---
> >>  5 files changed, 20 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 72a9449b674e..4f20acebb038 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> >>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> >>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> >> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> >> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> >> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> >> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
> >
> > I think we've learned from history that we want the platform checks to
> > be independent. I.e. if you need to split ELK and JSP, you need to make
> > IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> > IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
> >
> > We've been here before, and we've thought before that we can get by with
> > the minimal change. It's just postponing the inevitable and generates
> > confusion.
> >
> > BR,
> > Jani.
> >
> > Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> > make lot of changes at each place. To avoid huge change and to
> > differentiate between platforms we have taken this way. Do you think
> > we still change it everywhere? Do you have example where it can harm
> > this change?
> 
> If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
> must mean only ELK and IS_JASPERLAKE() must mean only JSP.
> 
> It's non-negotiable. We've made the mistake before, we're not doing it
> again.
> 
> There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
> the alternative is worse.

Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
same graphics IP, but are paired with different PCHs in the final SoCs,
which is what causes the minor differences in programming.  My
understanding is that the voltage programming differences are ultimately
due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
rather than using a platform test.


Matt

> 
> 
> BR,
> Jani.
> 
> 
> >
> >>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> >>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> >>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> >> index 366ddfc8df6b..8690b69fcf33 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
> >>        .ppgtt_size = 36,
> >>  };
> >>
> >> +static const struct intel_device_info jsl_info = {
> >> +     GEN11_FEATURES,
> >> +     PLATFORM(INTEL_JASPERLAKE),
> >> +     .require_force_probe = 1,
> >> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> >> +     .ppgtt_size = 36,
> >> +};
> >> +
> >>  #define GEN12_FEATURES \
> >>        GEN11_FEATURES, \
> >>        GEN(12), \
> >> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
> >>        INTEL_CNL_IDS(&cnl_info),
> >>        INTEL_ICL_11_IDS(&icl_info),
> >>        INTEL_EHL_IDS(&ehl_info),
> >> +     INTEL_JSL_IDS(&jsl_info),
> >>        INTEL_TGL_12_IDS(&tgl_info),
> >>        INTEL_RKL_IDS(&rkl_info),
> >>        {0, 0, 0}
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index adc836f15fde..e67cec8fa2aa 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
> >>        PLATFORM_NAME(CANNONLAKE),
> >>        PLATFORM_NAME(ICELAKE),
> >>        PLATFORM_NAME(ELKHARTLAKE),
> >> +     PLATFORM_NAME(JASPERLAKE),
> >>        PLATFORM_NAME(TIGERLAKE),
> >>        PLATFORM_NAME(ROCKETLAKE),
> >>        PLATFORM_NAME(DG1),
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index 6a3d607218aa..d92fa041c700 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -79,6 +79,7 @@ enum intel_platform {
> >>        /* gen11 */
> >>        INTEL_ICELAKE,
> >>        INTEL_ELKHARTLAKE,
> >> +     INTEL_JASPERLAKE,
> >>        /* gen12 */
> >>        INTEL_TIGERLAKE,
> >>        INTEL_ROCKETLAKE,
> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> >> index 7eeecb07c9a1..1b5e09cfa11e 100644
> >> --- a/include/drm/i915_pciids.h
> >> +++ b/include/drm/i915_pciids.h
> >> @@ -579,15 +579,18 @@
> >>        INTEL_VGA_DEVICE(0x8A51, info), \
> >>        INTEL_VGA_DEVICE(0x8A5D, info)
> >>
> >> -/* EHL/JSL */
> >> +/* EHL */
> >>  #define INTEL_EHL_IDS(info) \
> >>        INTEL_VGA_DEVICE(0x4500, info), \
> >>        INTEL_VGA_DEVICE(0x4571, info), \
> >>        INTEL_VGA_DEVICE(0x4551, info), \
> >>        INTEL_VGA_DEVICE(0x4541, info), \
> >> -     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4557, info), \
> >> -     INTEL_VGA_DEVICE(0x4555, info), \
> >> +     INTEL_VGA_DEVICE(0x4555, info)
> >> +
> >> +/* JSL */
> >> +#define INTEL_JSL_IDS(info) \
> >> +     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4E61, info), \
> >>        INTEL_VGA_DEVICE(0x4E57, info), \
> >>        INTEL_VGA_DEVICE(0x4E55, info), \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:24           ` Matt Roper
  0 siblings, 0 replies; 58+ messages in thread
From: Matt Roper @ 2020-09-28 17:24 UTC (permalink / raw)
  To: Jani Nikula
  Cc: Pandey, Hariom, airlied, intel-gfx, De Marchi, Lucas,
	linux-kernel, dri-devel

On Mon, Sep 28, 2020 at 08:14:02PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > ________________________________
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Monday, September 28, 2020 7:07 PM
> > To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> > Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
> 
> Please fix your email quoting when interacting on the public lists.
> 
> >
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> Split the basic platform definition, macros, and PCI IDs to
> >> differentiate between EHL and JSL platforms.
> >>
> >> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
> >>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
> >>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >>  include/drm/i915_pciids.h                | 9 ++++++---
> >>  5 files changed, 20 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 72a9449b674e..4f20acebb038 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> >>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> >>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> >> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> >> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> >> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> >> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
> >
> > I think we've learned from history that we want the platform checks to
> > be independent. I.e. if you need to split ELK and JSP, you need to make
> > IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> > IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
> >
> > We've been here before, and we've thought before that we can get by with
> > the minimal change. It's just postponing the inevitable and generates
> > confusion.
> >
> > BR,
> > Jani.
> >
> > Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> > make lot of changes at each place. To avoid huge change and to
> > differentiate between platforms we have taken this way. Do you think
> > we still change it everywhere? Do you have example where it can harm
> > this change?
> 
> If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
> must mean only ELK and IS_JASPERLAKE() must mean only JSP.
> 
> It's non-negotiable. We've made the mistake before, we're not doing it
> again.
> 
> There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
> the alternative is worse.

Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
same graphics IP, but are paired with different PCHs in the final SoCs,
which is what causes the minor differences in programming.  My
understanding is that the voltage programming differences are ultimately
due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
rather than using a platform test.


Matt

> 
> 
> BR,
> Jani.
> 
> 
> >
> >>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> >>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> >>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> >> index 366ddfc8df6b..8690b69fcf33 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
> >>        .ppgtt_size = 36,
> >>  };
> >>
> >> +static const struct intel_device_info jsl_info = {
> >> +     GEN11_FEATURES,
> >> +     PLATFORM(INTEL_JASPERLAKE),
> >> +     .require_force_probe = 1,
> >> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> >> +     .ppgtt_size = 36,
> >> +};
> >> +
> >>  #define GEN12_FEATURES \
> >>        GEN11_FEATURES, \
> >>        GEN(12), \
> >> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
> >>        INTEL_CNL_IDS(&cnl_info),
> >>        INTEL_ICL_11_IDS(&icl_info),
> >>        INTEL_EHL_IDS(&ehl_info),
> >> +     INTEL_JSL_IDS(&jsl_info),
> >>        INTEL_TGL_12_IDS(&tgl_info),
> >>        INTEL_RKL_IDS(&rkl_info),
> >>        {0, 0, 0}
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index adc836f15fde..e67cec8fa2aa 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
> >>        PLATFORM_NAME(CANNONLAKE),
> >>        PLATFORM_NAME(ICELAKE),
> >>        PLATFORM_NAME(ELKHARTLAKE),
> >> +     PLATFORM_NAME(JASPERLAKE),
> >>        PLATFORM_NAME(TIGERLAKE),
> >>        PLATFORM_NAME(ROCKETLAKE),
> >>        PLATFORM_NAME(DG1),
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index 6a3d607218aa..d92fa041c700 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -79,6 +79,7 @@ enum intel_platform {
> >>        /* gen11 */
> >>        INTEL_ICELAKE,
> >>        INTEL_ELKHARTLAKE,
> >> +     INTEL_JASPERLAKE,
> >>        /* gen12 */
> >>        INTEL_TIGERLAKE,
> >>        INTEL_ROCKETLAKE,
> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> >> index 7eeecb07c9a1..1b5e09cfa11e 100644
> >> --- a/include/drm/i915_pciids.h
> >> +++ b/include/drm/i915_pciids.h
> >> @@ -579,15 +579,18 @@
> >>        INTEL_VGA_DEVICE(0x8A51, info), \
> >>        INTEL_VGA_DEVICE(0x8A5D, info)
> >>
> >> -/* EHL/JSL */
> >> +/* EHL */
> >>  #define INTEL_EHL_IDS(info) \
> >>        INTEL_VGA_DEVICE(0x4500, info), \
> >>        INTEL_VGA_DEVICE(0x4571, info), \
> >>        INTEL_VGA_DEVICE(0x4551, info), \
> >>        INTEL_VGA_DEVICE(0x4541, info), \
> >> -     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4557, info), \
> >> -     INTEL_VGA_DEVICE(0x4555, info), \
> >> +     INTEL_VGA_DEVICE(0x4555, info)
> >> +
> >> +/* JSL */
> >> +#define INTEL_JSL_IDS(info) \
> >> +     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4E61, info), \
> >>        INTEL_VGA_DEVICE(0x4E57, info), \
> >>        INTEL_VGA_DEVICE(0x4E55, info), \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28 17:24           ` Matt Roper
@ 2020-09-28 17:30             ` Surendrakumar Upadhyay, TejaskumarX
  -1 siblings, 0 replies; 58+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2020-09-28 17:30 UTC (permalink / raw)
  To: Roper, Matthew D, Jani Nikula
  Cc: Pandey, Hariom, Ausmus, James, airlied, intel-gfx, De Marchi,
	Lucas, linux-kernel, dri-devel, Souza, Jose, Vivi, Rodrigo


[-- Attachment #1.1: Type: text/plain, Size: 8962 bytes --]



________________________________
From: Matt Roper <matthew.d.roper@intel.com>
Sent: Monday, September 28, 2020 10:54 PM
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

On Mon, Sep 28, 2020 at 08:14:02PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > ________________________________
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Monday, September 28, 2020 7:07 PM
> > To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> > Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
>
> Please fix your email quoting when interacting on the public lists.
>
> >
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> Split the basic platform definition, macros, and PCI IDs to
> >> differentiate between EHL and JSL platforms.
> >>
> >> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
> >>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
> >>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >>  include/drm/i915_pciids.h                | 9 ++++++---
> >>  5 files changed, 20 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 72a9449b674e..4f20acebb038 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> >>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> >>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> >> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> >> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> >> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> >> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
> >
> > I think we've learned from history that we want the platform checks to
> > be independent. I.e. if you need to split ELK and JSP, you need to make
> > IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> > IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
> >
> > We've been here before, and we've thought before that we can get by with
> > the minimal change. It's just postponing the inevitable and generates
> > confusion.
> >
> > BR,
> > Jani.
> >
> > Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> > make lot of changes at each place. To avoid huge change and to
> > differentiate between platforms we have taken this way. Do you think
> > we still change it everywhere? Do you have example where it can harm
> > this change?
>
> If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
> must mean only ELK and IS_JASPERLAKE() must mean only JSP.
>
> It's non-negotiable. We've made the mistake before, we're not doing it
> again.
>
> There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
> the alternative is worse.

Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
same graphics IP, but are paired with different PCHs in the final SoCs,
which is what causes the minor differences in programming.  My
understanding is that the voltage programming differences are ultimately
due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
rather than using a platform test.


Matt

Thanks for pointing out this Matt. I can change accordingly and send V2.

Tejas
>
>
> BR,
> Jani.
>
>
> >
> >>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> >>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> >>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> >> index 366ddfc8df6b..8690b69fcf33 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
> >>        .ppgtt_size = 36,
> >>  };
> >>
> >> +static const struct intel_device_info jsl_info = {
> >> +     GEN11_FEATURES,
> >> +     PLATFORM(INTEL_JASPERLAKE),
> >> +     .require_force_probe = 1,
> >> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> >> +     .ppgtt_size = 36,
> >> +};
> >> +
> >>  #define GEN12_FEATURES \
> >>        GEN11_FEATURES, \
> >>        GEN(12), \
> >> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
> >>        INTEL_CNL_IDS(&cnl_info),
> >>        INTEL_ICL_11_IDS(&icl_info),
> >>        INTEL_EHL_IDS(&ehl_info),
> >> +     INTEL_JSL_IDS(&jsl_info),
> >>        INTEL_TGL_12_IDS(&tgl_info),
> >>        INTEL_RKL_IDS(&rkl_info),
> >>        {0, 0, 0}
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index adc836f15fde..e67cec8fa2aa 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
> >>        PLATFORM_NAME(CANNONLAKE),
> >>        PLATFORM_NAME(ICELAKE),
> >>        PLATFORM_NAME(ELKHARTLAKE),
> >> +     PLATFORM_NAME(JASPERLAKE),
> >>        PLATFORM_NAME(TIGERLAKE),
> >>        PLATFORM_NAME(ROCKETLAKE),
> >>        PLATFORM_NAME(DG1),
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index 6a3d607218aa..d92fa041c700 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -79,6 +79,7 @@ enum intel_platform {
> >>        /* gen11 */
> >>        INTEL_ICELAKE,
> >>        INTEL_ELKHARTLAKE,
> >> +     INTEL_JASPERLAKE,
> >>        /* gen12 */
> >>        INTEL_TIGERLAKE,
> >>        INTEL_ROCKETLAKE,
> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> >> index 7eeecb07c9a1..1b5e09cfa11e 100644
> >> --- a/include/drm/i915_pciids.h
> >> +++ b/include/drm/i915_pciids.h
> >> @@ -579,15 +579,18 @@
> >>        INTEL_VGA_DEVICE(0x8A51, info), \
> >>        INTEL_VGA_DEVICE(0x8A5D, info)
> >>
> >> -/* EHL/JSL */
> >> +/* EHL */
> >>  #define INTEL_EHL_IDS(info) \
> >>        INTEL_VGA_DEVICE(0x4500, info), \
> >>        INTEL_VGA_DEVICE(0x4571, info), \
> >>        INTEL_VGA_DEVICE(0x4551, info), \
> >>        INTEL_VGA_DEVICE(0x4541, info), \
> >> -     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4557, info), \
> >> -     INTEL_VGA_DEVICE(0x4555, info), \
> >> +     INTEL_VGA_DEVICE(0x4555, info)
> >> +
> >> +/* JSL */
> >> +#define INTEL_JSL_IDS(info) \
> >> +     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4E61, info), \
> >>        INTEL_VGA_DEVICE(0x4E57, info), \
> >>        INTEL_VGA_DEVICE(0x4E55, info), \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center

--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

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_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:30             ` Surendrakumar Upadhyay, TejaskumarX
  0 siblings, 0 replies; 58+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2020-09-28 17:30 UTC (permalink / raw)
  To: Roper, Matthew D, Jani Nikula
  Cc: Pandey, Hariom, airlied, intel-gfx, De Marchi, Lucas,
	linux-kernel, dri-devel


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________________________________
From: Matt Roper <matthew.d.roper@intel.com>
Sent: Monday, September 28, 2020 10:54 PM
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

On Mon, Sep 28, 2020 at 08:14:02PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX" <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > ________________________________
> > From: Jani Nikula <jani.nikula@linux.intel.com>
> > Sent: Monday, September 28, 2020 7:07 PM
> > To: Surendrakumar Upadhyay, TejaskumarX <tejaskumarx.surendrakumar.upadhyay@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>; airlied@linux.ie <airlied@linux.ie>; daniel@ffwll.ch <daniel@ffwll.ch>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; Ausmus, James <james.ausmus@intel.com>; Roper, Matthew D <matthew.d.roper@intel.com>; Souza, Jose <jose.souza@intel.com>; ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com>; Pandey, Hariom <hariom.pandey@intel.com>
> > Subject: Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
>
> Please fix your email quoting when interacting on the public lists.
>
> >
> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> Split the basic platform definition, macros, and PCI IDs to
> >> differentiate between EHL and JSL platforms.
> >>
> >> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_drv.h          | 4 +++-
> >>  drivers/gpu/drm/i915/i915_pci.c          | 9 +++++++++
> >>  drivers/gpu/drm/i915/intel_device_info.c | 1 +
> >>  drivers/gpu/drm/i915/intel_device_info.h | 1 +
> >>  include/drm/i915_pciids.h                | 9 ++++++---
> >>  5 files changed, 20 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >> index 72a9449b674e..4f20acebb038 100644
> >> --- a/drivers/gpu/drm/i915/i915_drv.h
> >> +++ b/drivers/gpu/drm/i915/i915_drv.h
> >> @@ -1417,7 +1417,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >>  #define IS_COMETLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> >>  #define IS_CANNONLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> >>  #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> >> -#define IS_ELKHARTLAKE(dev_priv)     IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)
> >> +#define IS_ELKHARTLAKE(dev_priv) (IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) || \
> >> +                             IS_PLATFORM(dev_priv, INTEL_JASPERLAKE))
> >> +#define IS_JASPERLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_JASPERLAKE)
> >
> > I think we've learned from history that we want the platform checks to
> > be independent. I.e. if you need to split ELK and JSP, you need to make
> > IS_ELKHARTLAKE() match *only* ELK, and you need to replace every current
> > IS_ELKHARTLAKE() check with IS_ELKHARTLAKE() || IS_JASPERLAKE().
> >
> > We've been here before, and we've thought before that we can get by with
> > the minimal change. It's just postponing the inevitable and generates
> > confusion.
> >
> > BR,
> > Jani.
> >
> > Tejas : Replacing IS_ELKHARTLAKE() || IS_JASPERLAKE() everywhere will
> > make lot of changes at each place. To avoid huge change and to
> > differentiate between platforms we have taken this way. Do you think
> > we still change it everywhere? Do you have example where it can harm
> > this change?
>
> If you need to differentiate between the two platforms, IS_ELKHARTLAKE()
> must mean only ELK and IS_JASPERLAKE() must mean only JSP.
>
> It's non-negotiable. We've made the mistake before, we're not doing it
> again.
>
> There are 32 references to IS_ELKHARTLAKE(). It's slightly painful, but
> the alternative is worse.

Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
same graphics IP, but are paired with different PCHs in the final SoCs,
which is what causes the minor differences in programming.  My
understanding is that the voltage programming differences are ultimately
due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
rather than using a platform test.


Matt

Thanks for pointing out this Matt. I can change accordingly and send V2.

Tejas
>
>
> BR,
> Jani.
>
>
> >
> >>  #define IS_TIGERLAKE(dev_priv)       IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> >>  #define IS_ROCKETLAKE(dev_priv)      IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> >>  #define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> >> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> >> index 366ddfc8df6b..8690b69fcf33 100644
> >> --- a/drivers/gpu/drm/i915/i915_pci.c
> >> +++ b/drivers/gpu/drm/i915/i915_pci.c
> >> @@ -846,6 +846,14 @@ static const struct intel_device_info ehl_info = {
> >>        .ppgtt_size = 36,
> >>  };
> >>
> >> +static const struct intel_device_info jsl_info = {
> >> +     GEN11_FEATURES,
> >> +     PLATFORM(INTEL_JASPERLAKE),
> >> +     .require_force_probe = 1,
> >> +     .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> >> +     .ppgtt_size = 36,
> >> +};
> >> +
> >>  #define GEN12_FEATURES \
> >>        GEN11_FEATURES, \
> >>        GEN(12), \
> >> @@ -985,6 +993,7 @@ static const struct pci_device_id pciidlist[] = {
> >>        INTEL_CNL_IDS(&cnl_info),
> >>        INTEL_ICL_11_IDS(&icl_info),
> >>        INTEL_EHL_IDS(&ehl_info),
> >> +     INTEL_JSL_IDS(&jsl_info),
> >>        INTEL_TGL_12_IDS(&tgl_info),
> >>        INTEL_RKL_IDS(&rkl_info),
> >>        {0, 0, 0}
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> >> index adc836f15fde..e67cec8fa2aa 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -62,6 +62,7 @@ static const char * const platform_names[] = {
> >>        PLATFORM_NAME(CANNONLAKE),
> >>        PLATFORM_NAME(ICELAKE),
> >>        PLATFORM_NAME(ELKHARTLAKE),
> >> +     PLATFORM_NAME(JASPERLAKE),
> >>        PLATFORM_NAME(TIGERLAKE),
> >>        PLATFORM_NAME(ROCKETLAKE),
> >>        PLATFORM_NAME(DG1),
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> >> index 6a3d607218aa..d92fa041c700 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.h
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> >> @@ -79,6 +79,7 @@ enum intel_platform {
> >>        /* gen11 */
> >>        INTEL_ICELAKE,
> >>        INTEL_ELKHARTLAKE,
> >> +     INTEL_JASPERLAKE,
> >>        /* gen12 */
> >>        INTEL_TIGERLAKE,
> >>        INTEL_ROCKETLAKE,
> >> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> >> index 7eeecb07c9a1..1b5e09cfa11e 100644
> >> --- a/include/drm/i915_pciids.h
> >> +++ b/include/drm/i915_pciids.h
> >> @@ -579,15 +579,18 @@
> >>        INTEL_VGA_DEVICE(0x8A51, info), \
> >>        INTEL_VGA_DEVICE(0x8A5D, info)
> >>
> >> -/* EHL/JSL */
> >> +/* EHL */
> >>  #define INTEL_EHL_IDS(info) \
> >>        INTEL_VGA_DEVICE(0x4500, info), \
> >>        INTEL_VGA_DEVICE(0x4571, info), \
> >>        INTEL_VGA_DEVICE(0x4551, info), \
> >>        INTEL_VGA_DEVICE(0x4541, info), \
> >> -     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4557, info), \
> >> -     INTEL_VGA_DEVICE(0x4555, info), \
> >> +     INTEL_VGA_DEVICE(0x4555, info)
> >> +
> >> +/* JSL */
> >> +#define INTEL_JSL_IDS(info) \
> >> +     INTEL_VGA_DEVICE(0x4E71, info), \
> >>        INTEL_VGA_DEVICE(0x4E61, info), \
> >>        INTEL_VGA_DEVICE(0x4E57, info), \
> >>        INTEL_VGA_DEVICE(0x4E55, info), \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center

--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
  2020-09-28 17:24           ` Matt Roper
  (?)
@ 2020-09-28 17:32             ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:32 UTC (permalink / raw)
  To: Matt Roper
  Cc: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Souza,
	Jose, ville.syrjala, De Marchi, Lucas, Pandey, Hariom

On Mon, 28 Sep 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
> same graphics IP, but are paired with different PCHs in the final SoCs,
> which is what causes the minor differences in programming.  My
> understanding is that the voltage programming differences are ultimately
> due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
> and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
> rather than using a platform test.

Good point. If the difference is in the PCH, then of course the PCH
check should be used instead. Which avoids the problem altogether.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:32             ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:32 UTC (permalink / raw)
  To: Matt Roper
  Cc: Pandey, Hariom, Ausmus, James, airlied, intel-gfx, De Marchi,
	Lucas, linux-kernel, dri-devel, Souza, Jose, Vivi, Rodrigo,
	Surendrakumar Upadhyay, TejaskumarX

On Mon, 28 Sep 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
> same graphics IP, but are paired with different PCHs in the final SoCs,
> which is what causes the minor differences in programming.  My
> understanding is that the voltage programming differences are ultimately
> due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
> and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
> rather than using a platform test.

Good point. If the difference is in the PCH, then of course the PCH
check should be used instead. Which avoids the problem altogether.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids
@ 2020-09-28 17:32             ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-28 17:32 UTC (permalink / raw)
  To: Matt Roper
  Cc: Pandey, Hariom, airlied, intel-gfx, De Marchi, Lucas,
	linux-kernel, dri-devel

On Mon, 28 Sep 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> Why are we adding IS_JASPERLAKE at all?  EHL/JSL are documented as the
> same graphics IP, but are paired with different PCHs in the final SoCs,
> which is what causes the minor differences in programming.  My
> understanding is that the voltage programming differences are ultimately
> due to that difference in PCH so we should just use HAS_PCH_MCC (EHL)
> and HAS_PCH_JSP (JSL) to distinguish which type of programming is needed
> rather than using a platform test.

Good point. If the difference is in the PCH, then of course the PCH
check should be used instead. Which avoids the problem altogether.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 17:15         ` Jani Nikula
  (?)
@ 2020-09-28 23:07           ` Lucas De Marchi
  -1 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2020-09-28 23:07 UTC (permalink / raw)
  To: Jani Nikula
  Cc: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Roper,
	Matthew D, Souza, Jose, ville.syrjala, Pandey, Hariom

On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
>On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> This is a good example of a potential trap that having
>> IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
>> might change the if ladder to have IS_ELKHARTLAKE() first, and the
>> subsequent IS_JASPERLAKE() branch would never be taken.
>>
>> BR,
>> Jani.
>>
>> Tejas : In that case I will put attention note in comment about
>> platform checks such that ladder distrubance can be avoided. What you
>> suggest?

>The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.

Since we are talking about the TLA for JSL in the other patch, for
elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
what:

$ git grep -w ELK -- drivers/gpu/drm/
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.

Lucas De Marchi

>
>BR,
>Jani.
>
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 23:07           ` Lucas De Marchi
  0 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2020-09-28 23:07 UTC (permalink / raw)
  To: Jani Nikula
  Cc: Pandey, Hariom, Ausmus, James, airlied, intel-gfx, linux-kernel,
	dri-devel, Souza, Jose, Vivi, Rodrigo, Surendrakumar Upadhyay,
	TejaskumarX

On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
>On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> This is a good example of a potential trap that having
>> IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
>> might change the if ladder to have IS_ELKHARTLAKE() first, and the
>> subsequent IS_JASPERLAKE() branch would never be taken.
>>
>> BR,
>> Jani.
>>
>> Tejas : In that case I will put attention note in comment about
>> platform checks such that ladder distrubance can be avoided. What you
>> suggest?

>The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.

Since we are talking about the TLA for JSL in the other patch, for
elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
what:

$ git grep -w ELK -- drivers/gpu/drm/
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.

Lucas De Marchi

>
>BR,
>Jani.
>
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 23:07           ` Lucas De Marchi
  0 siblings, 0 replies; 58+ messages in thread
From: Lucas De Marchi @ 2020-09-28 23:07 UTC (permalink / raw)
  To: Jani Nikula; +Cc: Pandey, Hariom, airlied, intel-gfx, linux-kernel, dri-devel

On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
>On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> This is a good example of a potential trap that having
>> IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
>> might change the if ladder to have IS_ELKHARTLAKE() first, and the
>> subsequent IS_JASPERLAKE() branch would never be taken.
>>
>> BR,
>> Jani.
>>
>> Tejas : In that case I will put attention note in comment about
>> platform checks such that ladder distrubance can be avoided. What you
>> suggest?

>The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.

Since we are talking about the TLA for JSL in the other patch, for
elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
what:

$ git grep -w ELK -- drivers/gpu/drm/
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.

Lucas De Marchi

>
>BR,
>Jani.
>
>
>-- 
>Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 23:07           ` Lucas De Marchi
  (?)
@ 2020-09-28 23:10             ` Matt Roper
  -1 siblings, 0 replies; 58+ messages in thread
From: Matt Roper @ 2020-09-28 23:10 UTC (permalink / raw)
  To: Lucas De Marchi
  Cc: Jani Nikula, Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo,
	airlied, daniel, intel-gfx, dri-devel, linux-kernel, Ausmus,
	James, Souza, Jose, ville.syrjala, Pandey, Hariom

On Mon, Sep 28, 2020 at 04:07:39PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
> > On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > > This is a good example of a potential trap that having
> > > IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
> > > might change the if ladder to have IS_ELKHARTLAKE() first, and the
> > > subsequent IS_JASPERLAKE() branch would never be taken.
> > > 
> > > BR,
> > > Jani.
> > > 
> > > Tejas : In that case I will put attention note in comment about
> > > platform checks such that ladder distrubance can be avoided. What you
> > > suggest?
> 
> > The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.
> 
> Since we are talking about the TLA for JSL in the other patch, for
> elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
> what:
> 
> $ git grep -w ELK -- drivers/gpu/drm/
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
> drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
> drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.

Yeah, ELK = Eagle Lake, CTG = Cantiga.  Both are old gen5 platforms IIRC.


Matt

> 
> Lucas De Marchi
> 
> > 
> > BR,
> > Jani.
> > 
> > 
> > -- 
> > Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 23:10             ` Matt Roper
  0 siblings, 0 replies; 58+ messages in thread
From: Matt Roper @ 2020-09-28 23:10 UTC (permalink / raw)
  To: Lucas De Marchi
  Cc: Pandey, Hariom, Ausmus, James, airlied, intel-gfx, linux-kernel,
	dri-devel, Vivi, Rodrigo, Souza, Jose, Surendrakumar Upadhyay,
	TejaskumarX

On Mon, Sep 28, 2020 at 04:07:39PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
> > On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > > This is a good example of a potential trap that having
> > > IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
> > > might change the if ladder to have IS_ELKHARTLAKE() first, and the
> > > subsequent IS_JASPERLAKE() branch would never be taken.
> > > 
> > > BR,
> > > Jani.
> > > 
> > > Tejas : In that case I will put attention note in comment about
> > > platform checks such that ladder distrubance can be avoided. What you
> > > suggest?
> 
> > The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.
> 
> Since we are talking about the TLA for JSL in the other patch, for
> elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
> what:
> 
> $ git grep -w ELK -- drivers/gpu/drm/
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
> drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
> drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.

Yeah, ELK = Eagle Lake, CTG = Cantiga.  Both are old gen5 platforms IIRC.


Matt

> 
> Lucas De Marchi
> 
> > 
> > BR,
> > Jani.
> > 
> > 
> > -- 
> > Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-28 23:10             ` Matt Roper
  0 siblings, 0 replies; 58+ messages in thread
From: Matt Roper @ 2020-09-28 23:10 UTC (permalink / raw)
  To: Lucas De Marchi
  Cc: Pandey, Hariom, airlied, intel-gfx, linux-kernel, dri-devel

On Mon, Sep 28, 2020 at 04:07:39PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
> > On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> > > This is a good example of a potential trap that having
> > > IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
> > > might change the if ladder to have IS_ELKHARTLAKE() first, and the
> > > subsequent IS_JASPERLAKE() branch would never be taken.
> > > 
> > > BR,
> > > Jani.
> > > 
> > > Tejas : In that case I will put attention note in comment about
> > > platform checks such that ladder distrubance can be avoided. What you
> > > suggest?
> 
> > The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.
> 
> Since we are talking about the TLA for JSL in the other patch, for
> elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
> what:
> 
> $ git grep -w ELK -- drivers/gpu/drm/
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
> drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
> drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.

Yeah, ELK = Eagle Lake, CTG = Cantiga.  Both are old gen5 platforms IIRC.


Matt

> 
> Lucas De Marchi
> 
> > 
> > BR,
> > Jani.
> > 
> > 
> > -- 
> > Jani Nikula, Intel Open Source Graphics Center

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 23:10             ` Matt Roper
  (?)
@ 2020-09-29  7:30               ` Jani Nikula
  -1 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-29  7:30 UTC (permalink / raw)
  To: Matt Roper, Lucas De Marchi
  Cc: Surendrakumar Upadhyay, TejaskumarX, Vivi, Rodrigo, airlied,
	daniel, intel-gfx, dri-devel, linux-kernel, Ausmus, James, Souza,
	Jose, ville.syrjala, Pandey, Hariom

On Mon, 28 Sep 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Mon, Sep 28, 2020 at 04:07:39PM -0700, Lucas De Marchi wrote:
>> On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
>> > On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> > > This is a good example of a potential trap that having
>> > > IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
>> > > might change the if ladder to have IS_ELKHARTLAKE() first, and the
>> > > subsequent IS_JASPERLAKE() branch would never be taken.
>> > > 
>> > > BR,
>> > > Jani.
>> > > 
>> > > Tejas : In that case I will put attention note in comment about
>> > > platform checks such that ladder distrubance can be avoided. What you
>> > > suggest?
>> 
>> > The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.
>> 
>> Since we are talking about the TLA for JSL in the other patch, for
>> elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
>> what:
>> 
>> $ git grep -w ELK -- drivers/gpu/drm/
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
>> drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
>> drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.
>
> Yeah, ELK = Eagle Lake, CTG = Cantiga.  Both are old gen5 platforms IIRC.

Yeah, I know, my bad.

BR,
Jani.


>
>
> Matt
>
>> 
>> Lucas De Marchi
>> 
>> > 
>> > BR,
>> > Jani.
>> > 
>> > 
>> > -- 
>> > Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-29  7:30               ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-29  7:30 UTC (permalink / raw)
  To: Matt Roper, Lucas De Marchi
  Cc: Pandey, Hariom, Ausmus, James, airlied, intel-gfx, linux-kernel,
	dri-devel, Souza, Jose, Vivi, Rodrigo, Surendrakumar Upadhyay,
	TejaskumarX

On Mon, 28 Sep 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Mon, Sep 28, 2020 at 04:07:39PM -0700, Lucas De Marchi wrote:
>> On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
>> > On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> > > This is a good example of a potential trap that having
>> > > IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
>> > > might change the if ladder to have IS_ELKHARTLAKE() first, and the
>> > > subsequent IS_JASPERLAKE() branch would never be taken.
>> > > 
>> > > BR,
>> > > Jani.
>> > > 
>> > > Tejas : In that case I will put attention note in comment about
>> > > platform checks such that ladder distrubance can be avoided. What you
>> > > suggest?
>> 
>> > The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.
>> 
>> Since we are talking about the TLA for JSL in the other patch, for
>> elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
>> what:
>> 
>> $ git grep -w ELK -- drivers/gpu/drm/
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
>> drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
>> drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.
>
> Yeah, ELK = Eagle Lake, CTG = Cantiga.  Both are old gen5 platforms IIRC.

Yeah, I know, my bad.

BR,
Jani.


>
>
> Matt
>
>> 
>> Lucas De Marchi
>> 
>> > 
>> > BR,
>> > Jani.
>> > 
>> > 
>> > -- 
>> > Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-29  7:30               ` Jani Nikula
  0 siblings, 0 replies; 58+ messages in thread
From: Jani Nikula @ 2020-09-29  7:30 UTC (permalink / raw)
  To: Matt Roper, Lucas De Marchi
  Cc: Pandey, Hariom, airlied, intel-gfx, linux-kernel, dri-devel

On Mon, 28 Sep 2020, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Mon, Sep 28, 2020 at 04:07:39PM -0700, Lucas De Marchi wrote:
>> On Mon, Sep 28, 2020 at 08:15:29PM +0300, Jani Nikula wrote:
>> > On Mon, 28 Sep 2020, "Surendrakumar Upadhyay, TejaskumarX"	<tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
>> > > This is a good example of a potential trap that having
>> > > IS_ELKHARTLAKE() cover both ELK and JSP creates. An unsuspecting coder
>> > > might change the if ladder to have IS_ELKHARTLAKE() first, and the
>> > > subsequent IS_JASPERLAKE() branch would never be taken.
>> > > 
>> > > BR,
>> > > Jani.
>> > > 
>> > > Tejas : In that case I will put attention note in comment about
>> > > platform checks such that ladder distrubance can be avoided. What you
>> > > suggest?
>> 
>> > The solution is to make IS_ELKHARTLAKE() mean ELK and only ELK.
>> 
>> Since we are talking about the TLA for JSL in the other patch, for
>> elkhartlake it is EHL, not ELK. ELK is something else, but I'm not sure
>> what:
>> 
>> $ git grep -w ELK -- drivers/gpu/drm/
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:             IS_GM45(i915) ? "CTG" : "ELK", reg_val);
>> drivers/gpu/drm/i915/gem/i915_gem_stolen.c:      * Whether ILK really reuses the ELK register for this is unclear.
>> drivers/gpu/drm/i915/intel_pm.c:         * Not 100% sure which way ELK should go here as the
>> drivers/gpu/drm/i915/intel_pm.c:         * assume ELK doesn't need this.
>
> Yeah, ELK = Eagle Lake, CTG = Cantiga.  Both are old gen5 platforms IIRC.

Yeah, I know, my bad.

BR,
Jani.


>
>
> Matt
>
>> 
>> Lucas De Marchi
>> 
>> > 
>> > BR,
>> > Jani.
>> > 
>> > 
>> > -- 
>> > Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
  2020-09-28 17:20           ` Jani Nikula
  (?)
@ 2020-09-29 12:45             ` Ville Syrjälä
  -1 siblings, 0 replies; 58+ messages in thread
From: Ville Syrjälä @ 2020-09-29 12:45 UTC (permalink / raw)
  To: Jani Nikula
  Cc: James Ausmus, Tejas Upadhyay, rodrigo.vivi, airlied, daniel,
	intel-gfx, dri-devel, linux-kernel, matthew.d.roper, jose.souza,
	lucas.demarchi, hariom.pandey

On Mon, Sep 28, 2020 at 08:20:59PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
> >> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> >> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> > > JSL has update in vswing table for eDP
> >> > 
> >> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> >> > PCH_JSP for Jasper Lake PCH.
> >> 
> >> JSP == Point (the PCH), JSL == Lake
> >
> > .PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.
> 
> Yeah, nowadays it doesn't have "Point", however bspec agrees on the JSL
> acronym for Jasper Lake.

Bspec uses ..P for "<platform> PCH", when it acknowledges the existence
of said PCH (see eg. CNP,ICP,TGP). JSP is not among that select crowd
however, neither really is MCC (although it is mentioned by name in the
JSL section).

I kinda want to nuke the JSP and MCC types entirely. I believe we should
be able to treat them as just ICP and TGP variants respectively. But
theres's still a bit of work left to do before we can get there.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-29 12:45             ` Ville Syrjälä
  0 siblings, 0 replies; 58+ messages in thread
From: Ville Syrjälä @ 2020-09-29 12:45 UTC (permalink / raw)
  To: Jani Nikula
  Cc: hariom.pandey, James Ausmus, airlied, intel-gfx, lucas.demarchi,
	linux-kernel, dri-devel, jose.souza, rodrigo.vivi,
	Tejas Upadhyay

On Mon, Sep 28, 2020 at 08:20:59PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
> >> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> >> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> > > JSL has update in vswing table for eDP
> >> > 
> >> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> >> > PCH_JSP for Jasper Lake PCH.
> >> 
> >> JSP == Point (the PCH), JSL == Lake
> >
> > .PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.
> 
> Yeah, nowadays it doesn't have "Point", however bspec agrees on the JSL
> acronym for Jasper Lake.

Bspec uses ..P for "<platform> PCH", when it acknowledges the existence
of said PCH (see eg. CNP,ICP,TGP). JSP is not among that select crowd
however, neither really is MCC (although it is mentioned by name in the
JSL section).

I kinda want to nuke the JSP and MCC types entirely. I believe we should
be able to treat them as just ICP and TGP variants respectively. But
theres's still a bit of work left to do before we can get there.

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 58+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2
@ 2020-09-29 12:45             ` Ville Syrjälä
  0 siblings, 0 replies; 58+ messages in thread
From: Ville Syrjälä @ 2020-09-29 12:45 UTC (permalink / raw)
  To: Jani Nikula
  Cc: hariom.pandey, airlied, intel-gfx, lucas.demarchi, linux-kernel,
	dri-devel

On Mon, Sep 28, 2020 at 08:20:59PM +0300, Jani Nikula wrote:
> On Mon, 28 Sep 2020, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Mon, Sep 28, 2020 at 07:15:43AM -0700, James Ausmus wrote:
> >> On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote:
> >> > On Mon, 28 Sep 2020, Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> wrote:
> >> > > JSL has update in vswing table for eDP
> >> > 
> >> > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have
> >> > PCH_JSP for Jasper Lake PCH.
> >> 
> >> JSP == Point (the PCH), JSL == Lake
> >
> > .PT was "<something> Point", ..P stands just for "<something> PCH" IIRC.
> 
> Yeah, nowadays it doesn't have "Point", however bspec agrees on the JSL
> acronym for Jasper Lake.

Bspec uses ..P for "<platform> PCH", when it acknowledges the existence
of said PCH (see eg. CNP,ICP,TGP). JSP is not among that select crowd
however, neither really is MCC (although it is mentioned by name in the
JSL section).

I kinda want to nuke the JSP and MCC types entirely. I believe we should
be able to treat them as just ICP and TGP variants respectively. But
theres's still a bit of work left to do before we can get there.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 58+ messages in thread
end of thread, other threads:[~2020-09-29 12:46 UTC | newest]

Thread overview: 58+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-28  8:09 [PATCH 0/2] drm/i915/jsl: Update JasperLake Voltage swing table Tejas Upadhyay
2020-09-28  8:09 ` [Intel-gfx] " Tejas Upadhyay
2020-09-28  8:09 ` Tejas Upadhyay
2020-09-28  8:09 ` [PATCH 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids Tejas Upadhyay
2020-09-28  8:09   ` [Intel-gfx] " Tejas Upadhyay
2020-09-28  8:09   ` Tejas Upadhyay
2020-09-28 13:37   ` Jani Nikula
2020-09-28 13:37     ` [Intel-gfx] " Jani Nikula
2020-09-28 13:37     ` Jani Nikula
2020-09-28 16:31     ` Surendrakumar Upadhyay, TejaskumarX
2020-09-28 16:31       ` [Intel-gfx] " Surendrakumar Upadhyay, TejaskumarX
2020-09-28 17:14       ` Jani Nikula
2020-09-28 17:14         ` [Intel-gfx] " Jani Nikula
2020-09-28 17:14         ` Jani Nikula
2020-09-28 17:24         ` Matt Roper
2020-09-28 17:24           ` [Intel-gfx] " Matt Roper
2020-09-28 17:24           ` Matt Roper
2020-09-28 17:30           ` Surendrakumar Upadhyay, TejaskumarX
2020-09-28 17:30             ` [Intel-gfx] " Surendrakumar Upadhyay, TejaskumarX
2020-09-28 17:32           ` Jani Nikula
2020-09-28 17:32             ` [Intel-gfx] " Jani Nikula
2020-09-28 17:32             ` Jani Nikula
2020-09-28  8:09 ` [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2 Tejas Upadhyay
2020-09-28  8:09   ` [Intel-gfx] " Tejas Upadhyay
2020-09-28  8:09   ` Tejas Upadhyay
2020-09-28 13:43   ` [Intel-gfx] " Jani Nikula
2020-09-28 13:43     ` Jani Nikula
2020-09-28 13:43     ` Jani Nikula
2020-09-28 14:15     ` James Ausmus
2020-09-28 14:15       ` James Ausmus
2020-09-28 14:15       ` James Ausmus
2020-09-28 15:02       ` Ville Syrjälä
2020-09-28 15:02         ` Ville Syrjälä
2020-09-28 15:02         ` Ville Syrjälä
2020-09-28 17:20         ` Jani Nikula
2020-09-28 17:20           ` Jani Nikula
2020-09-28 17:20           ` Jani Nikula
2020-09-29 12:45           ` Ville Syrjälä
2020-09-29 12:45             ` Ville Syrjälä
2020-09-29 12:45             ` Ville Syrjälä
2020-09-28 16:34     ` Surendrakumar Upadhyay, TejaskumarX
2020-09-28 16:34       ` Surendrakumar Upadhyay, TejaskumarX
2020-09-28 17:15       ` Jani Nikula
2020-09-28 17:15         ` Jani Nikula
2020-09-28 17:15         ` Jani Nikula
2020-09-28 23:07         ` Lucas De Marchi
2020-09-28 23:07           ` Lucas De Marchi
2020-09-28 23:07           ` Lucas De Marchi
2020-09-28 23:10           ` Matt Roper
2020-09-28 23:10             ` Matt Roper
2020-09-28 23:10             ` Matt Roper
2020-09-29  7:30             ` Jani Nikula
2020-09-29  7:30               ` Jani Nikula
2020-09-29  7:30               ` Jani Nikula
2020-09-28  8:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/jsl: Update JasperLake Voltage swing table Patchwork
2020-09-28  8:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-09-28  9:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-09-28 12:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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