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MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 98A02145FE27BB9A30E7185DFB45C7ED9B1B7E39BB6B948EB11B042E961A9C452000:8 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Q29udmVydCBNZWRpYVRlayBJT01NVSB0byBEVCBzY2hlbWEuDQoNClNpZ25lZC1vZmYtYnk6IFlv bmcgV3UgPHlvbmcud3VAbWVkaWF0ZWsuY29tPg0KLS0tDQogLi4uL2JpbmRpbmdzL2lvbW11L21l ZGlhdGVrLGlvbW11LnR4dCAgICAgICAgIHwgMTAzIC0tLS0tLS0tLS0tLQ0KIC4uLi9iaW5kaW5n cy9pb21tdS9tZWRpYXRlayxpb21tdS55YW1sICAgICAgICB8IDE1NCArKysrKysrKysrKysrKysr KysNCiAyIGZpbGVzIGNoYW5nZWQsIDE1NCBpbnNlcnRpb25zKCspLCAxMDMgZGVsZXRpb25zKC0p DQogZGVsZXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9p b21tdS9tZWRpYXRlayxpb21tdS50eHQNCiBjcmVhdGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlv bi9kZXZpY2V0cmVlL2JpbmRpbmdzL2lvbW11L21lZGlhdGVrLGlvbW11LnlhbWwNCg0KZGlmZiAt LWdpdCBhL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9pb21tdS9tZWRpYXRlayxp b21tdS50eHQgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvbWVkaWF0 ZWssaW9tbXUudHh0DQpkZWxldGVkIGZpbGUgbW9kZSAxMDA2NDQNCmluZGV4IGMxY2NkODU4MmVi Mi4uMDAwMDAwMDAwMDAwDQotLS0gYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv aW9tbXUvbWVkaWF0ZWssaW9tbXUudHh0DQorKysgL2Rldi9udWxsDQpAQCAtMSwxMDMgKzAsMCBA QA0KLSogTWVkaWF0ZWsgSU9NTVUgQXJjaGl0ZWN0dXJlIEltcGxlbWVudGF0aW9uDQotDQotICBT b21lIE1lZGlhdGVrIFNPQ3MgY29udGFpbiBhIE11bHRpbWVkaWEgTWVtb3J5IE1hbmFnZW1lbnQg VW5pdCAoTTRVKSwgYW5kDQotdGhpcyBNNFUgaGF2ZSB0d28gZ2VuZXJhdGlvbnMgb2YgSFcgYXJj aGl0ZWN0dXJlLiBHZW5lcmF0aW9uIG9uZSB1c2VzIGZsYXQNCi1wYWdldGFibGUsIGFuZCBvbmx5 IHN1cHBvcnRzIDRLIHNpemUgcGFnZSBtYXBwaW5nLiBHZW5lcmF0aW9uIHR3byB1c2VzIHRoZQ0K LUFSTSBTaG9ydC1EZXNjcmlwdG9yIHRyYW5zbGF0aW9uIHRhYmxlIGZvcm1hdCBmb3IgYWRkcmVz cyB0cmFuc2xhdGlvbi4NCi0NCi0gIEFib3V0IHRoZSBNNFUgSGFyZHdhcmUgQmxvY2sgRGlhZ3Jh bSwgcGxlYXNlIGNoZWNrIGJlbG93Og0KLQ0KLSAgICAgICAgICAgICAgRU1JIChFeHRlcm5hbCBN ZW1vcnkgSW50ZXJmYWNlKQ0KLSAgICAgICAgICAgICAgIHwNCi0gICAgICAgICAgICAgIG00dSAo TXVsdGltZWRpYSBNZW1vcnkgTWFuYWdlbWVudCBVbml0KQ0KLSAgICAgICAgICAgICAgIHwNCi0g ICAgICAgICAgKy0tLS0tLS0tKw0KLSAgICAgICAgICB8ICAgICAgICB8DQotICAgICAgZ2FsczAt cnggICBnYWxzMS1yeCAgICAoR2xvYmFsIEFzeW5jIExvY2FsIFN5bmMgcngpDQotICAgICAgICAg IHwgICAgICAgIHwNCi0gICAgICAgICAgfCAgICAgICAgfA0KLSAgICAgIGdhbHMwLXR4ICAgZ2Fs czEtdHggICAgKEdsb2JhbCBBc3luYyBMb2NhbCBTeW5jIHR4KQ0KLSAgICAgICAgICB8ICAgICAg ICB8ICAgICAgICAgIFNvbWUgU29DcyBtYXkgaGF2ZSBHQUxTLg0KLSAgICAgICAgICArLS0tLS0t LS0rDQotICAgICAgICAgICAgICAgfA0KLSAgICAgICAgICAgU01JIENvbW1vbihTbWFydCBNdWx0 aW1lZGlhIEludGVyZmFjZSBDb21tb24pDQotICAgICAgICAgICAgICAgfA0KLSAgICAgICArLS0t LS0tLS0tLS0tLS0tLSstLS0tLS0tDQotICAgICAgIHwgICAgICAgICAgICAgICAgfA0KLSAgICAg ICB8ICAgICAgICAgICAgIGdhbHMtcnggICAgICAgIFRoZXJlIG1heSBiZSBHQUxTIGluIHNvbWUg bGFyYnMuDQotICAgICAgIHwgICAgICAgICAgICAgICAgfA0KLSAgICAgICB8ICAgICAgICAgICAg ICAgIHwNCi0gICAgICAgfCAgICAgICAgICAgICBnYWxzLXR4DQotICAgICAgIHwgICAgICAgICAg ICAgICAgfA0KLSAgIFNNSSBsYXJiMCAgICAgICAgU01JIGxhcmIxICAgLi4uIFNvQ3MgaGF2ZSBz ZXZlcmFsIFNNSSBsb2NhbCBhcmJpdGVyKGxhcmIpLg0KLSAgIChkaXNwbGF5KSAgICAgICAgICh2 ZGVjKQ0KLSAgICAgICB8ICAgICAgICAgICAgICAgIHwNCi0gICAgICAgfCAgICAgICAgICAgICAg ICB8DQotICstLS0tLSstLS0tLSsgICAgICstLS0tKy0tLS0rDQotIHwgICAgIHwgICAgIHwgICAg IHwgICAgfCAgICB8DQotIHwgICAgIHwgICAgIHwuLi4gIHwgICAgfCAgICB8ICAuLi4gVGhlcmUg YXJlIGRpZmZlcmVudCBwb3J0cyBpbiBlYWNoIGxhcmIuDQotIHwgICAgIHwgICAgIHwgICAgIHwg ICAgfCAgICB8DQotT1ZMMCBSRE1BMCBXRE1BMCAgTUMgICBQUCAgIFZMRA0KLQ0KLSAgQXMgYWJv dmUsIFRoZSBNdWx0aW1lZGlhIEhXIHdpbGwgZ28gdGhyb3VnaCBTTUkgYW5kIE00VSB3aGlsZSBp dA0KLWFjY2VzcyBFTUkuIFNNSSBpcyBhIGJyaWRnZSBiZXR3ZWVuIG00dSBhbmQgdGhlIE11bHRp bWVkaWEgSFcuIEl0IGNvbnRhaW4NCi1zbWkgbG9jYWwgYXJiaXRlciBhbmQgc21pIGNvbW1vbi4g SXQgd2lsbCBjb250cm9sIHdoZXRoZXIgdGhlIE11bHRpbWVkaWENCi1IVyBzaG91bGQgZ28gdGhv dWdoIHRoZSBtNHUgZm9yIHRyYW5zbGF0aW9uIG9yIGJ5cGFzcyBpdCBhbmQgdGFsaw0KLWRpcmVj dGx5IHdpdGggRU1JLiBBbmQgYWxzbyBTTUkgaGVscCBjb250cm9sIHRoZSBwb3dlciBkb21haW4g YW5kIGNsb2NrcyBmb3INCi1lYWNoIGxvY2FsIGFyYml0ZXIuDQotICBOb3JtYWxseSB3ZSBzcGVj aWZ5IGEgbG9jYWwgYXJiaXRlcihsYXJiKSBmb3IgZWFjaCBtdWx0aW1lZGlhIEhXDQotbGlrZSBk aXNwbGF5LCB2aWRlbyBkZWNvZGUsIGFuZCBjYW1lcmEuIEFuZCB0aGVyZSBhcmUgZGlmZmVyZW50 IHBvcnRzDQotaW4gZWFjaCBsYXJiLiBUYWtlIGEgZXhhbXBsZSwgVGhlcmUgYXJlIG1hbnkgcG9y dHMgbGlrZSBNQywgUFAsIFZMRCBpbiB0aGUNCi12aWRlbyBkZWNvZGUgbG9jYWwgYXJiaXRlciwg YWxsIHRoZXNlIHBvcnRzIGFyZSBhY2NvcmRpbmcgdG8gdGhlIHZpZGVvIEhXLg0KLSAgSW4gc29t ZSBTb0NzLCB0aGVyZSBtYXkgYmUgYSBHQUxTKEdsb2JhbCBBc3luYyBMb2NhbCBTeW5jKSBtb2R1 bGUgYmV0d2Vlbg0KLXNtaS1jb21tb24gYW5kIG00dSwgYW5kIGFkZGl0aW9uYWwgR0FMUyBtb2R1 bGUgYmV0d2VlbiBzbWktbGFyYiBhbmQNCi1zbWktY29tbW9uLiBHQUxTIGNhbiBiZWVuIHNlZW4g YXMgYSAiYXN5bmNocm9ub3VzIGZpZm8iIHdoaWNoIGNvdWxkIGhlbHANCi1zeW5jaHJvbml6ZSBm b3IgdGhlIG1vZHVsZXMgaW4gZGlmZmVyZW50IGNsb2NrIGZyZXF1ZW5jeS4NCi0NCi1SZXF1aXJl ZCBwcm9wZXJ0aWVzOg0KLS0gY29tcGF0aWJsZSA6IG11c3QgYmUgb25lIG9mIHRoZSBmb2xsb3dp bmcgc3RyaW5nOg0KLQkibWVkaWF0ZWssbXQyNzAxLW00dSIgZm9yIG10MjcwMSB3aGljaCB1c2Vz IGdlbmVyYXRpb24gb25lIG00dSBIVy4NCi0JIm1lZGlhdGVrLG10MjcxMi1tNHUiIGZvciBtdDI3 MTIgd2hpY2ggdXNlcyBnZW5lcmF0aW9uIHR3byBtNHUgSFcuDQotCSJtZWRpYXRlayxtdDY3Nzkt bTR1IiBmb3IgbXQ2Nzc5IHdoaWNoIHVzZXMgZ2VuZXJhdGlvbiB0d28gbTR1IEhXLg0KLQkibWVk aWF0ZWssbXQ3NjIzLW00dSIsICJtZWRpYXRlayxtdDI3MDEtbTR1IiBmb3IgbXQ3NjIzIHdoaWNo IHVzZXMNCi0JCQkJCQkgICAgIGdlbmVyYXRpb24gb25lIG00dSBIVy4NCi0JIm1lZGlhdGVrLG10 ODE3My1tNHUiIGZvciBtdDgxNzMgd2hpY2ggdXNlcyBnZW5lcmF0aW9uIHR3byBtNHUgSFcuDQot CSJtZWRpYXRlayxtdDgxODMtbTR1IiBmb3IgbXQ4MTgzIHdoaWNoIHVzZXMgZ2VuZXJhdGlvbiB0 d28gbTR1IEhXLg0KLS0gcmVnIDogbTR1IHJlZ2lzdGVyIGJhc2UgYW5kIHNpemUuDQotLSBpbnRl cnJ1cHRzIDogdGhlIGludGVycnVwdCBvZiBtNHUuDQotLSBjbG9ja3MgOiBtdXN0IGNvbnRhaW4g b25lIGVudHJ5IGZvciBlYWNoIGNsb2NrLW5hbWVzLg0KLS0gY2xvY2stbmFtZXMgOiBPbmx5IDEg b3B0aW9uYWwgY2xvY2s6DQotICAtICJiY2xrIjogdGhlIGJsb2NrIGNsb2NrIG9mIG00dS4NCi0g IEhlcmUgaXMgdGhlIGxpc3Qgd2hpY2ggcmVxdWlyZSB0aGlzICJiY2xrIjoNCi0gIC0gbXQyNzAx LCBtdDI3MTIsIG10NzYyMyBhbmQgbXQ4MTczLg0KLSAgTm90ZSB0aGF0IG00dSB1c2UgdGhlIEVN SSBjbG9jayB3aGljaCBhbHdheXMgaGFzIGJlZW4gZW5hYmxlZCBiZWZvcmUga2VybmVsDQotICBp ZiB0aGVyZSBpcyBubyB0aGlzICJiY2xrIi4NCi0tIG1lZGlhdGVrLGxhcmJzIDogTGlzdCBvZiBw aGFuZGxlIHRvIHRoZSBsb2NhbCBhcmJpdGVycyBpbiB0aGUgY3VycmVudCBTb2NzLg0KLQlSZWZl ciB0byBiaW5kaW5ncy9tZW1vcnktY29udHJvbGxlcnMvbWVkaWF0ZWssc21pLWxhcmIudHh0LiBJ dCBtdXN0IHNvcnQNCi0JYWNjb3JkaW5nIHRvIHRoZSBsb2NhbCBhcmJpdGVyIGluZGV4LCBsaWtl IGxhcmIwLCBsYXJiMSwgbGFyYjIuLi4NCi0tIGlvbW11LWNlbGxzIDogbXVzdCBiZSAxLiBUaGlz IGlzIHRoZSBtdGtfbTR1X2lkIGFjY29yZGluZyB0byB0aGUgSFcuDQotCVNwZWNpZmllcyB0aGUg bXRrX200dV9pZCBhcyBkZWZpbmVkIGluDQotCWR0LWJpbmRpbmcvbWVtb3J5L210MjcwMS1sYXJi LXBvcnQuaCBmb3IgbXQyNzAxLCBtdDc2MjMNCi0JZHQtYmluZGluZy9tZW1vcnkvbXQyNzEyLWxh cmItcG9ydC5oIGZvciBtdDI3MTIsDQotCWR0LWJpbmRpbmcvbWVtb3J5L210Njc3OS1sYXJiLXBv cnQuaCBmb3IgbXQ2Nzc5LA0KLQlkdC1iaW5kaW5nL21lbW9yeS9tdDgxNzMtbGFyYi1wb3J0Lmgg Zm9yIG10ODE3MywgYW5kDQotCWR0LWJpbmRpbmcvbWVtb3J5L210ODE4My1sYXJiLXBvcnQuaCBm b3IgbXQ4MTgzLg0KLQ0KLUV4YW1wbGU6DQotCWlvbW11OiBpb21tdUAxMDIwNTAwMCB7DQotCQlj b21wYXRpYmxlID0gIm1lZGlhdGVrLG10ODE3My1tNHUiOw0KLQkJcmVnID0gPDAgMHgxMDIwNTAw MCAwIDB4MTAwMD47DQotCQlpbnRlcnJ1cHRzID0gPEdJQ19TUEkgMTM5IElSUV9UWVBFX0xFVkVM X0xPVz47DQotCQljbG9ja3MgPSA8JmluZnJhY2ZnIENMS19JTkZSQV9NNFU+Ow0KLQkJY2xvY2st bmFtZXMgPSAiYmNsayI7DQotCQltZWRpYXRlayxsYXJicyA9IDwmbGFyYjAgJmxhcmIxICZsYXJi MiAmbGFyYjMgJmxhcmI0ICZsYXJiNT47DQotCQkjaW9tbXUtY2VsbHMgPSA8MT47DQotCX07DQot DQotRXhhbXBsZSBmb3IgYSBjbGllbnQgZGV2aWNlOg0KLQlkaXNwbGF5IHsNCi0JCWNvbXBhdGli bGUgPSAibWVkaWF0ZWssbXQ4MTczLWRpc3AiOw0KLQkJaW9tbXVzID0gPCZpb21tdSBNNFVfUE9S VF9ESVNQX09WTDA+LA0KLQkJCSA8JmlvbW11IE00VV9QT1JUX0RJU1BfUkRNQTA+Ow0KLQkJLi4u DQotCX07DQpkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2lv bW11L21lZGlhdGVrLGlvbW11LnlhbWwgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGlu Z3MvaW9tbXUvbWVkaWF0ZWssaW9tbXUueWFtbA0KbmV3IGZpbGUgbW9kZSAxMDA2NDQNCmluZGV4 IDAwMDAwMDAwMDAwMC4uZWFlNzczYWQ1M2EzDQotLS0gL2Rldi9udWxsDQorKysgYi9Eb2N1bWVu dGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvaW9tbXUvbWVkaWF0ZWssaW9tbXUueWFtbA0KQEAg LTAsMCArMSwxNTQgQEANCisjIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiAoR1BMLTIuMC1vbmx5 IE9SIEJTRC0yLUNsYXVzZSkNCislWUFNTCAxLjINCistLS0NCiskaWQ6IGh0dHA6Ly9kZXZpY2V0 cmVlLm9yZy9zY2hlbWFzL2lvbW11L21lZGlhdGVrLGlvbW11LnlhbWwjDQorJHNjaGVtYTogaHR0 cDovL2RldmljZXRyZWUub3JnL21ldGEtc2NoZW1hcy9jb3JlLnlhbWwjDQorDQordGl0bGU6IE1l ZGlhVGVrIElPTU1VIEFyY2hpdGVjdHVyZSBJbXBsZW1lbnRhdGlvbg0KKw0KK21haW50YWluZXJz Og0KKyAgLSBZb25nIFd1IDx5b25nLnd1QG1lZGlhdGVrLmNvbT4NCisNCitkZXNjcmlwdGlvbjog fCsNCisgIFNvbWUgTWVkaWFUZWsgU09DcyBjb250YWluIGEgTXVsdGltZWRpYSBNZW1vcnkgTWFu YWdlbWVudCBVbml0IChNNFUpLCBhbmQNCisgIHRoaXMgTTRVIGhhdmUgdHdvIGdlbmVyYXRpb25z IG9mIEhXIGFyY2hpdGVjdHVyZS4gR2VuZXJhdGlvbiBvbmUgdXNlcyBmbGF0DQorICBwYWdldGFi bGUsIGFuZCBvbmx5IHN1cHBvcnRzIDRLIHNpemUgcGFnZSBtYXBwaW5nLiBHZW5lcmF0aW9uIHR3 byB1c2VzIHRoZQ0KKyAgQVJNIFNob3J0LURlc2NyaXB0b3IgdHJhbnNsYXRpb24gdGFibGUgZm9y bWF0IGZvciBhZGRyZXNzIHRyYW5zbGF0aW9uLg0KKw0KKyAgQWJvdXQgdGhlIE00VSBIYXJkd2Fy ZSBCbG9jayBEaWFncmFtLCBwbGVhc2UgY2hlY2sgYmVsb3c6DQorDQorICAgICAgICAgICAgICAg IEVNSSAoRXh0ZXJuYWwgTWVtb3J5IEludGVyZmFjZSkNCisgICAgICAgICAgICAgICAgIHwNCisg ICAgICAgICAgICAgICAgbTR1IChNdWx0aW1lZGlhIE1lbW9yeSBNYW5hZ2VtZW50IFVuaXQpDQor ICAgICAgICAgICAgICAgICB8DQorICAgICAgICAgICAgKy0tLS0tLS0tKw0KKyAgICAgICAgICAg IHwgICAgICAgIHwNCisgICAgICAgIGdhbHMwLXJ4ICAgZ2FsczEtcnggICAgKEdsb2JhbCBBc3lu YyBMb2NhbCBTeW5jIHJ4KQ0KKyAgICAgICAgICAgIHwgICAgICAgIHwNCisgICAgICAgICAgICB8 ICAgICAgICB8DQorICAgICAgICBnYWxzMC10eCAgIGdhbHMxLXR4ICAgIChHbG9iYWwgQXN5bmMg TG9jYWwgU3luYyB0eCkNCisgICAgICAgICAgICB8ICAgICAgICB8ICAgICAgICAgIFNvbWUgU29D cyBtYXkgaGF2ZSBHQUxTLg0KKyAgICAgICAgICAgICstLS0tLS0tLSsNCisgICAgICAgICAgICAg ICAgIHwNCisgICAgICAgICAgICAgU01JIENvbW1vbihTbWFydCBNdWx0aW1lZGlhIEludGVyZmFj ZSBDb21tb24pDQorICAgICAgICAgICAgICAgICB8DQorICAgICAgICAgKy0tLS0tLS0tLS0tLS0t LS0rLS0tLS0tLQ0KKyAgICAgICAgIHwgICAgICAgICAgICAgICAgfA0KKyAgICAgICAgIHwgICAg ICAgICAgICAgZ2Fscy1yeCAgICAgICAgVGhlcmUgbWF5IGJlIEdBTFMgaW4gc29tZSBsYXJicy4N CisgICAgICAgICB8ICAgICAgICAgICAgICAgIHwNCisgICAgICAgICB8ICAgICAgICAgICAgICAg IHwNCisgICAgICAgICB8ICAgICAgICAgICAgIGdhbHMtdHgNCisgICAgICAgICB8ICAgICAgICAg ICAgICAgIHwNCisgICAgIFNNSSBsYXJiMCAgICAgICAgU01JIGxhcmIxICAgLi4uIFNvQ3MgaGF2 ZSBzZXZlcmFsIFNNSSBsb2NhbCBhcmJpdGVyKGxhcmIpLg0KKyAgICAgKGRpc3BsYXkpICAgICAg ICAgKHZkZWMpDQorICAgICAgICAgfCAgICAgICAgICAgICAgICB8DQorICAgICAgICAgfCAgICAg ICAgICAgICAgICB8DQorICAgKy0tLS0tKy0tLS0tKyAgICAgKy0tLS0rLS0tLSsNCisgICB8ICAg ICB8ICAgICB8ICAgICB8ICAgIHwgICAgfA0KKyAgIHwgICAgIHwgICAgIHwuLi4gIHwgICAgfCAg ICB8ICAuLi4gVGhlcmUgYXJlIGRpZmZlcmVudCBwb3J0cyBpbiBlYWNoIGxhcmIuDQorICAgfCAg ICAgfCAgICAgfCAgICAgfCAgICB8ICAgIHwNCisgIE9WTDAgUkRNQTAgV0RNQTAgIE1DICAgUFAg ICBWTEQNCisNCisgIEFzIGFib3ZlLCBUaGUgTXVsdGltZWRpYSBIVyB3aWxsIGdvIHRocm91Z2gg U01JIGFuZCBNNFUgd2hpbGUgaXQNCisgIGFjY2VzcyBFTUkuIFNNSSBpcyBhIGJyaWRnZSBiZXR3 ZWVuIG00dSBhbmQgdGhlIE11bHRpbWVkaWEgSFcuIEl0IGNvbnRhaW4NCisgIHNtaSBsb2NhbCBh cmJpdGVyIGFuZCBzbWkgY29tbW9uLiBJdCB3aWxsIGNvbnRyb2wgd2hldGhlciB0aGUgTXVsdGlt ZWRpYQ0KKyAgSFcgc2hvdWxkIGdvIHRob3VnaCB0aGUgbTR1IGZvciB0cmFuc2xhdGlvbiBvciBi eXBhc3MgaXQgYW5kIHRhbGsNCisgIGRpcmVjdGx5IHdpdGggRU1JLiBBbmQgYWxzbyBTTUkgaGVs cCBjb250cm9sIHRoZSBwb3dlciBkb21haW4gYW5kIGNsb2NrcyBmb3INCisgIGVhY2ggbG9jYWwg YXJiaXRlci4NCisNCisgIE5vcm1hbGx5IHdlIHNwZWNpZnkgYSBsb2NhbCBhcmJpdGVyKGxhcmIp IGZvciBlYWNoIG11bHRpbWVkaWEgSFcNCisgIGxpa2UgZGlzcGxheSwgdmlkZW8gZGVjb2RlLCBh bmQgY2FtZXJhLiBBbmQgdGhlcmUgYXJlIGRpZmZlcmVudCBwb3J0cw0KKyAgaW4gZWFjaCBsYXJi LiBUYWtlIGEgZXhhbXBsZSwgVGhlcmUgYXJlIG1hbnkgcG9ydHMgbGlrZSBNQywgUFAsIFZMRCBp biB0aGUNCisgIHZpZGVvIGRlY29kZSBsb2NhbCBhcmJpdGVyLCBhbGwgdGhlc2UgcG9ydHMgYXJl IGFjY29yZGluZyB0byB0aGUgdmlkZW8gSFcuDQorDQorICBJbiBzb21lIFNvQ3MsIHRoZXJlIG1h eSBiZSBhIEdBTFMoR2xvYmFsIEFzeW5jIExvY2FsIFN5bmMpIG1vZHVsZSBiZXR3ZWVuDQorICBz bWktY29tbW9uIGFuZCBtNHUsIGFuZCBhZGRpdGlvbmFsIEdBTFMgbW9kdWxlIGJldHdlZW4gc21p LWxhcmIgYW5kDQorICBzbWktY29tbW9uLiBHQUxTIGNhbiBiZWVuIHNlZW4gYXMgYSAiYXN5bmNo cm9ub3VzIGZpZm8iIHdoaWNoIGNvdWxkIGhlbHANCisgIHN5bmNocm9uaXplIGZvciB0aGUgbW9k dWxlcyBpbiBkaWZmZXJlbnQgY2xvY2sgZnJlcXVlbmN5Lg0KKw0KK3Byb3BlcnRpZXM6DQorICBj b21wYXRpYmxlOg0KKyAgICBvbmVPZjoNCisgICAgICAtIGVudW06DQorICAgICAgICAgIC0gbWVk aWF0ZWssbXQyNzAxLW00dSAjIG10MjcwMSBnZW5lcmF0aW9uIG9uZSBIVw0KKyAgICAgICAgICAt IG1lZGlhdGVrLG10MjcxMi1tNHUgIyBtdDI3MTIgZ2VuZXJhdGlvbiB0d28gSFcNCisgICAgICAg ICAgLSBtZWRpYXRlayxtdDY3NzktbTR1ICMgbXQ2Nzc5IGdlbmVyYXRpb24gdHdvIEhXDQorICAg ICAgICAgIC0gbWVkaWF0ZWssbXQ4MTczLW00dSAjIG10ODE3MyBnZW5lcmF0aW9uIHR3byBIVw0K KyAgICAgICAgICAtIG1lZGlhdGVrLG10ODE4My1tNHUgIyBtdDgxODMgZ2VuZXJhdGlvbiB0d28g SFcNCisNCisgICAgICAtIGRlc2NyaXB0aW9uOiBtdDc2MjMgZ2VuZXJhdGlvbiBvbmUgSFcNCisg ICAgICAgIGl0ZW1zOg0KKyAgICAgICAgICAtIGNvbnN0OiBtZWRpYXRlayxtdDc2MjMtbTR1DQor ICAgICAgICAgIC0gY29uc3Q6IG1lZGlhdGVrLG10MjcwMS1tNHUNCisNCisgIHJlZzoNCisgICAg bWF4SXRlbXM6IDENCisNCisgIGludGVycnVwdHM6DQorICAgIG1heEl0ZW1zOiAxDQorDQorICBj bG9ja3M6DQorICAgIGRlc2NyaXB0aW9uOiB8DQorICAgICAgYmNsayBpcyBvcHRpb25hbC4gaGVy ZSBpcyB0aGUgbGlzdCB3aGljaCByZXF1aXJlIHRoaXMgYmNsazoNCisgICAgICBtdDI3MDEsIG10 MjcxMiwgbXQ3NjIzIGFuZCBtdDgxNzMuDQorICAgICAgTTRVIHdpbGwgdXNlIHRoZSBFTUkgY2xv Y2sgd2hpY2ggYWx3YXlzIGhhcyBiZWVuIGVuYWJsZWQgYmVmb3JlDQorICAgICAga2VybmVsIGlm IHRoZXJlIGlzIG5vIHRoaXMgYmNsay4NCisgICAgaXRlbXM6DQorICAgICAgLSBkZXNjcmlwdGlv bjogYmNsayBpcyB0aGUgYmxvY2sgY2xvY2suDQorDQorICBjbG9jay1uYW1lczoNCisgICAgaXRl bXM6DQorICAgICAgLSBjb25zdDogYmNsaw0KKw0KKyAgbWVkaWF0ZWssbGFyYnM6DQorICAgICRy ZWY6IC9zY2hlbWFzL3R5cGVzLnlhbWwjL2RlZmluaXRpb25zL3BoYW5kbGUtYXJyYXkNCisgICAg ZGVzY3JpcHRpb246IHwNCisgICAgICBMaXN0IG9mIHBoYW5kbGUgdG8gdGhlIGxvY2FsIGFyYml0 ZXJzIGluIHRoZSBjdXJyZW50IFNvY3MuDQorICAgICAgUmVmZXIgdG8gYmluZGluZ3MvbWVtb3J5 LWNvbnRyb2xsZXJzL21lZGlhdGVrLHNtaS1sYXJiLnlhbWwuIEl0IG11c3Qgc29ydA0KKyAgICAg IGFjY29yZGluZyB0byB0aGUgbG9jYWwgYXJiaXRlciBpbmRleCwgbGlrZSBsYXJiMCwgbGFyYjEs IGxhcmIyLi4uDQorDQorICAnI2lvbW11LWNlbGxzJzoNCisgICAgY29uc3Q6IDENCisgICAgZGVz Y3JpcHRpb246IHwNCisgICAgICBUaGlzIGlzIHRoZSBtdGtfbTR1X2lkIGFjY29yZGluZyB0byB0 aGUgSFcuIFNwZWNpZmllcyB0aGUgbXRrX200dV9pZCBhcw0KKyAgICAgIGRlZmluZWQgaW4NCisg ICAgICBkdC1iaW5kaW5nL21lbW9yeS9tdDI3MDEtbGFyYi1wb3J0LmggZm9yIG10MjcwMSBhbmQg bXQ3NjIzLA0KKyAgICAgIGR0LWJpbmRpbmcvbWVtb3J5L210MjcxMi1sYXJiLXBvcnQuaCBmb3Ig bXQyNzEyLA0KKyAgICAgIGR0LWJpbmRpbmcvbWVtb3J5L210Njc3OS1sYXJiLXBvcnQuaCBmb3Ig bXQ2Nzc5LA0KKyAgICAgIGR0LWJpbmRpbmcvbWVtb3J5L210ODE3My1sYXJiLXBvcnQuaCBmb3Ig bXQ4MTczLA0KKyAgICAgIGR0LWJpbmRpbmcvbWVtb3J5L210ODE4My1sYXJiLXBvcnQuaCBmb3Ig bXQ4MTgzLg0KKw0KK3JlcXVpcmVkOg0KKyAgLSBjb21wYXRpYmxlDQorICAtIHJlZw0KKyAgLSBp bnRlcnJ1cHRzDQorICAtIG1lZGlhdGVrLGxhcmJzDQorICAtICcjaW9tbXUtY2VsbHMnDQorDQor YWRkaXRpb25hbFByb3BlcnRpZXM6IGZhbHNlDQorDQorZXhhbXBsZXM6DQorICAtIHwNCisgICAg I2luY2x1ZGUgPGR0LWJpbmRpbmdzL2Nsb2NrL210ODE3My1jbGsuaD4NCisgICAgI2luY2x1ZGUg PGR0LWJpbmRpbmdzL2ludGVycnVwdC1jb250cm9sbGVyL2FybS1naWMuaD4NCisNCisgICAgaW9t bXU6IGlvbW11QDEwMjA1MDAwIHsNCisgICAgICAgICAgICBjb21wYXRpYmxlID0gIm1lZGlhdGVr LG10ODE3My1tNHUiOw0KKyAgICAgICAgICAgIHJlZyA9IDwweDEwMjA1MDAwIDB4MTAwMD47DQor ICAgICAgICAgICAgaW50ZXJydXB0cyA9IDxHSUNfU1BJIDEzOSBJUlFfVFlQRV9MRVZFTF9MT1c+ Ow0KKyAgICAgICAgICAgIGNsb2NrcyA9IDwmaW5mcmFjZmcgQ0xLX0lORlJBX000VT47DQorICAg ICAgICAgICAgY2xvY2stbmFtZXMgPSAiYmNsayI7DQorICAgICAgICAgICAgbWVkaWF0ZWssbGFy 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mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 919837546; Wed, 30 Sep 2020 15:07:20 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 30 Sep 2020 15:07:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 15:07:15 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Robin Murphy , Krzysztof Kozlowski , Will Deacon Subject: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Date: Wed, 30 Sep 2020 15:06:24 +0800 Message-ID: <20200930070647.10188-2-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930070647.10188-1-yong.wu@mediatek.com> References: <20200930070647.10188-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 98A02145FE27BB9A30E7185DFB45C7ED9B1B7E39BB6B948EB11B042E961A9C452000:8 X-MTK: N Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, kernel-team@android.com, linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Convert MediaTek IOMMU to DT schema. Signed-off-by: Yong Wu --- .../bindings/iommu/mediatek,iommu.txt | 103 ------------ .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++ 2 files changed, 154 insertions(+), 103 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt deleted file mode 100644 index c1ccd8582eb2..000000000000 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Mediatek IOMMU Architecture Implementation - - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and -this M4U have two generations of HW architecture. Generation one uses flat -pagetable, and only supports 4K size page mapping. Generation two uses the -ARM Short-Descriptor translation table format for address translation. - - About the M4U Hardware Block Diagram, please check below: - - EMI (External Memory Interface) - | - m4u (Multimedia Memory Management Unit) - | - +--------+ - | | - gals0-rx gals1-rx (Global Async Local Sync rx) - | | - | | - gals0-tx gals1-tx (Global Async Local Sync tx) - | | Some SoCs may have GALS. - +--------+ - | - SMI Common(Smart Multimedia Interface Common) - | - +----------------+------- - | | - | gals-rx There may be GALS in some larbs. - | | - | | - | gals-tx - | | - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). - (display) (vdec) - | | - | | - +-----+-----+ +----+----+ - | | | | | | - | | |... | | | ... There are different ports in each larb. - | | | | | | -OVL0 RDMA0 WDMA0 MC PP VLD - - As above, The Multimedia HW will go through SMI and M4U while it -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain -smi local arbiter and smi common. It will control whether the Multimedia -HW should go though the m4u for translation or bypass it and talk -directly with EMI. And also SMI help control the power domain and clocks for -each local arbiter. - Normally we specify a local arbiter(larb) for each multimedia HW -like display, video decode, and camera. And there are different ports -in each larb. Take a example, There are many ports like MC, PP, VLD in the -video decode local arbiter, all these ports are according to the video HW. - In some SoCs, there may be a GALS(Global Async Local Sync) module between -smi-common and m4u, and additional GALS module between smi-larb and -smi-common. GALS can been seen as a "asynchronous fifo" which could help -synchronize for the modules in different clock frequency. - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses - generation one m4u HW. - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. -- reg : m4u register base and size. -- interrupts : the interrupt of m4u. -- clocks : must contain one entry for each clock-names. -- clock-names : Only 1 optional clock: - - "bclk": the block clock of m4u. - Here is the list which require this "bclk": - - mt2701, mt2712, mt7623 and mt8173. - Note that m4u use the EMI clock which always has been enabled before kernel - if there is no this "bclk". -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort - according to the local arbiter index, like larb0, larb1, larb2... -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. - Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 - dt-binding/memory/mt2712-larb-port.h for mt2712, - dt-binding/memory/mt6779-larb-port.h for mt6779, - dt-binding/memory/mt8173-larb-port.h for mt8173, and - dt-binding/memory/mt8183-larb-port.h for mt8183. - -Example: - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - -Example for a client device: - display { - compatible = "mediatek,mt8173-disp"; - iommus = <&iommu M4U_PORT_DISP_OVL0>, - <&iommu M4U_PORT_DISP_RDMA0>; - ... - }; diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml new file mode 100644 index 000000000000..eae773ad53a3 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek IOMMU Architecture Implementation + +maintainers: + - Yong Wu + +description: |+ + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and + this M4U have two generations of HW architecture. Generation one uses flat + pagetable, and only supports 4K size page mapping. Generation two uses the + ARM Short-Descriptor translation table format for address translation. + + About the M4U Hardware Block Diagram, please check below: + + EMI (External Memory Interface) + | + m4u (Multimedia Memory Management Unit) + | + +--------+ + | | + gals0-rx gals1-rx (Global Async Local Sync rx) + | | + | | + gals0-tx gals1-tx (Global Async Local Sync tx) + | | Some SoCs may have GALS. + +--------+ + | + SMI Common(Smart Multimedia Interface Common) + | + +----------------+------- + | | + | gals-rx There may be GALS in some larbs. + | | + | | + | gals-tx + | | + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). + (display) (vdec) + | | + | | + +-----+-----+ +----+----+ + | | | | | | + | | |... | | | ... There are different ports in each larb. + | | | | | | + OVL0 RDMA0 WDMA0 MC PP VLD + + As above, The Multimedia HW will go through SMI and M4U while it + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain + smi local arbiter and smi common. It will control whether the Multimedia + HW should go though the m4u for translation or bypass it and talk + directly with EMI. And also SMI help control the power domain and clocks for + each local arbiter. + + Normally we specify a local arbiter(larb) for each multimedia HW + like display, video decode, and camera. And there are different ports + in each larb. Take a example, There are many ports like MC, PP, VLD in the + video decode local arbiter, all these ports are according to the video HW. + + In some SoCs, there may be a GALS(Global Async Local Sync) module between + smi-common and m4u, and additional GALS module between smi-larb and + smi-common. GALS can been seen as a "asynchronous fifo" which could help + synchronize for the modules in different clock frequency. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-m4u # mt2701 generation one HW + - mediatek,mt2712-m4u # mt2712 generation two HW + - mediatek,mt6779-m4u # mt6779 generation two HW + - mediatek,mt8173-m4u # mt8173 generation two HW + - mediatek,mt8183-m4u # mt8183 generation two HW + + - description: mt7623 generation one HW + items: + - const: mediatek,mt7623-m4u + - const: mediatek,mt2701-m4u + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: | + bclk is optional. here is the list which require this bclk: + mt2701, mt2712, mt7623 and mt8173. + M4U will use the EMI clock which always has been enabled before + kernel if there is no this bclk. + items: + - description: bclk is the block clock. + + clock-names: + items: + - const: bclk + + mediatek,larbs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle to the local arbiters in the current Socs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort + according to the local arbiter index, like larb0, larb1, larb2... + + '#iommu-cells': + const: 1 + description: | + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as + defined in + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, + dt-binding/memory/mt2712-larb-port.h for mt2712, + dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt8173-larb-port.h for mt8173, + dt-binding/memory/mt8183-larb-port.h for mt8183. + +required: + - compatible + - reg + - interrupts + - mediatek,larbs + - '#iommu-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + iommu: iommu@10205000 { + compatible = "mediatek,mt8173-m4u"; + reg = <0x10205000 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2 + &larb3 &larb4 &larb5>; + #iommu-cells = <1>; + }; + + - | + #include + + /* Example for a client device */ + display { + compatible = "mediatek,mt8173-disp"; + iommus = <&iommu M4U_PORT_DISP_OVL0>, + <&iommu M4U_PORT_DISP_RDMA0>; + }; -- 2.18.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DF0FC4727F for ; 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Wed, 30 Sep 2020 15:07:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 15:07:15 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Robin Murphy , Krzysztof Kozlowski , Will Deacon Subject: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Date: Wed, 30 Sep 2020 15:06:24 +0800 Message-ID: <20200930070647.10188-2-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930070647.10188-1-yong.wu@mediatek.com> References: <20200930070647.10188-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 98A02145FE27BB9A30E7185DFB45C7ED9B1B7E39BB6B948EB11B042E961A9C452000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_031732_460539_D9557E94 X-CRM114-Status: GOOD ( 22.20 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, kernel-team@android.com, linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, yong.wu@mediatek.com, ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Convert MediaTek IOMMU to DT schema. Signed-off-by: Yong Wu --- .../bindings/iommu/mediatek,iommu.txt | 103 ------------ .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++ 2 files changed, 154 insertions(+), 103 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt deleted file mode 100644 index c1ccd8582eb2..000000000000 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Mediatek IOMMU Architecture Implementation - - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and -this M4U have two generations of HW architecture. Generation one uses flat -pagetable, and only supports 4K size page mapping. Generation two uses the -ARM Short-Descriptor translation table format for address translation. - - About the M4U Hardware Block Diagram, please check below: - - EMI (External Memory Interface) - | - m4u (Multimedia Memory Management Unit) - | - +--------+ - | | - gals0-rx gals1-rx (Global Async Local Sync rx) - | | - | | - gals0-tx gals1-tx (Global Async Local Sync tx) - | | Some SoCs may have GALS. - +--------+ - | - SMI Common(Smart Multimedia Interface Common) - | - +----------------+------- - | | - | gals-rx There may be GALS in some larbs. - | | - | | - | gals-tx - | | - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). - (display) (vdec) - | | - | | - +-----+-----+ +----+----+ - | | | | | | - | | |... | | | ... There are different ports in each larb. - | | | | | | -OVL0 RDMA0 WDMA0 MC PP VLD - - As above, The Multimedia HW will go through SMI and M4U while it -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain -smi local arbiter and smi common. It will control whether the Multimedia -HW should go though the m4u for translation or bypass it and talk -directly with EMI. And also SMI help control the power domain and clocks for -each local arbiter. - Normally we specify a local arbiter(larb) for each multimedia HW -like display, video decode, and camera. And there are different ports -in each larb. Take a example, There are many ports like MC, PP, VLD in the -video decode local arbiter, all these ports are according to the video HW. - In some SoCs, there may be a GALS(Global Async Local Sync) module between -smi-common and m4u, and additional GALS module between smi-larb and -smi-common. GALS can been seen as a "asynchronous fifo" which could help -synchronize for the modules in different clock frequency. - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses - generation one m4u HW. - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. -- reg : m4u register base and size. -- interrupts : the interrupt of m4u. -- clocks : must contain one entry for each clock-names. -- clock-names : Only 1 optional clock: - - "bclk": the block clock of m4u. - Here is the list which require this "bclk": - - mt2701, mt2712, mt7623 and mt8173. - Note that m4u use the EMI clock which always has been enabled before kernel - if there is no this "bclk". -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort - according to the local arbiter index, like larb0, larb1, larb2... -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. - Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 - dt-binding/memory/mt2712-larb-port.h for mt2712, - dt-binding/memory/mt6779-larb-port.h for mt6779, - dt-binding/memory/mt8173-larb-port.h for mt8173, and - dt-binding/memory/mt8183-larb-port.h for mt8183. - -Example: - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - -Example for a client device: - display { - compatible = "mediatek,mt8173-disp"; - iommus = <&iommu M4U_PORT_DISP_OVL0>, - <&iommu M4U_PORT_DISP_RDMA0>; - ... - }; diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml new file mode 100644 index 000000000000..eae773ad53a3 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek IOMMU Architecture Implementation + +maintainers: + - Yong Wu + +description: |+ + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and + this M4U have two generations of HW architecture. Generation one uses flat + pagetable, and only supports 4K size page mapping. Generation two uses the + ARM Short-Descriptor translation table format for address translation. + + About the M4U Hardware Block Diagram, please check below: + + EMI (External Memory Interface) + | + m4u (Multimedia Memory Management Unit) + | + +--------+ + | | + gals0-rx gals1-rx (Global Async Local Sync rx) + | | + | | + gals0-tx gals1-tx (Global Async Local Sync tx) + | | Some SoCs may have GALS. + +--------+ + | + SMI Common(Smart Multimedia Interface Common) + | + +----------------+------- + | | + | gals-rx There may be GALS in some larbs. + | | + | | + | gals-tx + | | + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). + (display) (vdec) + | | + | | + +-----+-----+ +----+----+ + | | | | | | + | | |... | | | ... There are different ports in each larb. + | | | | | | + OVL0 RDMA0 WDMA0 MC PP VLD + + As above, The Multimedia HW will go through SMI and M4U while it + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain + smi local arbiter and smi common. It will control whether the Multimedia + HW should go though the m4u for translation or bypass it and talk + directly with EMI. And also SMI help control the power domain and clocks for + each local arbiter. + + Normally we specify a local arbiter(larb) for each multimedia HW + like display, video decode, and camera. And there are different ports + in each larb. Take a example, There are many ports like MC, PP, VLD in the + video decode local arbiter, all these ports are according to the video HW. + + In some SoCs, there may be a GALS(Global Async Local Sync) module between + smi-common and m4u, and additional GALS module between smi-larb and + smi-common. GALS can been seen as a "asynchronous fifo" which could help + synchronize for the modules in different clock frequency. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-m4u # mt2701 generation one HW + - mediatek,mt2712-m4u # mt2712 generation two HW + - mediatek,mt6779-m4u # mt6779 generation two HW + - mediatek,mt8173-m4u # mt8173 generation two HW + - mediatek,mt8183-m4u # mt8183 generation two HW + + - description: mt7623 generation one HW + items: + - const: mediatek,mt7623-m4u + - const: mediatek,mt2701-m4u + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: | + bclk is optional. here is the list which require this bclk: + mt2701, mt2712, mt7623 and mt8173. + M4U will use the EMI clock which always has been enabled before + kernel if there is no this bclk. + items: + - description: bclk is the block clock. + + clock-names: + items: + - const: bclk + + mediatek,larbs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle to the local arbiters in the current Socs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort + according to the local arbiter index, like larb0, larb1, larb2... + + '#iommu-cells': + const: 1 + description: | + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as + defined in + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, + dt-binding/memory/mt2712-larb-port.h for mt2712, + dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt8173-larb-port.h for mt8173, + dt-binding/memory/mt8183-larb-port.h for mt8183. + +required: + - compatible + - reg + - interrupts + - mediatek,larbs + - '#iommu-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + iommu: iommu@10205000 { + compatible = "mediatek,mt8173-m4u"; + reg = <0x10205000 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2 + &larb3 &larb4 &larb5>; + #iommu-cells = <1>; + }; + + - | + #include + + /* Example for a client device */ + display { + compatible = "mediatek,mt8173-disp"; + iommus = <&iommu M4U_PORT_DISP_OVL0>, + <&iommu M4U_PORT_DISP_RDMA0>; + }; -- 2.18.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52744C2D0A8 for ; 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Wed, 30 Sep 2020 15:07:16 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 30 Sep 2020 15:07:15 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Rob Herring , Robin Murphy , Krzysztof Kozlowski , Will Deacon Subject: [PATCH v3 01/24] dt-bindings: iommu: mediatek: Convert IOMMU to DT schema Date: Wed, 30 Sep 2020 15:06:24 +0800 Message-ID: <20200930070647.10188-2-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200930070647.10188-1-yong.wu@mediatek.com> References: <20200930070647.10188-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 98A02145FE27BB9A30E7185DFB45C7ED9B1B7E39BB6B948EB11B042E961A9C452000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_031732_460539_D9557E94 X-CRM114-Status: GOOD ( 22.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, kernel-team@android.com, linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, linux-mediatek@lists.infradead.org, yong.wu@mediatek.com, ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Convert MediaTek IOMMU to DT schema. Signed-off-by: Yong Wu --- .../bindings/iommu/mediatek,iommu.txt | 103 ------------ .../bindings/iommu/mediatek,iommu.yaml | 154 ++++++++++++++++++ 2 files changed, 154 insertions(+), 103 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.txt create mode 100644 Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt deleted file mode 100644 index c1ccd8582eb2..000000000000 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt +++ /dev/null @@ -1,103 +0,0 @@ -* Mediatek IOMMU Architecture Implementation - - Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U), and -this M4U have two generations of HW architecture. Generation one uses flat -pagetable, and only supports 4K size page mapping. Generation two uses the -ARM Short-Descriptor translation table format for address translation. - - About the M4U Hardware Block Diagram, please check below: - - EMI (External Memory Interface) - | - m4u (Multimedia Memory Management Unit) - | - +--------+ - | | - gals0-rx gals1-rx (Global Async Local Sync rx) - | | - | | - gals0-tx gals1-tx (Global Async Local Sync tx) - | | Some SoCs may have GALS. - +--------+ - | - SMI Common(Smart Multimedia Interface Common) - | - +----------------+------- - | | - | gals-rx There may be GALS in some larbs. - | | - | | - | gals-tx - | | - SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). - (display) (vdec) - | | - | | - +-----+-----+ +----+----+ - | | | | | | - | | |... | | | ... There are different ports in each larb. - | | | | | | -OVL0 RDMA0 WDMA0 MC PP VLD - - As above, The Multimedia HW will go through SMI and M4U while it -access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain -smi local arbiter and smi common. It will control whether the Multimedia -HW should go though the m4u for translation or bypass it and talk -directly with EMI. And also SMI help control the power domain and clocks for -each local arbiter. - Normally we specify a local arbiter(larb) for each multimedia HW -like display, video decode, and camera. And there are different ports -in each larb. Take a example, There are many ports like MC, PP, VLD in the -video decode local arbiter, all these ports are according to the video HW. - In some SoCs, there may be a GALS(Global Async Local Sync) module between -smi-common and m4u, and additional GALS module between smi-larb and -smi-common. GALS can been seen as a "asynchronous fifo" which could help -synchronize for the modules in different clock frequency. - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW. - "mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW. - "mediatek,mt6779-m4u" for mt6779 which uses generation two m4u HW. - "mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses - generation one m4u HW. - "mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW. - "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW. -- reg : m4u register base and size. -- interrupts : the interrupt of m4u. -- clocks : must contain one entry for each clock-names. -- clock-names : Only 1 optional clock: - - "bclk": the block clock of m4u. - Here is the list which require this "bclk": - - mt2701, mt2712, mt7623 and mt8173. - Note that m4u use the EMI clock which always has been enabled before kernel - if there is no this "bclk". -- mediatek,larbs : List of phandle to the local arbiters in the current Socs. - Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort - according to the local arbiter index, like larb0, larb1, larb2... -- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW. - Specifies the mtk_m4u_id as defined in - dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623 - dt-binding/memory/mt2712-larb-port.h for mt2712, - dt-binding/memory/mt6779-larb-port.h for mt6779, - dt-binding/memory/mt8173-larb-port.h for mt8173, and - dt-binding/memory/mt8183-larb-port.h for mt8183. - -Example: - iommu: iommu@10205000 { - compatible = "mediatek,mt8173-m4u"; - reg = <0 0x10205000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_M4U>; - clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>; - #iommu-cells = <1>; - }; - -Example for a client device: - display { - compatible = "mediatek,mt8173-disp"; - iommus = <&iommu M4U_PORT_DISP_OVL0>, - <&iommu M4U_PORT_DISP_RDMA0>; - ... - }; diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml new file mode 100644 index 000000000000..eae773ad53a3 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek IOMMU Architecture Implementation + +maintainers: + - Yong Wu + +description: |+ + Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and + this M4U have two generations of HW architecture. Generation one uses flat + pagetable, and only supports 4K size page mapping. Generation two uses the + ARM Short-Descriptor translation table format for address translation. + + About the M4U Hardware Block Diagram, please check below: + + EMI (External Memory Interface) + | + m4u (Multimedia Memory Management Unit) + | + +--------+ + | | + gals0-rx gals1-rx (Global Async Local Sync rx) + | | + | | + gals0-tx gals1-tx (Global Async Local Sync tx) + | | Some SoCs may have GALS. + +--------+ + | + SMI Common(Smart Multimedia Interface Common) + | + +----------------+------- + | | + | gals-rx There may be GALS in some larbs. + | | + | | + | gals-tx + | | + SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb). + (display) (vdec) + | | + | | + +-----+-----+ +----+----+ + | | | | | | + | | |... | | | ... There are different ports in each larb. + | | | | | | + OVL0 RDMA0 WDMA0 MC PP VLD + + As above, The Multimedia HW will go through SMI and M4U while it + access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain + smi local arbiter and smi common. It will control whether the Multimedia + HW should go though the m4u for translation or bypass it and talk + directly with EMI. And also SMI help control the power domain and clocks for + each local arbiter. + + Normally we specify a local arbiter(larb) for each multimedia HW + like display, video decode, and camera. And there are different ports + in each larb. Take a example, There are many ports like MC, PP, VLD in the + video decode local arbiter, all these ports are according to the video HW. + + In some SoCs, there may be a GALS(Global Async Local Sync) module between + smi-common and m4u, and additional GALS module between smi-larb and + smi-common. GALS can been seen as a "asynchronous fifo" which could help + synchronize for the modules in different clock frequency. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-m4u # mt2701 generation one HW + - mediatek,mt2712-m4u # mt2712 generation two HW + - mediatek,mt6779-m4u # mt6779 generation two HW + - mediatek,mt8173-m4u # mt8173 generation two HW + - mediatek,mt8183-m4u # mt8183 generation two HW + + - description: mt7623 generation one HW + items: + - const: mediatek,mt7623-m4u + - const: mediatek,mt2701-m4u + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + description: | + bclk is optional. here is the list which require this bclk: + mt2701, mt2712, mt7623 and mt8173. + M4U will use the EMI clock which always has been enabled before + kernel if there is no this bclk. + items: + - description: bclk is the block clock. + + clock-names: + items: + - const: bclk + + mediatek,larbs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle to the local arbiters in the current Socs. + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort + according to the local arbiter index, like larb0, larb1, larb2... + + '#iommu-cells': + const: 1 + description: | + This is the mtk_m4u_id according to the HW. Specifies the mtk_m4u_id as + defined in + dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623, + dt-binding/memory/mt2712-larb-port.h for mt2712, + dt-binding/memory/mt6779-larb-port.h for mt6779, + dt-binding/memory/mt8173-larb-port.h for mt8173, + dt-binding/memory/mt8183-larb-port.h for mt8183. + +required: + - compatible + - reg + - interrupts + - mediatek,larbs + - '#iommu-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + iommu: iommu@10205000 { + compatible = "mediatek,mt8173-m4u"; + reg = <0x10205000 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_M4U>; + clock-names = "bclk"; + mediatek,larbs = <&larb0 &larb1 &larb2 + &larb3 &larb4 &larb5>; + #iommu-cells = <1>; + }; + + - | + #include + + /* Example for a client device */ + display { + compatible = "mediatek,mt8173-disp"; + iommus = <&iommu M4U_PORT_DISP_OVL0>, + <&iommu M4U_PORT_DISP_RDMA0>; + }; -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel