From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F78C4727E for ; Thu, 1 Oct 2020 16:02:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF2A220872 for ; Thu, 1 Oct 2020 16:02:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732853AbgJAQCc (ORCPT ); Thu, 1 Oct 2020 12:02:32 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:38584 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732213AbgJAQCJ (ORCPT ); Thu, 1 Oct 2020 12:02:09 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id A015929D759 From: Enric Balletbo i Serra To: linux-kernel@vger.kernel.org Cc: Collabora Kernel ML , fparent@baylibre.com, matthias.bgg@gmail.com, drinkcat@chromium.org, hsinyi@chromium.org, weiyi.lu@mediatek.com, Matthias Brugger , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 07/12] soc: mediatek: pm-domains: Add extra sram control Date: Thu, 1 Oct 2020 18:01:49 +0200 Message-Id: <20201001160154.3587848-8-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201001160154.3587848-1-enric.balletbo@collabora.com> References: <20201001160154.3587848-1-enric.balletbo@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matthias Brugger For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra --- Changes in v2: - Nit, split readl(ctl_addr) | pd->data->sram_pdn_bits in two lines. - Use regmap API drivers/soc/mediatek/mtk-pm-domains.c | 30 +++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 38f2630bdd0a..e0a52d489fea 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -21,6 +21,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -42,6 +43,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) @@ -155,14 +158,28 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; u32 val; int tmp; + int ret; regmap_read(scpsys->base, pd->data->ctl_offs, &val); val &= ~pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ - return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + } + + return 0; } static int scpsys_sram_disable(struct scpsys_domain *pd) @@ -172,6 +189,15 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) u32 val; int tmp; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + val &= ~PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + } + regmap_read(scpsys->base, pd->data->ctl_offs, &val); val |= pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); -- 2.28.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 644EEC4727E for ; Thu, 1 Oct 2020 16:03:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1570020872 for ; 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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kO13C-0000gD-1E; Thu, 01 Oct 2020 16:03:22 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kO122-0008PV-Fi; Thu, 01 Oct 2020 16:02:11 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id A015929D759 From: Enric Balletbo i Serra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 07/12] soc: mediatek: pm-domains: Add extra sram control Date: Thu, 1 Oct 2020 18:01:49 +0200 Message-Id: <20201001160154.3587848-8-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201001160154.3587848-1-enric.balletbo@collabora.com> References: <20201001160154.3587848-1-enric.balletbo@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201001_120210_644587_91551ABD X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, weiyi.lu@mediatek.com, fparent@baylibre.com, Matthias Brugger , linux-mediatek@lists.infradead.org, hsinyi@chromium.org, matthias.bgg@gmail.com, Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Matthias Brugger For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra --- Changes in v2: - Nit, split readl(ctl_addr) | pd->data->sram_pdn_bits in two lines. - Use regmap API drivers/soc/mediatek/mtk-pm-domains.c | 30 +++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 38f2630bdd0a..e0a52d489fea 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -21,6 +21,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -42,6 +43,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) @@ -155,14 +158,28 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; u32 val; int tmp; + int ret; regmap_read(scpsys->base, pd->data->ctl_offs, &val); val &= ~pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ - return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + } + + return 0; } static int scpsys_sram_disable(struct scpsys_domain *pd) @@ -172,6 +189,15 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) u32 val; int tmp; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + val &= ~PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + } + regmap_read(scpsys->base, pd->data->ctl_offs, &val); val |= pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); -- 2.28.0 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D90CC4727E for ; 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bh=BnJUVWcIWq9FcLrBZhCUzEHwaOBpDZa8imuqqrHp+mY=; b=x+OLBqzAEhLekDu3+0hP+RSWH w3jfQ1m2DuR9dsCG/aLlHC+kLbwcPMy+Cr9YzXndS4tboO5W/hYdNHY1B61/0giDjKaGXKA64vdeK q0PBIqLNSyAUSUx3aCkec24hl6b+DhGMv0UlTZPmC5bFB0fjDS749ScuiF/6geCKIgltwBSaShNc7 AVDUlyXQ+SsakdWz5QLxsrenXXFFoSGa2ABDacKpa6w0c05dQw0bCDPYOiao70p4mgGcbnsRF6FJ+ 6BAXG+JgTWH+ejV+MfSwUIKY6+ZBxexfz0N5UR+KBMehHtNuuuI+zvfqgnmoJi0o+APOoh3XVJTnZ 76DD1siXg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kO12j-0000Mv-2P; Thu, 01 Oct 2020 16:02:53 +0000 Received: from bhuna.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e3e3]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kO122-0008PV-Fi; Thu, 01 Oct 2020 16:02:11 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id A015929D759 From: Enric Balletbo i Serra To: linux-kernel@vger.kernel.org Subject: [PATCH v2 07/12] soc: mediatek: pm-domains: Add extra sram control Date: Thu, 1 Oct 2020 18:01:49 +0200 Message-Id: <20201001160154.3587848-8-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201001160154.3587848-1-enric.balletbo@collabora.com> References: <20201001160154.3587848-1-enric.balletbo@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201001_120210_644587_91551ABD X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drinkcat@chromium.org, weiyi.lu@mediatek.com, fparent@baylibre.com, Matthias Brugger , linux-mediatek@lists.infradead.org, hsinyi@chromium.org, matthias.bgg@gmail.com, Collabora Kernel ML , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Matthias Brugger For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra --- Changes in v2: - Nit, split readl(ctl_addr) | pd->data->sram_pdn_bits in two lines. - Use regmap API drivers/soc/mediatek/mtk-pm-domains.c | 30 +++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 38f2630bdd0a..e0a52d489fea 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -21,6 +21,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 @@ -42,6 +43,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) @@ -155,14 +158,28 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; u32 val; int tmp; + int ret; regmap_read(scpsys->base, pd->data->ctl_offs, &val); val &= ~pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ - return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + val &= ~PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + } + + return 0; } static int scpsys_sram_disable(struct scpsys_domain *pd) @@ -172,6 +189,15 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) u32 val; int tmp; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_read(scpsys->base, pd->data->ctl_offs, &val); + val |= PWR_SRAM_CLKISO_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + val &= ~PWR_SRAM_ISOINT_B_BIT; + regmap_write(scpsys->base, pd->data->ctl_offs, val); + udelay(1); + } + regmap_read(scpsys->base, pd->data->ctl_offs, &val); val |= pd->data->sram_pdn_bits; regmap_write(scpsys->base, pd->data->ctl_offs, val); -- 2.28.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel