From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FFBEC4363A for ; Mon, 5 Oct 2020 23:12:42 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D92A207F7 for ; Mon, 5 Oct 2020 23:12:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5D92A207F7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7977F6E194; Mon, 5 Oct 2020 23:12:40 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id A193D6E194 for ; Mon, 5 Oct 2020 23:12:39 +0000 (UTC) IronPort-SDR: SUTuXWqgRgS5TcewDvNcnc/QypOWndPMPM64zOmFjaflCnQufr+neURG5DhL1h0bZUiwGj5bLi WuqVuUerGhyw== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="248908449" X-IronPort-AV: E=Sophos;i="5.77,341,1596524400"; d="scan'208";a="248908449" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 05 Oct 2020 16:12:27 -0700 IronPort-SDR: bV4Kbn5ADWnpTH8fVe0UgrlTSV0Q8DOPmp6dvgxafCnW6SxgP1u62B8LCEhWLRN85uMArbtXIx ekF1FaoYu9MQ== X-IronPort-AV: E=Sophos;i="5.77,341,1596524400"; d="scan'208";a="460086003" Received: from ideak-desk.fi.intel.com ([10.237.68.141]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2020 13:46:39 -0700 Date: Mon, 5 Oct 2020 23:46:17 +0300 From: Imre Deak To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Message-ID: <20201005204617.GC1378377@ideak-desk.fi.intel.com> References: <20201003001846.1271151-1-imre.deak@intel.com> <20201003001846.1271151-5-imre.deak@intel.com> <20201005203055.GM6112@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201005203055.GM6112@intel.com> Subject: Re: [Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Oct 05, 2020 at 11:30:55PM +0300, Ville Syrj=E4l=E4 wrote: > On Sat, Oct 03, 2020 at 03:18:45AM +0300, Imre Deak wrote: > > Atm, if a full modeset is performed during the initial modeset the link > > training will happen with uninitialized max DP rate and lane count. Make > > sure the corresponding encoder state is initialized by adding an encoder > > hook called during driver init and system resume. > > = > > A better alternative would be to store all states in the CRTC state and > > make this state available for the link re-training code. Also instead of > > the DPCD read in the hook there should be really a proper sink HW > > readout in place. Both of these require a bigger rework, so for now opt= ing > > for this minimal fix to make at least full initial modesets work. > > = > > The patch is based on > > https://patchwork.freedesktop.org/patch/101473/?series=3D10354&rev=3D3 > > = > > Cc: Ville Syrj=E4l=E4 > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++++ > > drivers/gpu/drm/i915/display/intel_display.c | 4 +++ > > .../drm/i915/display/intel_display_types.h | 7 +++++ > > drivers/gpu/drm/i915/display/intel_dp.c | 31 +++++++++++++++++++ > > drivers/gpu/drm/i915/display/intel_dp.h | 2 ++ > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++++++ > > 6 files changed, 62 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm= /i915/display/intel_ddi.c > > index 4e54c55ec99f..a0805260b224 100644 > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > > @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder *= encoder, > > intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); > > } > > = > > +static void intel_ddi_sanitize_state(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state) > > +{ > > + if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) > > + intel_dp_sanitize_state(encoder, crtc_state); > > +} > = > I think we usually use 'sanitize' to mean "hw state is garbage -> must > take steps to sanitize it". This one is just filling in our intel_dp > sidechannel state. So the name isn't super consistnet with existing > practies. It is called during init/resume time when encoders are sanitized as well, but yea it's a separate step from HW readout. So I can rename it for instance (back) to sync_state, or any better idea? > = > > + > > static bool intel_ddi_initial_fastset_check(struct intel_encoder *enco= der, > > struct intel_crtc_state *crtc_state) > > { > > @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_= priv, enum port port) > > encoder->update_pipe =3D intel_ddi_update_pipe; > > encoder->get_hw_state =3D intel_ddi_get_hw_state; > > encoder->get_config =3D intel_ddi_get_config; > > + encoder->sanitize_state =3D intel_ddi_sanitize_state; > > encoder->initial_fastset_check =3D intel_ddi_initial_fastset_check; > > encoder->suspend =3D intel_dp_encoder_suspend; > > encoder->get_power_domains =3D intel_ddi_get_power_domains; > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu= /drm/i915/display/intel_display.c > > index 31be63225b10..e61311ee8b8c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -18725,8 +18725,12 @@ static void intel_modeset_readout_hw_state(str= uct drm_device *dev) > > = > > encoder->base.crtc =3D &crtc->base; > > encoder->get_config(encoder, crtc_state); > > + if (encoder->sanitize_state) > > + encoder->sanitize_state(encoder, crtc_state); > > } else { > > encoder->base.crtc =3D NULL; > > + if (encoder->sanitize_state) > > + encoder->sanitize_state(encoder, NULL); > = > I wonder if we should even bother calling it in this case. Yes, it would be just a nop atm, and can't think what state would need to be updated, so will remove it. > = > > } > > = > > drm_dbg_kms(&dev_priv->drm, > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drive= rs/gpu/drm/i915/display/intel_display_types.h > > index 5297b2f08ff9..b2b458144f5a 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -188,6 +188,13 @@ struct intel_encoder { > > void (*get_config)(struct intel_encoder *, > > struct intel_crtc_state *pipe_config); > > = > > + /* > > + * Optional hook called during init/resume to sanitize any state > > + * stored in the encoder (eg. DP link parameters). > > + */ > > + void (*sanitize_state)(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state); > > + > > /* > > * Optional hook, returning true if this encoder allows a fastset > > * during the initial commit, false otherwise. > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/= i915/display/intel_dp.c > > index df5277c2b9ba..9b6fe3b3b5b2 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -3703,6 +3703,36 @@ static void intel_dp_get_config(struct intel_enc= oder *encoder, > > } > > } > > = > > +static bool > > +intel_dp_get_dpcd(struct intel_dp *intel_dp); > > + > > +/** > > + * intel_dp_sanitize_state - sanitize the encoder state during init/re= sume > > + * @encoder: intel encoder to sanitize > > + * @crtc_state: state for the CRTC connected to the encoder > > + * > > + * Sanitize any state stored in the encoder during driver init and sys= tem > > + * resume. > > + */ > > +void intel_dp_sanitize_state(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state) > > +{ > > + struct intel_dp *intel_dp =3D enc_to_intel_dp(encoder); > > + > > + if (!crtc_state) > > + return; > > + > > + /* > > + * Don't clobber DPCD if it's been already read out during output > > + * setup (eDP) or detect. > > + */ > > + if (!memchr_inv(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd))) > > + intel_dp_get_dpcd(intel_dp); > > + > > + intel_dp->max_link_lane_count =3D intel_dp_max_common_lane_count(inte= l_dp); > > + intel_dp->max_link_rate =3D intel_dp_max_common_rate(intel_dp); > > +} > > + > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, > > struct intel_crtc_state *crtc_state) > > { > > @@ -8090,6 +8120,7 @@ bool intel_dp_init(struct drm_i915_private *dev_p= riv, > > intel_encoder->compute_config =3D intel_dp_compute_config; > > intel_encoder->get_hw_state =3D intel_dp_get_hw_state; > > intel_encoder->get_config =3D intel_dp_get_config; > > + intel_encoder->sanitize_state =3D intel_dp_sanitize_state; > > intel_encoder->initial_fastset_check =3D intel_dp_initial_fastset_che= ck; > > intel_encoder->update_pipe =3D intel_panel_update_backlight; > > intel_encoder->suspend =3D intel_dp_encoder_suspend; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/= i915/display/intel_dp.h > > index 977585aea3c8..1ab741e0be67 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.h > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h > > @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port *d= ig_port, > > = > > bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, > > struct intel_crtc_state *crtc_state); > > +void intel_dp_sanitize_state(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state); > > = > > #endif /* __INTEL_DP_H__ */ > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/= drm/i915/display/intel_dp_mst.c > > index e948aacbd4ab..0831d1ee7978 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > > @@ -591,6 +591,15 @@ static void intel_dp_mst_enc_get_config(struct int= el_encoder *encoder, > > intel_ddi_get_config(&dig_port->base, pipe_config); > > } > > = > > +static void intel_dp_mst_sync_state(struct intel_encoder *encoder, > > + const struct intel_crtc_state *crtc_state) > > +{ > > + struct intel_dp_mst_encoder *intel_mst =3D enc_to_mst(encoder); > > + struct intel_digital_port *dig_port =3D intel_mst->primary; > > + > > + return intel_dp_sanitize_state(&dig_port->base, crtc_state); > > +} > > + > > static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *e= ncoder, > > struct intel_crtc_state *crtc_state) > > { > > @@ -906,6 +915,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digit= al_port *dig_port, enum pipe > > intel_encoder->enable =3D intel_mst_enable_dp; > > intel_encoder->get_hw_state =3D intel_dp_mst_enc_get_hw_state; > > intel_encoder->get_config =3D intel_dp_mst_enc_get_config; > > + intel_encoder->sanitize_state =3D intel_dp_mst_sync_state; > > intel_encoder->initial_fastset_check =3D intel_dp_mst_initial_fastset= _check; > > = > > return intel_mst; > > -- = > > 2.25.1 > = > -- = > Ville Syrj=E4l=E4 > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx