From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9080CC41604 for ; Tue, 6 Oct 2020 16:13:53 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 27C5C206D4 for ; Tue, 6 Oct 2020 16:13:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="gVxRRBll"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="IMNPWuaT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 27C5C206D4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=7vq5wu+pqAW9sLWatZRaTLW9MyWTTLc/ecudwb+5py0=; b=gVxRRBllgsukLgDB/KKpxWZgz i/nci3UVPYY6M8QXxiUGlb/AnS5Ay6mctItjoNDdz+P4+bwcMzvy5egS7t3HK1o9Kg6Pmk2HulroQ k2b+2lQ6GENqfAkBaQtMWvrIdwDzd9pkGcoZPFBS5Kpm0roExzxRRHfsYOV316IjHf5X8ZmtIOEjf +i2rFcqdJEovFAD+pOejNRzJmXLk3C1FLGSbadNxg5kvWom7WvsxPAxKi+HhGDGJ3OTuxpZoa5BHM LUb6a9da2qmW/JCXmAfWTIPVDEZ9tz1hgxrgImTUqg2IwIcjls3z0+7F/m9BPdwKlXrpw9W1rBksf mu9mlQNqg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPpZk-0005CY-V5; Tue, 06 Oct 2020 16:12:29 +0000 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPpZg-00059c-7o for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2020 16:12:25 +0000 Received: by mail-pg1-x542.google.com with SMTP id h6so7557164pgk.4 for ; Tue, 06 Oct 2020 09:12:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=TATwM2xkGOIgB5UlKvFW5Ghzf3vguryeGSn0430hIvc=; b=IMNPWuaTwFRfhrCmT0Kb85R4bQdVQAm4XP7r3Dd8Hw3p8nns1z/Gynmgx9/WNFQM5X XJlHr9SMcV6uazSrAERFb/IACmBKAZ+vzcOgsnKE/NR7PdxuzGalFTuaio/lf2EgPdAv XBGevGYctebp/U+CsWGbaXmg5yTYe6KoQbuYJYhywuM1OPmHwKhBMqnK2cqlu+H1UWNJ B/vhP6ROZlKo7PItSWOy1ZGzOStkQPjSqjzgMGGIEev1wyu7oQcAux31DT4v+iAPQFaC +vKLgxArWw6OvUpJYnGi9TLgXkJHh2GOuDRJJwXoHvCeC/TIEgINMLN7rzPAtKJcbWdj 3Stw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=TATwM2xkGOIgB5UlKvFW5Ghzf3vguryeGSn0430hIvc=; b=NJXSVhRhgk/Yql8IJtTbHoMSheTMAjfb6efAkE2kyOg8klZMO0bH7sa6+S2ri2oFXB vvTXUJiVP3rtmytsNRPOmoS0MYKFuzvS0++Qc7NPLW1Dp0F8Jja5aQzzEQjD9c9FnRHE MfSKfFlKbOTqjihQt3s9Xww995o2vTgJjazICfUJ1YawiupCnQZYc5cBHgqdAao6YXhd PAesyJ21fAPAXHIYEVPcxbCo4D6MCmSPmDMrqI03WDiTsD7TsuCWOydoachRrhjn9jxe DHlxIQIAtavrJ+4srjCXfctDXNZzXmkoIqJ6nYWLElYn5uvwcCFS39yiJGHaR9UmuNTX zkjA== X-Gm-Message-State: AOAM532fH1Aq4iQzcYJXfvfhfvsoQinGu9xk9ZDGHUPUj9+QIyoqbd4s zYfrEfrDMO9aT4kcxdMkQXs4Sg== X-Google-Smtp-Source: ABdhPJzqhqLTNvMvxs6c0ZK0ECf7rgRvBYSOBo/jE3pOdJybIvKsiXPlSl3dqD+BFaEQPNMXeeXMPw== X-Received: by 2002:a62:fb1a:0:b029:142:2501:39f9 with SMTP id x26-20020a62fb1a0000b0290142250139f9mr4970751pfm.72.1602000740387; Tue, 06 Oct 2020 09:12:20 -0700 (PDT) Received: from xps15 (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id mh8sm3186808pjb.32.2020.10.06.09.12.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Oct 2020 09:12:19 -0700 (PDT) Date: Tue, 6 Oct 2020 10:12:17 -0600 From: Mathieu Poirier To: Suzuki K Poulose Subject: Re: [PATCH v4 0/2] Make sysFS functional on topologies with per core sink Message-ID: <20201006161217.GC404547@xps15> References: <20200904024106.21478-1-lcherian@marvell.com> <2bd65f2d-5660-10b3-f51f-448221d78d3d@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <2bd65f2d-5660-10b3-f51f-448221d78d3d@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_121224_306410_5B2F3999 X-CRM114-Status: GOOD ( 48.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linuc.decode@gmail.com, linux-arm-kernel@lists.infradead.org, lcherian@marvell.com, mike.leach@linaro.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 05, 2020 at 12:27:07PM +0100, Suzuki K Poulose wrote: > Hi Linu, > > On 09/04/2020 03:41 AM, Linu Cherian wrote: > > This patch series tries to fix the sysfs breakage on topologies > > with per core sink. > > > > Changes since v3: > > - References to coresight_get_enabled_sink in perf interface > > has been removed and marked deprecated as a new patch. > > - To avoid changes to coresight_find_sink for ease of maintenance, > > search function specific to sysfs usage has been added. > > - Sysfs being the only user for coresight_get_enabled sink, > > reset option is removed as well. > > Have you tried running perf with --per-thread option ? I believe > this will be impacted as well, as we choose a single sink at the > moment and this may not be reachable from the other CPUs, where > the event may be scheduled. Eventually loosing trace for the > duration where the task is scheduled on a different CPU. Right, I considered this set in the context of sysfs only. I expect supporting 1:1 configuration on perf to require changes in the kernel drivers and the perf tools. > > Please could you try this patch and see if helps ? I have lightly > tested this on a fast model. > > ---8>--- > > coresight: etm-perf: Allow an event to use multiple sinks > > When there are multiple sinks on the system, in the absence > of a specified sink, it is quite possible that a default sink > for an ETM could be different from that of another ETM (e.g, on > systems with per-CPU sinks). However we do not support having > multiple sinks for an event yet. This patch allows the event to > use the default sinks on the ETMs where they are scheduled as > long as the sinks are of the same type. > > e.g, if we have 1x1 topology with per-CPU ETRs, the event can > use the per-CPU ETR for the session. However, if the sinks > are of different type, e.g TMC-ETR on one and a custom sink > on another, the event will only trace on the first detected > sink (just like we have today). > > Cc: Linu Cherian > Cc: Mathieu Poirier > Cc: Mike Leach > Signed-off-by: Suzuki K Poulose > --- > .../hwtracing/coresight/coresight-etm-perf.c | 69 +++++++++++++------ > 1 file changed, 49 insertions(+), 20 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c > b/drivers/hwtracing/coresight/coresight-etm-perf.c > index c2c9b127d074..19fe38010474 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -204,14 +204,28 @@ static void etm_free_aux(void *data) > schedule_work(&event_data->work); > } > > +/* > + * When an event could be scheduled on more than one CPUs, we have to make > + * sure that the sinks are of the same type, so that the sink_buffer could > + * be reused. > + */ > +static bool sinks_match(struct coresight_device *a, struct coresight_device *b) > +{ > + if (!a || !b) > + return false; > + return (sink_ops(a) == sink_ops(b)) && > + (a->subtype.sink_subtype == b->subtype.sink_subtype); > +} > + > static void *etm_setup_aux(struct perf_event *event, void **pages, > int nr_pages, bool overwrite) > { > u32 id; > int cpu = event->cpu; > cpumask_t *mask; > - struct coresight_device *sink; > + struct coresight_device *sink = NULL; > struct etm_event_data *event_data = NULL; > + bool sink_forced = false; > > event_data = alloc_event_data(cpu); > if (!event_data) > @@ -222,6 +236,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > if (event->attr.config2) { > id = (u32)event->attr.config2; > sink = coresight_get_sink_by_id(id); > + sink_forced = true; > } > > mask = &event_data->mask; > @@ -235,7 +250,7 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > */ > for_each_cpu(cpu, mask) { > struct list_head *path; > - struct coresight_device *csdev; > + struct coresight_device *csdev, *cpu_sink; > > csdev = per_cpu(csdev_src, cpu); > /* > @@ -243,33 +258,42 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > * the mask and continue with the rest. If ever we try to trace > * on this CPU, we handle it accordingly. > */ > - if (!csdev) { > - cpumask_clear_cpu(cpu, mask); > - continue; > - } > - > + if (!csdev) > + goto clear_cpu; > /* > - * No sink provided - look for a default sink for one of the > - * devices. At present we only support topology where all CPUs > - * use the same sink [N:1], so only need to find one sink. The > - * coresight_build_path later will remove any CPU that does not > - * attach to the sink, or if we have not found a sink. > + * No sink provided - look for a default sink for all the devices. > + * We only support multiple sinks, only if all the default sinks > + * are of the same type, so that the sink buffer can be shared > + * as the event moves around. As earlier, we don't trace on a > + * CPU, if we can't find a suitable sink. > */ > - if (!sink) > - sink = coresight_find_default_sink(csdev); > + if (!sink_forced) { > + cpu_sink = coresight_find_default_sink(csdev); > + if (!cpu_sink) > + goto clear_cpu; > + /* First sink for this event */ > + if (!sink) { > + sink = cpu_sink; > + } else if (!sinks_match(cpu_sink, sink)) { > + goto clear_cpu; > + } > + > + } else { > + cpu_sink = sink; > + } > > /* > * Building a path doesn't enable it, it simply builds a > * list of devices from source to sink that can be > * referenced later when the path is actually needed. > */ > - path = coresight_build_path(csdev, sink); > - if (IS_ERR(path)) { > - cpumask_clear_cpu(cpu, mask); > + path = coresight_build_path(csdev, cpu_sink); > + if (!IS_ERR(path)) { > + *etm_event_cpu_path_ptr(event_data, cpu) = path; > continue; > } > - > - *etm_event_cpu_path_ptr(event_data, cpu) = path; > +clear_cpu: > + cpumask_clear_cpu(cpu, mask); > } > > /* no sink found for any CPU - cannot trace */ > @@ -284,7 +308,12 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > if (!sink_ops(sink)->alloc_buffer || !sink_ops(sink)->free_buffer) > goto err; > > - /* Allocate the sink buffer for this session */ > + /* > + * Allocate the sink buffer for this session. All the sinks > + * where this event can be scheduled are ensured to be of the > + * same type. Thus the same sink configuration is used by the > + * sinks. > + */ > event_data->snk_config = > sink_ops(sink)->alloc_buffer(sink, event, pages, > nr_pages, overwrite); > -- > 2.24.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel