From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/3] drm/i915: Do drm_mode_config_reset() after HPD init
Date: Tue, 6 Oct 2020 21:58:08 +0300 [thread overview]
Message-ID: <20201006185809.4655-2-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20201006185809.4655-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
LSPCON requires HPD detection logic to be enabled when we call
its .reset() hook during resume, to check the live state of the
pin. To that end let's reorder the resume sequence such that
we do HPD init before the encoder reset.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b2a050d916e3..66ddd4161885 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1213,21 +1213,20 @@ static int i915_drm_resume(struct drm_device *dev)
* GPU will hang. i915_gem_init_hw() will initiate batches to
* update/restore the context.
*
- * drm_mode_config_reset() needs AUX interrupts.
- *
* Modeset enabling in intel_modeset_init_hw() also needs working
* interrupts.
*/
intel_runtime_pm_enable_interrupts(dev_priv);
- drm_mode_config_reset(dev);
-
i915_gem_resume(dev_priv);
intel_modeset_init_hw(dev_priv);
intel_init_clock_gating(dev_priv);
intel_hpd_init(dev_priv);
+ /* May need AUX interrupts and HPD detection enabled */
+ drm_mode_config_reset(dev);
+
/* MST sideband requires HPD interrupts enabled */
intel_dp_mst_resume(dev_priv);
intel_display_resume(dev);
--
2.26.2
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next prev parent reply other threads:[~2020-10-06 18:59 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-06 18:58 [Intel-gfx] [PATCH 1/3] drm/i915: Reorder hpd init vs. display resume Ville Syrjala
2020-10-06 18:58 ` Ville Syrjala [this message]
2020-10-12 20:16 ` [Intel-gfx] [PATCH 2/3] drm/i915: Do drm_mode_config_reset() after HPD init Imre Deak
2020-10-19 15:39 ` Imre Deak
2020-10-19 15:58 ` Ville Syrjälä
2020-10-06 18:58 ` [Intel-gfx] [PATCH 3/3] drm/i915: Refactor .hpd_irq_setup() calls a bit Ville Syrjala
2020-10-12 20:22 ` Imre Deak
2020-10-06 19:27 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915: Reorder hpd init vs. display resume Patchwork
2020-10-07 11:06 ` [Intel-gfx] [PATCH 1/3] " Ville Syrjälä
2020-10-07 19:22 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2020-10-07 22:15 ` Lyude Paul
2020-10-08 8:19 ` Ville Syrjälä
2020-10-12 19:36 ` Imre Deak
2020-10-13 13:39 ` Ville Syrjälä
2020-10-13 18:11 ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2020-10-19 15:38 ` Imre Deak
2020-10-19 16:52 ` Lyude Paul
2020-10-08 11:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915: Reorder hpd init vs. display resume (rev2) Patchwork
2020-10-08 12:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-08 17:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/3] drm/i915: Reorder hpd init vs. display resume (rev3) Patchwork
2020-10-08 17:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-08 19:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-10-13 18:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/3] drm/i915: Reorder hpd init vs. display resume (rev4) Patchwork
2020-10-13 18:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-14 14:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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