From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_BASE64_TEXT,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CBC6C04EBE for ; Thu, 8 Oct 2020 11:33:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EEAAB2145D for ; Thu, 8 Oct 2020 11:33:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iFp69IHF" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729849AbgJHLd3 (ORCPT ); Thu, 8 Oct 2020 07:33:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:47557 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729829AbgJHLd1 (ORCPT ); Thu, 8 Oct 2020 07:33:27 -0400 X-UUID: 2c92eaa616ee47df8c7d03ead87aa5f0-20201008 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=eDsG0jlH0SbkNBK6qh4H39uup3IqO1o0uLrj6K7Zkvc=; b=iFp69IHF1ba7iiIZiVRA9WvDN9N148PAAhBahz/h9q/qhbqwKH0hbtLJO54GXNGOMTn1mhCD+vh2Kgu8xyuVWZCpNJWIYYJMMt53tw50EaY689RL6v9wCEg6Otot8B+r3Gq8H3kJ4T6Wjhu57irJIrTLKK7tt09tRrJv55KDpDg=; X-UUID: 2c92eaa616ee47df8c7d03ead87aa5f0-20201008 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 717460526; Thu, 08 Oct 2020 19:33:21 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Oct 2020 19:33:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Oct 2020 19:33:14 +0800 From: Shayne Chen To: Felix Fietkau CC: linux-wireless , Lorenzo Bianconi , Ryder Lee , "Evelyn Tsai" , linux-mediatek , Shayne Chen Subject: [PATCH 08/10] mt76: mt7915: implement testmode rx support Date: Thu, 8 Oct 2020 19:29:02 +0800 Message-ID: <20201008112904.10620-8-shayne.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201008112904.10620-1-shayne.chen@mediatek.com> References: <20201008112904.10620-1-shayne.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org U3VwcG9ydCB0ZXN0bW9kZSByeCBhbmQgZGlzcGxheSByeCBzdGF0aXN0aWMgYnkgcGFyc2luZyBS WFYgcGFja2V0DQp0eXBlLCB3aGljaCBpcyBjdXJyZW50bHkgb25seSBlbmFibGVkIGluIHRlc3Rt b2RlLg0KDQpTaWduZWQtb2ZmLWJ5OiBTaGF5bmUgQ2hlbiA8c2hheW5lLmNoZW5AbWVkaWF0ZWsu Y29tPg0KUmV2aWV3ZWQtYnk6IFJ5ZGVyIExlZSA8cnlkZXIubGVlQG1lZGlhdGVrLmNvbT4NCi0t LQ0KIC4uLi9uZXQvd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvZG1hLmMgICB8ICAzICsN CiAuLi4vbmV0L3dpcmVsZXNzL21lZGlhdGVrL210NzYvbXQ3OTE1L21hYy5jICAgfCAzNyArKysr KysrDQogLi4uL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS9tYWMuaCAgIHwgIDUg Kw0KIC4uLi9uZXQvd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvbWN1LmggICB8ICAxICsN CiAuLi4vd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvbXQ3OTE1LmggICAgfCAgNyArKw0K IC4uLi93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS90ZXN0bW9kZS5jICB8IDk3ICsrKysr KysrKysrKysrKysrKysNCiAuLi4vd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvdGVzdG1v ZGUuaCAgfCAzMCArKysrKysNCiA3IGZpbGVzIGNoYW5nZWQsIDE4MCBpbnNlcnRpb25zKCspDQoN CmRpZmYgLS1naXQgYS9kcml2ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS9k bWEuYyBiL2RyaXZlcnMvbmV0L3dpcmVsZXNzL21lZGlhdGVrL210NzYvbXQ3OTE1L2RtYS5jDQpp bmRleCBjZmExMmM0Li5lMTQ4MTRkIDEwMDY0NA0KLS0tIGEvZHJpdmVycy9uZXQvd2lyZWxlc3Mv bWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvZG1hLmMNCisrKyBiL2RyaXZlcnMvbmV0L3dpcmVsZXNzL21l ZGlhdGVrL210NzYvbXQ3OTE1L2RtYS5jDQpAQCAtNjEsNiArNjEsOSBAQCB2b2lkIG10NzkxNV9x dWV1ZV9yeF9za2Ioc3RydWN0IG10NzZfZGV2ICptZGV2LCBlbnVtIG10NzZfcnhxX2lkIHEsDQog CWNhc2UgUEtUX1RZUEVfUlhfRVZFTlQ6DQogCQltdDc5MTVfbWN1X3J4X2V2ZW50KGRldiwgc2ti KTsNCiAJCWJyZWFrOw0KKwljYXNlIFBLVF9UWVBFX1RYUlhWOg0KKwkJbXQ3OTE1X21hY19maWxs X3J4X3ZlY3RvcihkZXYsIHNrYik7DQorCQlicmVhazsNCiAJY2FzZSBQS1RfVFlQRV9OT1JNQUw6 DQogCQlpZiAoIW10NzkxNV9tYWNfZmlsbF9yeChkZXYsIHNrYikpIHsNCiAJCQltdDc2X3J4KCZk ZXYtPm10NzYsIHEsIHNrYik7DQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9uZXQvd2lyZWxlc3MvbWVk aWF0ZWsvbXQ3Ni9tdDc5MTUvbWFjLmMgYi9kcml2ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9t dDc2L210NzkxNS9tYWMuYw0KaW5kZXggZTAzZTEyZi4uZWMzMGRkMiAxMDA2NDQNCi0tLSBhL2Ry aXZlcnMvbmV0L3dpcmVsZXNzL21lZGlhdGVrL210NzYvbXQ3OTE1L21hYy5jDQorKysgYi9kcml2 ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS9tYWMuYw0KQEAgLTU2Miw2ICs1 NjIsNDMgQEAgaW50IG10NzkxNV9tYWNfZmlsbF9yeChzdHJ1Y3QgbXQ3OTE1X2RldiAqZGV2LCBz dHJ1Y3Qgc2tfYnVmZiAqc2tiKQ0KIAlyZXR1cm4gMDsNCiB9DQogDQordm9pZCBtdDc5MTVfbWFj X2ZpbGxfcnhfdmVjdG9yKHN0cnVjdCBtdDc5MTVfZGV2ICpkZXYsIHN0cnVjdCBza19idWZmICpz a2IpDQorew0KKyNpZmRlZiBDT05GSUdfTkw4MDIxMV9URVNUTU9ERQ0KKwlfX2xlMzIgKnJ4ZCA9 IChfX2xlMzIgKilza2ItPmRhdGE7DQorCV9fbGUzMiAqcnh2ID0gcnhkICsgNDsNCisJdTMyIHJj cGksIGliX3Jzc2ksIHdiX3Jzc2ksIHYyMCwgdjIxOw0KKwlzMzIgZm9lLCBzbnI7DQorCWludCBp Ow0KKw0KKwlyY3BpID0gbGUzMl90b19jcHUocnh2WzZdKTsNCisJaWJfcnNzaSA9IGxlMzJfdG9f Y3B1KHJ4dls3XSk7DQorCXdiX3Jzc2kgPSBsZTMyX3RvX2NwdShyeHZbOF0pID4+IDU7DQorDQor CWZvciAoaSA9IDA7IGkgPCA0OyBpKyssIHJjcGkgPj49IDgsIGliX3Jzc2kgPj49IDgsIHdiX3Jz c2kgPj49IDkpIHsNCisJCWlmIChpID09IDMpDQorCQkJd2JfcnNzaSA9IGxlMzJfdG9fY3B1KHJ4 dls5XSk7DQorDQorCQlkZXYtPnRlc3QubGFzdF9yY3BpW2ldID0gcmNwaSAmIDB4ZmY7DQorCQlk ZXYtPnRlc3QubGFzdF9pYl9yc3NpW2ldID0gaWJfcnNzaSAmIDB4ZmY7DQorCQlkZXYtPnRlc3Qu bGFzdF93Yl9yc3NpW2ldID0gd2JfcnNzaSAmIDB4ZmY7DQorCX0NCisNCisJdjIwID0gbGUzMl90 b19jcHUocnh2WzIwXSk7DQorCXYyMSA9IGxlMzJfdG9fY3B1KHJ4dlsyMV0pOw0KKw0KKwlmb2Ug PSBGSUVMRF9HRVQoTVRfQ1JYVl9GT0VfTE8sIHYyMCkgfA0KKwkgICAgICAoRklFTERfR0VUKE1U X0NSWFZfRk9FX0hJLCB2MjEpIDw8IE1UX0NSWFZfRk9FX1NISUZUKTsNCisNCisJc25yID0gRklF TERfR0VUKE1UX0NSWFZfU05SLCB2MjApIC0gMTY7DQorDQorCWRldi0+dGVzdC5sYXN0X2ZyZXFf b2Zmc2V0ID0gZm9lOw0KKwlkZXYtPnRlc3QubGFzdF9zbnIgPSBzbnI7DQorDQorCWRldl9rZnJl ZV9za2Ioc2tiKTsNCisjZW5kaWYNCit9DQorDQogc3RhdGljIHUxNg0KIG10NzkxNV9tYWNfdHhf cmF0ZV92YWwoc3RydWN0IG10NzZfcGh5ICptcGh5LCB1OCBtb2RlLCB1OCByYXRlX2lkeCwNCiAJ CSAgICAgICB1OCBuc3MsIHU4IHN0YmMsIHU4ICpidykNCmRpZmYgLS1naXQgYS9kcml2ZXJzL25l dC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS9tYWMuaCBiL2RyaXZlcnMvbmV0L3dpcmVs ZXNzL21lZGlhdGVrL210NzYvbXQ3OTE1L21hYy5oDQppbmRleCAwOTIxYjZmLi5kNDIwMzkyIDEw MDY0NA0KLS0tIGEvZHJpdmVycy9uZXQvd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvbWFj LmgNCisrKyBiL2RyaXZlcnMvbmV0L3dpcmVsZXNzL21lZGlhdGVrL210NzYvbXQ3OTE1L21hYy5o DQpAQCAtMTI4LDYgKzEyOCwxMSBAQCBlbnVtIHJ4X3BrdF90eXBlIHsNCiAjZGVmaW5lIE1UX0NS WFZfSEVfQkVBTV9DSE5HCQlCSVQoMTMpDQogI2RlZmluZSBNVF9DUlhWX0hFX0RPUFBMRVIJCUJJ VCgxNikNCiANCisjZGVmaW5lIE1UX0NSWFZfU05SCQlHRU5NQVNLKDE4LCAxMykNCisjZGVmaW5l IE1UX0NSWFZfRk9FX0xPCQlHRU5NQVNLKDMxLCAxOSkNCisjZGVmaW5lIE1UX0NSWFZfRk9FX0hJ CQlHRU5NQVNLKDYsIDApDQorI2RlZmluZSBNVF9DUlhWX0ZPRV9TSElGVAkxMw0KKw0KIGVudW0g dHhfaGVhZGVyX2Zvcm1hdCB7DQogCU1UX0hEUl9GT1JNQVRfODAyXzMsDQogCU1UX0hEUl9GT1JN QVRfQ01ELA0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvbmV0L3dpcmVsZXNzL21lZGlhdGVrL210NzYv bXQ3OTE1L21jdS5oIGIvZHJpdmVycy9uZXQvd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUv bWN1LmgNCmluZGV4IDBhN2U5ZDIuLjg5NDUzYTYgMTAwNjQ0DQotLS0gYS9kcml2ZXJzL25ldC93 aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS9tY3UuaA0KKysrIGIvZHJpdmVycy9uZXQvd2ly ZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvbWN1LmgNCkBAIC00OCw2ICs0OCw3IEBAIGVudW0g ew0KIA0KIGVudW0gew0KIAlNQ1VfQVRFX1NFVF9UUlggPSAweDEsDQorCU1DVV9BVEVfU0VUX1JY X0ZJTFRFUiA9IDB4MywNCiB9Ow0KIA0KIHN0cnVjdCBtdDc5MTVfbWN1X3J4ZCB7DQpkaWZmIC0t Z2l0IGEvZHJpdmVycy9uZXQvd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvbXQ3OTE1Lmgg Yi9kcml2ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS9tdDc5MTUuaA0KaW5k ZXggNjczNTkxNS4uOGViZmVkOCAxMDA2NDQNCi0tLSBhL2RyaXZlcnMvbmV0L3dpcmVsZXNzL21l ZGlhdGVrL210NzYvbXQ3OTE1L210NzkxNS5oDQorKysgYi9kcml2ZXJzL25ldC93aXJlbGVzcy9t ZWRpYXRlay9tdDc2L210NzkxNS9tdDc5MTUuaA0KQEAgLTE2NSw2ICsxNjUsMTIgQEAgc3RydWN0 IG10NzkxNV9kZXYgew0KIAlzdHJ1Y3Qgew0KIAkJdTMyICpyZWdfYmFja3VwOw0KIA0KKwkJczMy IGxhc3RfZnJlcV9vZmZzZXQ7DQorCQl1OCBsYXN0X3JjcGlbNF07DQorCQlzOCBsYXN0X2liX3Jz c2lbNF07DQorCQlzOCBsYXN0X3diX3Jzc2lbNF07DQorCQlzMzIgbGFzdF9zbnI7DQorDQogCQl1 OCBzcGVfaWR4Ow0KIAl9IHRlc3Q7DQogI2VuZGlmDQpAQCAtNDM2LDYgKzQ0Miw3IEBAIHZvaWQg bXQ3OTE1X21hY193cml0ZV90eHdpKHN0cnVjdCBtdDc5MTVfZGV2ICpkZXYsIF9fbGUzMiAqdHh3 aSwNCiAJCQkgICBzdHJ1Y3QgaWVlZTgwMjExX2tleV9jb25mICprZXksIGJvb2wgYmVhY29uKTsN CiB2b2lkIG10NzkxNV9tYWNfc2V0X3RpbWluZyhzdHJ1Y3QgbXQ3OTE1X3BoeSAqcGh5KTsNCiBp bnQgbXQ3OTE1X21hY19maWxsX3J4KHN0cnVjdCBtdDc5MTVfZGV2ICpkZXYsIHN0cnVjdCBza19i dWZmICpza2IpOw0KK3ZvaWQgbXQ3OTE1X21hY19maWxsX3J4X3ZlY3RvcihzdHJ1Y3QgbXQ3OTE1 X2RldiAqZGV2LCBzdHJ1Y3Qgc2tfYnVmZiAqc2tiKTsNCiB2b2lkIG10NzkxNV9tYWNfdHhfZnJl ZShzdHJ1Y3QgbXQ3OTE1X2RldiAqZGV2LCBzdHJ1Y3Qgc2tfYnVmZiAqc2tiKTsNCiBpbnQgbXQ3 OTE1X21hY19zdGFfYWRkKHN0cnVjdCBtdDc2X2RldiAqbWRldiwgc3RydWN0IGllZWU4MDIxMV92 aWYgKnZpZiwNCiAJCSAgICAgICBzdHJ1Y3QgaWVlZTgwMjExX3N0YSAqc3RhKTsNCmRpZmYgLS1n aXQgYS9kcml2ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS90ZXN0bW9kZS5j IGIvZHJpdmVycy9uZXQvd2lyZWxlc3MvbWVkaWF0ZWsvbXQ3Ni9tdDc5MTUvdGVzdG1vZGUuYw0K aW5kZXggNTNmYzk3Ny4uY2M1YWI5OCAxMDA2NDQNCi0tLSBhL2RyaXZlcnMvbmV0L3dpcmVsZXNz L21lZGlhdGVrL210NzYvbXQ3OTE1L3Rlc3Rtb2RlLmMNCisrKyBiL2RyaXZlcnMvbmV0L3dpcmVs ZXNzL21lZGlhdGVrL210NzYvbXQ3OTE1L3Rlc3Rtb2RlLmMNCkBAIC0xMTMsNiArMTEzLDMxIEBA IG10NzkxNV90bV9yZWdfYmFja3VwX3Jlc3RvcmUoc3RydWN0IG10NzkxNV9kZXYgKmRldiwgc3Ry dWN0IG10NzkxNV9waHkgKnBoeSkNCiAJbXQ3Nl9jbGVhcihkZXYsIE1UX1RNQUNfVENSMCgwKSwg TVRfVE1BQ19UQ1IwX1RCVFRfU1RPUF9DVFJMKTsNCiB9DQogDQorc3RhdGljIGludA0KK210Nzkx NV90bV9jb25maWdfcnhfZmlsdGVyKHN0cnVjdCBtdDc5MTVfZGV2ICpkZXYsIGJvb2wgZW4pDQor ew0KKwlzdHJ1Y3QgbXQ3OTE1X3RtX2NtZCByZXEgPSB7DQorCQkudGVzdG1vZGVfZW4gPSAxLA0K KwkJLnBhcmFtX2lkeCA9IE1DVV9BVEVfU0VUX1JYX0ZJTFRFUiwNCisJCS5wYXJhbS5maWx0ZXIu cmVwb3J0X2VuID0gZW4sDQorCQkucGFyYW0uZmlsdGVyLmJhbmQgPSAwLA0KKwl9Ow0KKwlfX2xl MzIgbWFzayA9IFJYX0ZJTFRFUl9OT1RfT1dOX0JUSU0gfA0KKwkJICAgICAgUlhfRklMVEVSX05P VF9PV05fVUNBU1QgfA0KKwkJICAgICAgUlhfRklMVEVSX1JUUyB8IFJYX0ZJTFRFUl9DVFMgfA0K KwkJICAgICAgUlhfRklMVEVSX0NUUkxfUlNWIHwNCisJCSAgICAgIFJYX0ZJTFRFUl9CQ19NQ19C U1NJRF9BMiB8DQorCQkgICAgICBSWF9GSUxURVJfQkNfTUNfQlNTSURfQTMgfA0KKwkJICAgICAg UlhfRklMVEVSX0JDX01DX09NQUNfQTMgfA0KKwkJICAgICAgUlhfRklMVEVSX1BST1RPQ09MX1ZF UlNJT04gfA0KKwkJICAgICAgUlhfRklMVEVSX0ZDU19FUlI7DQorDQorCXJlcS5wYXJhbS5maWx0 ZXIubWFzayA9IGNwdV90b19sZTMyKG1hc2spOw0KKw0KKwlyZXR1cm4gbXQ3Nl9tY3Vfc2VuZF9t c2coJmRldi0+bXQ3NiwgTUNVX0VYVF9DTURfQVRFX0NUUkwsICZyZXEsDQorCQkJCSBzaXplb2Yo cmVxKSwgZmFsc2UpOw0KK30NCisNCiBzdGF0aWMgdm9pZA0KIG10NzkxNV90bV9pbml0KHN0cnVj dCBtdDc5MTVfZGV2ICpkZXYpDQogew0KQEAgLTEyNCw2ICsxNDksNyBAQCBtdDc5MTVfdG1faW5p dChzdHJ1Y3QgbXQ3OTE1X2RldiAqZGV2KQ0KIAltdDc5MTVfdG1fbW9kZV9jdHJsKGRldiwgZW4p Ow0KIAltdDc5MTVfdG1fcmVnX2JhY2t1cF9yZXN0b3JlKGRldiwgJmRldi0+cGh5KTsNCiAJbXQ3 OTE1X3RtX3NldF90cngoZGV2LCAmZGV2LT5waHksIFRNX01BQ19UWFJYLCAhZW4pOw0KKwltdDc5 MTVfdG1fY29uZmlnX3J4X2ZpbHRlcihkZXYsIGVuKTsNCiB9DQogDQogc3RhdGljIHZvaWQNCkBA IC0xNTYsNiArMTgyLDIwIEBAIG10NzkxNV90bV9zZXRfdHhfZnJhbWVzKHN0cnVjdCBtdDc5MTVf ZGV2ICpkZXYsIGJvb2wgZW4pDQogCWluZm8tPmNvbnRyb2wudmlmID0gZGV2LT5waHkubW9uaXRv cl92aWY7DQogfQ0KIA0KK3N0YXRpYyB2b2lkDQorbXQ3OTE1X3RtX3NldF9yeF9mcmFtZXMoc3Ry dWN0IG10NzkxNV9kZXYgKmRldiwgYm9vbCBlbikNCit7DQorCWlmIChlbikgew0KKwkJbXV0ZXhf dW5sb2NrKCZkZXYtPm10NzYubXV0ZXgpOw0KKwkJbXQ3OTE1X3NldF9jaGFubmVsKCZkZXYtPnBo eSk7DQorCQltdXRleF9sb2NrKCZkZXYtPm10NzYubXV0ZXgpOw0KKw0KKwkJbXQ3OTE1X21jdV9z ZXRfY2hhbl9pbmZvKCZkZXYtPnBoeSwgTUNVX0VYVF9DTURfU0VUX1JYX1BBVEgpOw0KKwl9DQor DQorCW10NzkxNV90bV9zZXRfdHJ4KGRldiwgJmRldi0+cGh5LCBUTV9NQUNfUlhfUlhWLCBlbik7 DQorfQ0KKw0KIHN0YXRpYyBpbnQNCiBtdDc5MTVfdG1fc2V0X3N0YXRlKHN0cnVjdCBtdDc2X2Rl diAqbWRldiwgZW51bSBtdDc2X3Rlc3Rtb2RlX3N0YXRlIHN0YXRlKQ0KIHsNCkBAIC0xNjksMTIg KzIwOSw2OSBAQCBtdDc5MTVfdG1fc2V0X3N0YXRlKHN0cnVjdCBtdDc2X2RldiAqbWRldiwgZW51 bSBtdDc2X3Rlc3Rtb2RlX3N0YXRlIHN0YXRlKQ0KIAkJbXQ3OTE1X3RtX3NldF90eF9mcmFtZXMo ZGV2LCBmYWxzZSk7DQogCWVsc2UgaWYgKHN0YXRlID09IE1UNzZfVE1fU1RBVEVfVFhfRlJBTUVT KQ0KIAkJbXQ3OTE1X3RtX3NldF90eF9mcmFtZXMoZGV2LCB0cnVlKTsNCisJZWxzZSBpZiAocHJl dl9zdGF0ZSA9PSBNVDc2X1RNX1NUQVRFX1JYX0ZSQU1FUykNCisJCW10NzkxNV90bV9zZXRfcnhf ZnJhbWVzKGRldiwgZmFsc2UpOw0KKwllbHNlIGlmIChzdGF0ZSA9PSBNVDc2X1RNX1NUQVRFX1JY X0ZSQU1FUykNCisJCW10NzkxNV90bV9zZXRfcnhfZnJhbWVzKGRldiwgdHJ1ZSk7DQogCWVsc2Ug aWYgKHByZXZfc3RhdGUgPT0gTVQ3Nl9UTV9TVEFURV9PRkYgfHwgc3RhdGUgPT0gTVQ3Nl9UTV9T VEFURV9PRkYpDQogCQltdDc5MTVfdG1faW5pdChkZXYpOw0KIA0KIAlyZXR1cm4gMDsNCiB9DQog DQorc3RhdGljIGludA0KK210NzkxNV90bV9kdW1wX3N0YXRzKHN0cnVjdCBtdDc2X2RldiAqbWRl diwgc3RydWN0IHNrX2J1ZmYgKm1zZykNCit7DQorCXN0cnVjdCBtdDc5MTVfZGV2ICpkZXYgPSBj b250YWluZXJfb2YobWRldiwgc3RydWN0IG10NzkxNV9kZXYsIG10NzYpOw0KKwl2b2lkICpyeCwg KnJzc2k7DQorCWludCBpOw0KKw0KKwlyeCA9IG5sYV9uZXN0X3N0YXJ0KG1zZywgTVQ3Nl9UTV9T VEFUU19BVFRSX0xBU1RfUlgpOw0KKwlpZiAoIXJ4KQ0KKwkJcmV0dXJuIC1FTk9NRU07DQorDQor CWlmIChubGFfcHV0X3MzMihtc2csIE1UNzZfVE1fUlhfQVRUUl9GUkVRX09GRlNFVCwgZGV2LT50 ZXN0Lmxhc3RfZnJlcV9vZmZzZXQpKQ0KKwkJcmV0dXJuIC1FTk9NRU07DQorDQorCXJzc2kgPSBu bGFfbmVzdF9zdGFydChtc2csIE1UNzZfVE1fUlhfQVRUUl9SQ1BJKTsNCisJaWYgKCFyc3NpKQ0K KwkJcmV0dXJuIC1FTk9NRU07DQorDQorCWZvciAoaSA9IDA7IGkgPCBBUlJBWV9TSVpFKGRldi0+ dGVzdC5sYXN0X3JjcGkpOyBpKyspDQorCQlpZiAobmxhX3B1dF91OChtc2csIGksIGRldi0+dGVz dC5sYXN0X3JjcGlbaV0pKQ0KKwkJCXJldHVybiAtRU5PTUVNOw0KKw0KKwlubGFfbmVzdF9lbmQo bXNnLCByc3NpKTsNCisNCisJcnNzaSA9IG5sYV9uZXN0X3N0YXJ0KG1zZywgTVQ3Nl9UTV9SWF9B VFRSX0lCX1JTU0kpOw0KKwlpZiAoIXJzc2kpDQorCQlyZXR1cm4gLUVOT01FTTsNCisNCisJZm9y IChpID0gMDsgaSA8IEFSUkFZX1NJWkUoZGV2LT50ZXN0Lmxhc3RfaWJfcnNzaSk7IGkrKykNCisJ CWlmIChubGFfcHV0X3M4KG1zZywgaSwgZGV2LT50ZXN0Lmxhc3RfaWJfcnNzaVtpXSkpDQorCQkJ cmV0dXJuIC1FTk9NRU07DQorDQorCW5sYV9uZXN0X2VuZChtc2csIHJzc2kpOw0KKw0KKwlyc3Np ID0gbmxhX25lc3Rfc3RhcnQobXNnLCBNVDc2X1RNX1JYX0FUVFJfV0JfUlNTSSk7DQorCWlmICgh cnNzaSkNCisJCXJldHVybiAtRU5PTUVNOw0KKw0KKwlmb3IgKGkgPSAwOyBpIDwgQVJSQVlfU0la RShkZXYtPnRlc3QubGFzdF93Yl9yc3NpKTsgaSsrKQ0KKwkJaWYgKG5sYV9wdXRfczgobXNnLCBp LCBkZXYtPnRlc3QubGFzdF93Yl9yc3NpW2ldKSkNCisJCQlyZXR1cm4gLUVOT01FTTsNCisNCisJ bmxhX25lc3RfZW5kKG1zZywgcnNzaSk7DQorDQorCWlmIChubGFfcHV0X3MzMihtc2csIE1UNzZf VE1fUlhfQVRUUl9TTlIsIGRldi0+dGVzdC5sYXN0X3NucikpDQorCQlyZXR1cm4gLUVOT01FTTsN CisNCisJbmxhX25lc3RfZW5kKG1zZywgcngpOw0KKw0KKwlyZXR1cm4gMDsNCit9DQorDQogY29u c3Qgc3RydWN0IG10NzZfdGVzdG1vZGVfb3BzIG10NzkxNV90ZXN0bW9kZV9vcHMgPSB7DQogCS5z ZXRfc3RhdGUgPSBtdDc5MTVfdG1fc2V0X3N0YXRlLA0KKwkuZHVtcF9zdGF0cyA9IG10NzkxNV90 bV9kdW1wX3N0YXRzLA0KIH07DQpkaWZmIC0tZ2l0IGEvZHJpdmVycy9uZXQvd2lyZWxlc3MvbWVk aWF0ZWsvbXQ3Ni9tdDc5MTUvdGVzdG1vZGUuaCBiL2RyaXZlcnMvbmV0L3dpcmVsZXNzL21lZGlh dGVrL210NzYvbXQ3OTE1L3Rlc3Rtb2RlLmgNCmluZGV4IDA0ZjRhMmMuLmIzNDRhNjQgMTAwNjQ0 DQotLS0gYS9kcml2ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS90ZXN0bW9k ZS5oDQorKysgYi9kcml2ZXJzL25ldC93aXJlbGVzcy9tZWRpYXRlay9tdDc2L210NzkxNS90ZXN0 bW9kZS5oDQpAQCAtMTEsNiArMTEsMTUgQEAgc3RydWN0IG10NzkxNV90bV90cnggew0KIAl1OCBy c3Y7DQogfTsNCiANCitzdHJ1Y3QgbXQ3OTE1X3RtX3J4X2ZpbHRlciB7DQorCXU4IHByb21pc2N1 b3VzOw0KKwl1OCByZXBvcnRfZW47DQorCXU4IGJhbmQ7DQorCXU4IF9yc3Y7DQorCV9fbGUzMiBt YXNrOw0KKwl1OCBfcnN2MVs0XTsNCit9Ow0KKw0KIHN0cnVjdCBtdDc5MTVfdG1fY21kIHsNCiAJ dTggdGVzdG1vZGVfZW47DQogCXU4IHBhcmFtX2lkeDsNCkBAIC0xOCw2ICsyNyw3IEBAIHN0cnVj dCBtdDc5MTVfdG1fY21kIHsNCiAJdW5pb24gew0KIAkJX19sZTMyIGRhdGE7DQogCQlzdHJ1Y3Qg bXQ3OTE1X3RtX3RyeCB0cng7DQorCQlzdHJ1Y3QgbXQ3OTE1X3RtX3J4X2ZpbHRlciBmaWx0ZXI7 DQogCQl1OCB0ZXN0WzcyXTsNCiAJfSBwYXJhbTsNCiB9IF9fcGFja2VkOw0KQEAgLTMxLDQgKzQx LDI0IEBAIGVudW0gew0KIAlUTV9NQUNfUlhfUlhWLA0KIH07DQogDQorI2RlZmluZSBSWF9GSUxU RVJfU1RCQ19CQ05fQkNfTUMJQklUKDApDQorI2RlZmluZSBSWF9GSUxURVJfRkNTX0VSUgkJQklU KDEpDQorI2RlZmluZSBSWF9GSUxURVJfUFJPVE9DT0xfVkVSU0lPTglCSVQoMikNCisjZGVmaW5l IFJYX0ZJTFRFUl9QUk9CX1JFUQkJQklUKDMpDQorI2RlZmluZSBSWF9GSUxURVJfTUNBU1QJCQlC SVQoNCkNCisjZGVmaW5lIFJYX0ZJTFRFUl9CQ0FTVAkJCUJJVCg1KQ0KKyNkZWZpbmUgUlhfRklM VEVSX01DQVNUX1RBQkxFCQlCSVQoNikNCisjZGVmaW5lIFJYX0ZJTFRFUl9CQ19NQ19PTUFDX0Ez CQlCSVQoNykNCisjZGVmaW5lIFJYX0ZJTFRFUl9CQ19NQ19CU1NJRF9BMwlCSVQoOCkNCisjZGVm aW5lIFJYX0ZJTFRFUl9CQ19NQ19CU1NJRF9BMglCSVQoOSkNCisjZGVmaW5lIFJYX0ZJTFRFUl9C Q05fQlNTSUQJCUJJVCgxMCkNCisjZGVmaW5lIFJYX0ZJTFRFUl9DVFJMX1JTVgkJQklUKDExKQ0K KyNkZWZpbmUgUlhfRklMVEVSX0NUUwkJCUJJVCgxMikNCisjZGVmaW5lIFJYX0ZJTFRFUl9SVFMJ CQlCSVQoMTMpDQorI2RlZmluZSBSWF9GSUxURVJfRFVQTElDQVRFCQlCSVQoMTQpDQorI2RlZmlu ZSBSWF9GSUxURVJfTk9UX09XTl9CU1NJRAkJQklUKDE1KQ0KKyNkZWZpbmUgUlhfRklMVEVSX05P VF9PV05fVUNBU1QJCUJJVCgxNikNCisjZGVmaW5lIFJYX0ZJTFRFUl9OT1RfT1dOX0JUSU0JCUJJ VCgxNykNCisjZGVmaW5lIFJYX0ZJTFRFUl9ORFBBCQkJQklUKDE4KQ0KKw0KICNlbmRpZg0KLS0g DQoyLjE3LjENCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE639C4363A for ; Thu, 8 Oct 2020 11:33:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 51CC12145D for ; Thu, 8 Oct 2020 11:33:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Qp6vN2Yn"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iFp69IHF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 51CC12145D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3ZQgG5ALP/bgtq6xVVUSVVGR1d0aGlxaul2D//mKqmU=; b=Qp6vN2YnMKEBK7MmZtySKiXUn wQTEbaqVvQwkE/nctowNQKi3/LNrQMo8hKVN+s6GmGP15skU8lbqYWUR7wDdaCdL329ujZPaC4MFB m69QZU/L8WCHjpKnbCGpCbGZ//1n1baidI7dT24Flyv7TawG36z/LSdA7Xw2Qy94OzXFI3KwL/RMD 1Va6pxqhLT2x+zUf2jeKAJ+WP7nJw7d4tza6rhvHPW+AdgGMbmUkv1zQqim6JWm4Ud9I4LZH4xmJl FKk/VZVHpFe6SpVS00YTi7pIlYXEA4IRzk8BjnJqYc1tKaXBT5XPti7+agb9l9W0yLv+FxEObDyW1 c1cR6XvMQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQUB4-0003XZ-2F; Thu, 08 Oct 2020 11:33:42 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQUAw-0003T8-Sh for linux-mediatek@lists.infradead.org; Thu, 08 Oct 2020 11:33:38 +0000 X-UUID: 1eff43bdbe0e4b1f96c4265f97a1ec34-20201008 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=eDsG0jlH0SbkNBK6qh4H39uup3IqO1o0uLrj6K7Zkvc=; b=iFp69IHF1ba7iiIZiVRA9WvDN9N148PAAhBahz/h9q/qhbqwKH0hbtLJO54GXNGOMTn1mhCD+vh2Kgu8xyuVWZCpNJWIYYJMMt53tw50EaY689RL6v9wCEg6Otot8B+r3Gq8H3kJ4T6Wjhu57irJIrTLKK7tt09tRrJv55KDpDg=; X-UUID: 1eff43bdbe0e4b1f96c4265f97a1ec34-20201008 Received: from mtkcas68.mediatek.inc [(172.29.94.19)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 347594591; Thu, 08 Oct 2020 03:33:29 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Oct 2020 04:33:27 -0700 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Oct 2020 19:33:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Oct 2020 19:33:14 +0800 From: Shayne Chen To: Felix Fietkau Subject: [PATCH 08/10] mt76: mt7915: implement testmode rx support Date: Thu, 8 Oct 2020 19:29:02 +0800 Message-ID: <20201008112904.10620-8-shayne.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201008112904.10620-1-shayne.chen@mediatek.com> References: <20201008112904.10620-1-shayne.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201008_073335_185846_AE7F6152 X-CRM114-Status: GOOD ( 18.32 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ryder Lee , Evelyn Tsai , linux-wireless , linux-mediatek , Lorenzo Bianconi , Shayne Chen Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Support testmode rx and display rx statistic by parsing RXV packet type, which is currently only enabled in testmode. Signed-off-by: Shayne Chen Reviewed-by: Ryder Lee --- .../net/wireless/mediatek/mt76/mt7915/dma.c | 3 + .../net/wireless/mediatek/mt76/mt7915/mac.c | 37 +++++++ .../net/wireless/mediatek/mt76/mt7915/mac.h | 5 + .../net/wireless/mediatek/mt76/mt7915/mcu.h | 1 + .../wireless/mediatek/mt76/mt7915/mt7915.h | 7 ++ .../wireless/mediatek/mt76/mt7915/testmode.c | 97 +++++++++++++++++++ .../wireless/mediatek/mt76/mt7915/testmode.h | 30 ++++++ 7 files changed, 180 insertions(+) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c index cfa12c4..e14814d 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/dma.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/dma.c @@ -61,6 +61,9 @@ void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, case PKT_TYPE_RX_EVENT: mt7915_mcu_rx_event(dev, skb); break; + case PKT_TYPE_TXRXV: + mt7915_mac_fill_rx_vector(dev, skb); + break; case PKT_TYPE_NORMAL: if (!mt7915_mac_fill_rx(dev, skb)) { mt76_rx(&dev->mt76, q, skb); diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index e03e12f..ec30dd2 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -562,6 +562,43 @@ int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) return 0; } +void mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) +{ +#ifdef CONFIG_NL80211_TESTMODE + __le32 *rxd = (__le32 *)skb->data; + __le32 *rxv = rxd + 4; + u32 rcpi, ib_rssi, wb_rssi, v20, v21; + s32 foe, snr; + int i; + + rcpi = le32_to_cpu(rxv[6]); + ib_rssi = le32_to_cpu(rxv[7]); + wb_rssi = le32_to_cpu(rxv[8]) >> 5; + + for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { + if (i == 3) + wb_rssi = le32_to_cpu(rxv[9]); + + dev->test.last_rcpi[i] = rcpi & 0xff; + dev->test.last_ib_rssi[i] = ib_rssi & 0xff; + dev->test.last_wb_rssi[i] = wb_rssi & 0xff; + } + + v20 = le32_to_cpu(rxv[20]); + v21 = le32_to_cpu(rxv[21]); + + foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | + (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); + + snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; + + dev->test.last_freq_offset = foe; + dev->test.last_snr = snr; + + dev_kfree_skb(skb); +#endif +} + static u16 mt7915_mac_tx_rate_val(struct mt76_phy *mphy, u8 mode, u8 rate_idx, u8 nss, u8 stbc, u8 *bw) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h index 0921b6f..d420392 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.h @@ -128,6 +128,11 @@ enum rx_pkt_type { #define MT_CRXV_HE_BEAM_CHNG BIT(13) #define MT_CRXV_HE_DOPPLER BIT(16) +#define MT_CRXV_SNR GENMASK(18, 13) +#define MT_CRXV_FOE_LO GENMASK(31, 19) +#define MT_CRXV_FOE_HI GENMASK(6, 0) +#define MT_CRXV_FOE_SHIFT 13 + enum tx_header_format { MT_HDR_FORMAT_802_3, MT_HDR_FORMAT_CMD, diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h index 0a7e9d2..89453a6 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mcu.h @@ -48,6 +48,7 @@ enum { enum { MCU_ATE_SET_TRX = 0x1, + MCU_ATE_SET_RX_FILTER = 0x3, }; struct mt7915_mcu_rxd { diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h index 6735915..8ebfed8 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h @@ -165,6 +165,12 @@ struct mt7915_dev { struct { u32 *reg_backup; + s32 last_freq_offset; + u8 last_rcpi[4]; + s8 last_ib_rssi[4]; + s8 last_wb_rssi[4]; + s32 last_snr; + u8 spe_idx; } test; #endif @@ -436,6 +442,7 @@ void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi, struct ieee80211_key_conf *key, bool beacon); void mt7915_mac_set_timing(struct mt7915_phy *phy); int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb); +void mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb); void mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb); int mt7915_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c b/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c index 53fc977..cc5ab98 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/testmode.c @@ -113,6 +113,31 @@ mt7915_tm_reg_backup_restore(struct mt7915_dev *dev, struct mt7915_phy *phy) mt76_clear(dev, MT_TMAC_TCR0(0), MT_TMAC_TCR0_TBTT_STOP_CTRL); } +static int +mt7915_tm_config_rx_filter(struct mt7915_dev *dev, bool en) +{ + struct mt7915_tm_cmd req = { + .testmode_en = 1, + .param_idx = MCU_ATE_SET_RX_FILTER, + .param.filter.report_en = en, + .param.filter.band = 0, + }; + __le32 mask = RX_FILTER_NOT_OWN_BTIM | + RX_FILTER_NOT_OWN_UCAST | + RX_FILTER_RTS | RX_FILTER_CTS | + RX_FILTER_CTRL_RSV | + RX_FILTER_BC_MC_BSSID_A2 | + RX_FILTER_BC_MC_BSSID_A3 | + RX_FILTER_BC_MC_OMAC_A3 | + RX_FILTER_PROTOCOL_VERSION | + RX_FILTER_FCS_ERR; + + req.param.filter.mask = cpu_to_le32(mask); + + return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_ATE_CTRL, &req, + sizeof(req), false); +} + static void mt7915_tm_init(struct mt7915_dev *dev) { @@ -124,6 +149,7 @@ mt7915_tm_init(struct mt7915_dev *dev) mt7915_tm_mode_ctrl(dev, en); mt7915_tm_reg_backup_restore(dev, &dev->phy); mt7915_tm_set_trx(dev, &dev->phy, TM_MAC_TXRX, !en); + mt7915_tm_config_rx_filter(dev, en); } static void @@ -156,6 +182,20 @@ mt7915_tm_set_tx_frames(struct mt7915_dev *dev, bool en) info->control.vif = dev->phy.monitor_vif; } +static void +mt7915_tm_set_rx_frames(struct mt7915_dev *dev, bool en) +{ + if (en) { + mutex_unlock(&dev->mt76.mutex); + mt7915_set_channel(&dev->phy); + mutex_lock(&dev->mt76.mutex); + + mt7915_mcu_set_chan_info(&dev->phy, MCU_EXT_CMD_SET_RX_PATH); + } + + mt7915_tm_set_trx(dev, &dev->phy, TM_MAC_RX_RXV, en); +} + static int mt7915_tm_set_state(struct mt76_dev *mdev, enum mt76_testmode_state state) { @@ -169,12 +209,69 @@ mt7915_tm_set_state(struct mt76_dev *mdev, enum mt76_testmode_state state) mt7915_tm_set_tx_frames(dev, false); else if (state == MT76_TM_STATE_TX_FRAMES) mt7915_tm_set_tx_frames(dev, true); + else if (prev_state == MT76_TM_STATE_RX_FRAMES) + mt7915_tm_set_rx_frames(dev, false); + else if (state == MT76_TM_STATE_RX_FRAMES) + mt7915_tm_set_rx_frames(dev, true); else if (prev_state == MT76_TM_STATE_OFF || state == MT76_TM_STATE_OFF) mt7915_tm_init(dev); return 0; } +static int +mt7915_tm_dump_stats(struct mt76_dev *mdev, struct sk_buff *msg) +{ + struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); + void *rx, *rssi; + int i; + + rx = nla_nest_start(msg, MT76_TM_STATS_ATTR_LAST_RX); + if (!rx) + return -ENOMEM; + + if (nla_put_s32(msg, MT76_TM_RX_ATTR_FREQ_OFFSET, dev->test.last_freq_offset)) + return -ENOMEM; + + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_RCPI); + if (!rssi) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(dev->test.last_rcpi); i++) + if (nla_put_u8(msg, i, dev->test.last_rcpi[i])) + return -ENOMEM; + + nla_nest_end(msg, rssi); + + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_IB_RSSI); + if (!rssi) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(dev->test.last_ib_rssi); i++) + if (nla_put_s8(msg, i, dev->test.last_ib_rssi[i])) + return -ENOMEM; + + nla_nest_end(msg, rssi); + + rssi = nla_nest_start(msg, MT76_TM_RX_ATTR_WB_RSSI); + if (!rssi) + return -ENOMEM; + + for (i = 0; i < ARRAY_SIZE(dev->test.last_wb_rssi); i++) + if (nla_put_s8(msg, i, dev->test.last_wb_rssi[i])) + return -ENOMEM; + + nla_nest_end(msg, rssi); + + if (nla_put_s32(msg, MT76_TM_RX_ATTR_SNR, dev->test.last_snr)) + return -ENOMEM; + + nla_nest_end(msg, rx); + + return 0; +} + const struct mt76_testmode_ops mt7915_testmode_ops = { .set_state = mt7915_tm_set_state, + .dump_stats = mt7915_tm_dump_stats, }; diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/testmode.h b/drivers/net/wireless/mediatek/mt76/mt7915/testmode.h index 04f4a2c..b344a64 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/testmode.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/testmode.h @@ -11,6 +11,15 @@ struct mt7915_tm_trx { u8 rsv; }; +struct mt7915_tm_rx_filter { + u8 promiscuous; + u8 report_en; + u8 band; + u8 _rsv; + __le32 mask; + u8 _rsv1[4]; +}; + struct mt7915_tm_cmd { u8 testmode_en; u8 param_idx; @@ -18,6 +27,7 @@ struct mt7915_tm_cmd { union { __le32 data; struct mt7915_tm_trx trx; + struct mt7915_tm_rx_filter filter; u8 test[72]; } param; } __packed; @@ -31,4 +41,24 @@ enum { TM_MAC_RX_RXV, }; +#define RX_FILTER_STBC_BCN_BC_MC BIT(0) +#define RX_FILTER_FCS_ERR BIT(1) +#define RX_FILTER_PROTOCOL_VERSION BIT(2) +#define RX_FILTER_PROB_REQ BIT(3) +#define RX_FILTER_MCAST BIT(4) +#define RX_FILTER_BCAST BIT(5) +#define RX_FILTER_MCAST_TABLE BIT(6) +#define RX_FILTER_BC_MC_OMAC_A3 BIT(7) +#define RX_FILTER_BC_MC_BSSID_A3 BIT(8) +#define RX_FILTER_BC_MC_BSSID_A2 BIT(9) +#define RX_FILTER_BCN_BSSID BIT(10) +#define RX_FILTER_CTRL_RSV BIT(11) +#define RX_FILTER_CTS BIT(12) +#define RX_FILTER_RTS BIT(13) +#define RX_FILTER_DUPLICATE BIT(14) +#define RX_FILTER_NOT_OWN_BSSID BIT(15) +#define RX_FILTER_NOT_OWN_UCAST BIT(16) +#define RX_FILTER_NOT_OWN_BTIM BIT(17) +#define RX_FILTER_NDPA BIT(18) + #endif -- 2.17.1 _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek