All of lore.kernel.org
 help / color / mirror / Atom feed
From: Robert Marko <robert.marko@sartura.hr>
To: u-boot@lists.denx.de
Subject: [PATCH 2/6] IPQ40xx: Add SPI support
Date: Thu,  8 Oct 2020 22:05:10 +0200	[thread overview]
Message-ID: <20201008200514.2256778-3-robert.marko@sartura.hr> (raw)
In-Reply-To: <20201008200514.2256778-1-robert.marko@sartura.hr>

Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
 arch/arm/dts/qcom-ipq4019.dtsi          | 12 ++++++++++++
 arch/arm/mach-ipq40xx/clock-ipq4019.c   | 17 +++++++++++++++--
 arch/arm/mach-ipq40xx/pinctrl-ipq4019.c |  3 +++
 3 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi
index e0e4188e5d..936ef74f94 100644
--- a/arch/arm/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/dts/qcom-ipq4019.dtsi
@@ -22,6 +22,7 @@
 
 	aliases {
 		serial0 = &blsp1_uart1;
+		spi0 = &blsp1_spi1;
 	};
 
 	reserved-memory {
@@ -89,6 +90,17 @@
 			gpio-count = <100>;
 			gpio-bank-name="soc";
 			#gpio-cells = <2>;
+			u-boot,dm-pre-reloc;
+		};
+
+		blsp1_spi1: spi at 78b5000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x78b5000 0x600>;
+			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			u-boot,dm-pre-reloc;
 		};
 
 		usb3_ss_phy: ssphy at 9a000 {
diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c
index 83a688e625..d5b5f4cb79 100644
--- a/arch/arm/mach-ipq40xx/clock-ipq4019.c
+++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c
@@ -2,7 +2,7 @@
 /*
  * Clock drivers for Qualcomm IPQ40xx
  *
- * Copyright (c) 2019 Sartura Ltd.
+ * Copyright (c) 2020 Sartura Ltd.
  *
  * Author: Robert Marko <robert.marko@sartura.hr>
  *
@@ -24,7 +24,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
 	switch (clk->id) {
 	case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
 		/* This clock is already initialized by SBL1 */
-		return 0; 
+		return 0;
 		break;
 	default:
 		return 0;
@@ -47,8 +47,21 @@ static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
 	return msm_set_rate(clk, rate);
 }
 
+static int msm_enable(struct clk *clk)
+{
+	switch (clk->id) {
+	case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
+		/* This clock is already initialized by SBL1 */
+		return 0;
+		break;
+	default:
+		return 0;
+	}
+}
+
 static struct clk_ops msm_clk_ops = {
 	.set_rate = msm_clk_set_rate,
+	.enable = msm_enable,
 };
 
 static const struct udevice_id msm_clk_ids[] = {
diff --git a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c b/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c
index 06a57f2e5e..1f283516cb 100644
--- a/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c
+++ b/arch/arm/mach-ipq40xx/pinctrl-ipq4019.c
@@ -18,6 +18,9 @@ static const struct pinctrl_function msm_pinctrl_functions[] = {
 	{"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
 	{"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
 	{"blsp_uart1", 1},
+	{"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */
+	{"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */
+	{"blsp_spi1", 2},
 };
 
 static const char *ipq4019_get_function_name(struct udevice *dev,
-- 
2.28.0

  parent reply	other threads:[~2020-10-08 20:05 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08 20:05 [PATCH 0/6] IPQ40xx: Improve support Robert Marko
2020-10-08 20:05 ` [PATCH 1/6] spi: Add Qualcomm QUP SPI controller driver Robert Marko
2020-10-23  0:28   ` Tom Rini
2020-10-08 20:05 ` Robert Marko [this message]
2020-10-23  0:28   ` [PATCH 2/6] IPQ40xx: Add SPI support Tom Rini
2020-10-08 20:05 ` [PATCH 3/6] net: Add IPQ40xx MDIO driver Robert Marko
2020-10-23  0:28   ` Tom Rini
2020-10-08 20:05 ` [PATCH 4/6] IPQ40xx: Add support for MDIO Robert Marko
2020-10-23  0:29   ` Tom Rini
2020-10-08 20:05 ` [PATCH 5/6] rng: Add Qualcomm MSM PRNG driver Robert Marko
2020-10-23  0:29   ` Tom Rini
2020-12-14 17:22     ` Heinrich Schuchardt
2020-12-14 17:32       ` Robert Marko
2020-10-08 20:05 ` [PATCH 6/6] IPQ40xx: Add PRNG support Robert Marko
2020-10-23  0:29   ` Tom Rini

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201008200514.2256778-3-robert.marko@sartura.hr \
    --to=robert.marko@sartura.hr \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.