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From: Nicolin Chen <nicoleotsuka@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>
Cc: krzk@kernel.org, robh+dt@kernel.org, jonathanh@nvidia.com,
	linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups
Date: Fri, 9 Oct 2020 08:52:18 -0700	[thread overview]
Message-ID: <20201009155218.GA4469@Asurada-Nvidia> (raw)
In-Reply-To: <20201009122110.GD458338@ulmo>

On Fri, Oct 09, 2020 at 02:21:10PM +0200, Thierry Reding wrote:
> On Wed, Oct 07, 2020 at 05:37:45PM -0700, Nicolin Chen wrote:
> > According to Tegra X1 TRM, there are missing swgroups in the
> > tegra210_swgroups list. So this patch adds them in bindings.
> > 
> > Note that the TEGRA_SWGROUP_GPU (in list) should be actually
> > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM)
> > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So
> > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps
> > TEGRA_SWGROUP_GPU (in list) as it is.
> > 
> > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
> > ---
> >  include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> > 
> > diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h
> > index c226cba9e077..f9fcb18a6d9b 100644
> > --- a/include/dt-bindings/memory/tegra210-mc.h
> > +++ b/include/dt-bindings/memory/tegra210-mc.h
> > @@ -33,6 +33,16 @@
> >  #define TEGRA_SWGROUP_AXIAP	28
> >  #define TEGRA_SWGROUP_ETR	29
> >  #define TEGRA_SWGROUP_TSECB	30
> > +#define TEGRA_SWGROUP_NV	31
> > +#define TEGRA_SWGROUP_NV2	32
> > +#define TEGRA_SWGROUP_PPCS1	33
> > +#define TEGRA_SWGROUP_DC1	34
> > +#define TEGRA_SWGROUP_PPCS2	35
> > +#define TEGRA_SWGROUP_HC1	36
> > +#define TEGRA_SWGROUP_SE1	37
> > +#define TEGRA_SWGROUP_TSEC1	38
> > +#define TEGRA_SWGROUP_TSECB1	39
> > +#define TEGRA_SWGROUP_NVDEC1	40
> 
> I'm not sure this is right. The existing list is based on "Table 4:
> Client to Software Name Mapping" from page 28 of the Tegra X1 TRM, and
> none of these new swgroups seem to be present in that table.

I went through all the MC_SMMU_XX_ASID_0 registers. All of
them have their own ASID registers that I added in PATCH-5.

  reply	other threads:[~2020-10-09 15:59 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08  0:37 [PATCH 0/5] memory: tegra: Fix client list and add swgroups Nicolin Chen
2020-10-08  0:37 ` [PATCH 1/5] memory: tegra: Correct la.reg address of seswr Nicolin Chen
2020-10-09 12:11   ` Thierry Reding
2020-10-26 20:14   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 2/5] memory: tegra: Correct tegra210_mc_clients def values Nicolin Chen
2020-10-09 12:14   ` Thierry Reding
2020-10-26 20:15   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 3/5] memory: tegra: Sort tegra210_swgroups by reg address Nicolin Chen
2020-10-08 10:32   ` Krzysztof Kozlowski
2020-10-08 20:26     ` Nicolin Chen
2020-10-12 16:43       ` Krzysztof Kozlowski
2020-10-12 18:57         ` Nicolin Chen
2020-10-09 12:15   ` Thierry Reding
2020-10-26 20:17   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 4/5] dt-bindings: memory: tegra: Add missing swgroups Nicolin Chen
2020-10-09 12:21   ` Thierry Reding
2020-10-09 15:52     ` Nicolin Chen [this message]
2020-10-26 20:17       ` Krzysztof Kozlowski
2020-10-27 12:55         ` Thierry Reding
2020-10-27 23:31           ` Nicolin Chen
2020-10-27 19:54   ` Krzysztof Kozlowski
2020-10-08  0:37 ` [PATCH 5/5] memory: tegra: Complete tegra210_swgroups Nicolin Chen
2020-10-27 13:01   ` Thierry Reding
2020-10-27 23:37     ` Nicolin Chen
2020-11-20 16:27   ` Thierry Reding
2020-11-22 11:07   ` Krzysztof Kozlowski
2020-10-08 10:29 ` [PATCH 0/5] memory: tegra: Fix client list and add swgroups Krzysztof Kozlowski
2020-10-08 20:27   ` Nicolin Chen

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