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[209.6.122.159]) by smtp.gmail.com with ESMTPSA id o4sm7532382qkk.75.2020.10.09.18.58.56 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Oct 2020 18:58:57 -0700 (PDT) Date: Fri, 9 Oct 2020 21:58:55 -0400 From: Masayoshi Mizuma To: Sumit Garg Cc: maz@kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, daniel.thompson@linaro.org, jason@lakedaemon.net, kgdb-bugreport@lists.sourceforge.net, dianders@chromium.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jason.wessel@windriver.com, tglx@linutronix.de, julien.thierry.kdev@gmail.com Subject: Re: [PATCH v4 1/5] arm64: Add framework to turn IPI as NMI Message-ID: <20201010015855.vksetnj4luft5enc@gabell> References: <1599830924-13990-1-git-send-email-sumit.garg@linaro.org> <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sumit, On Fri, Sep 11, 2020 at 06:58:40PM +0530, Sumit Garg wrote: > Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a > particular platform doesn't support pseudo NMIs, then request IPI as a > regular IRQ. > > The main motivation for this feature is to have an IPI that can be > leveraged to invoke NMI functions on other CPUs. And current prospective > users are NMI backtrace and KGDB CPUs round-up whose support is added > via future patches. > > Signed-off-by: Sumit Garg > --- > arch/arm64/include/asm/nmi.h | 16 +++++++++ > arch/arm64/kernel/Makefile | 2 +- > arch/arm64/kernel/ipi_nmi.c | 80 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 97 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/include/asm/nmi.h > create mode 100644 arch/arm64/kernel/ipi_nmi.c > > diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h > new file mode 100644 > index 0000000..3433c55 > --- /dev/null > +++ b/arch/arm64/include/asm/nmi.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_NMI_H > +#define __ASM_NMI_H > + > +#ifndef __ASSEMBLER__ > + > +#include > + > +extern void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask); > + > +void set_smp_ipi_nmi(int ipi); > +void ipi_nmi_setup(int cpu); > +void ipi_nmi_teardown(int cpu); > + > +#endif /* !__ASSEMBLER__ */ > +#endif > diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile > index a561cbb..022c26b 100644 > --- a/arch/arm64/kernel/Makefile > +++ b/arch/arm64/kernel/Makefile > @@ -19,7 +19,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ > return_address.o cpuinfo.o cpu_errata.o \ > cpufeature.o alternative.o cacheinfo.o \ > smp.o smp_spin_table.o topology.o smccc-call.o \ > - syscall.o > + syscall.o ipi_nmi.o > > targets += efi-entry.o > > diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c > new file mode 100644 > index 0000000..355ef92 > --- /dev/null > +++ b/arch/arm64/kernel/ipi_nmi.c > @@ -0,0 +1,80 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * NMI support for IPIs > + * > + * Copyright (C) 2020 Linaro Limited > + * Author: Sumit Garg > + */ > + > +#include > +#include > +#include > + > +#include > + > +static struct irq_desc *ipi_desc __read_mostly; > +static int ipi_id __read_mostly; > +static bool is_nmi __read_mostly; > + > +void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask) > +{ > + if (WARN_ON_ONCE(!ipi_desc)) > + return; > + > + __ipi_send_mask(ipi_desc, mask); > +} > + > +static irqreturn_t ipi_nmi_handler(int irq, void *data) > +{ > + /* nop, NMI handlers for special features can be added here. */ > + > + return IRQ_HANDLED; > +} > + > +void ipi_nmi_setup(int cpu) > +{ > + if (!ipi_desc) > + return; ipi_nmi_setup() may be called twice for CPU0: set_smp_ipi_range => set_smp_ipi_nmi => ipi_nmi_setup => ipi_setup => ipi_nmi_setup Actually, I got the following error message via the second ipi_nmi_setup(): GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation GICv3: Cannot set NMI property of enabled IRQ 8 genirq: Failed to setup NMI delivery: irq 8 Why don't we have a check to prevent that? Like as: if (cpumask_test_cpu(cpu, ipi_desc->percpu_enabled)) return; > + > + if (is_nmi) { > + if (!prepare_percpu_nmi(ipi_id)) > + enable_percpu_nmi(ipi_id, 0); It would be better to use IRQ_TYPE_NONE instead of 0. enable_percpu_nmi(ipi_id, IRQ_TYPE_NONE); > + } else { > + enable_percpu_irq(ipi_id, 0); Same as here: enable_percpu_irq(ipi_id, IRQ_TYPE_NONE); Thanks, Masa > + } > +} > + > +void ipi_nmi_teardown(int cpu) > +{ > + if (!ipi_desc) > + return; > + > + if (is_nmi) { > + disable_percpu_nmi(ipi_id); > + teardown_percpu_nmi(ipi_id); > + } else { > + disable_percpu_irq(ipi_id); > + } > +} > + > +void __init set_smp_ipi_nmi(int ipi) > +{ > + int err; > + > + err = request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number); > + if (err) { > + err = request_percpu_irq(ipi, ipi_nmi_handler, "IPI", > + &cpu_number); > + WARN_ON(err); > + is_nmi = false; > + } else { > + is_nmi = true; > + } > + > + ipi_desc = irq_to_desc(ipi); > + irq_set_status_flags(ipi, IRQ_HIDDEN); > + ipi_id = ipi; > + > + /* Setup the boot CPU immediately */ > + ipi_nmi_setup(smp_processor_id()); > +} > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AF4DC433DF for ; Sat, 10 Oct 2020 02:00:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B68E2225D for ; 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Fri, 09 Oct 2020 18:58:57 -0700 (PDT) Received: from gabell (209-6-122-159.s2973.c3-0.arl-cbr1.sbo-arl.ma.cable.rcncustomer.com. [209.6.122.159]) by smtp.gmail.com with ESMTPSA id o4sm7532382qkk.75.2020.10.09.18.58.56 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Oct 2020 18:58:57 -0700 (PDT) Date: Fri, 9 Oct 2020 21:58:55 -0400 From: Masayoshi Mizuma To: Sumit Garg Subject: Re: [PATCH v4 1/5] arm64: Add framework to turn IPI as NMI Message-ID: <20201010015855.vksetnj4luft5enc@gabell> References: <1599830924-13990-1-git-send-email-sumit.garg@linaro.org> <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201009_215902_360172_2B9A9A4C X-CRM114-Status: GOOD ( 29.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, jason@lakedaemon.net, maz@kernel.org, jason.wessel@windriver.com, dianders@chromium.org, linux-kernel@vger.kernel.org, julien.thierry.kdev@gmail.com, catalin.marinas@arm.com, kgdb-bugreport@lists.sourceforge.net, tglx@linutronix.de, will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Sumit, On Fri, Sep 11, 2020 at 06:58:40PM +0530, Sumit Garg wrote: > Introduce framework to turn an IPI as NMI using pseudo NMIs. In case a > particular platform doesn't support pseudo NMIs, then request IPI as a > regular IRQ. > > The main motivation for this feature is to have an IPI that can be > leveraged to invoke NMI functions on other CPUs. And current prospective > users are NMI backtrace and KGDB CPUs round-up whose support is added > via future patches. > > Signed-off-by: Sumit Garg > --- > arch/arm64/include/asm/nmi.h | 16 +++++++++ > arch/arm64/kernel/Makefile | 2 +- > arch/arm64/kernel/ipi_nmi.c | 80 ++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 97 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/include/asm/nmi.h > create mode 100644 arch/arm64/kernel/ipi_nmi.c > > diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h > new file mode 100644 > index 0000000..3433c55 > --- /dev/null > +++ b/arch/arm64/include/asm/nmi.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __ASM_NMI_H > +#define __ASM_NMI_H > + > +#ifndef __ASSEMBLER__ > + > +#include > + > +extern void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask); > + > +void set_smp_ipi_nmi(int ipi); > +void ipi_nmi_setup(int cpu); > +void ipi_nmi_teardown(int cpu); > + > +#endif /* !__ASSEMBLER__ */ > +#endif > diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile > index a561cbb..022c26b 100644 > --- a/arch/arm64/kernel/Makefile > +++ b/arch/arm64/kernel/Makefile > @@ -19,7 +19,7 @@ obj-y := debug-monitors.o entry.o irq.o fpsimd.o \ > return_address.o cpuinfo.o cpu_errata.o \ > cpufeature.o alternative.o cacheinfo.o \ > smp.o smp_spin_table.o topology.o smccc-call.o \ > - syscall.o > + syscall.o ipi_nmi.o > > targets += efi-entry.o > > diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c > new file mode 100644 > index 0000000..355ef92 > --- /dev/null > +++ b/arch/arm64/kernel/ipi_nmi.c > @@ -0,0 +1,80 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * NMI support for IPIs > + * > + * Copyright (C) 2020 Linaro Limited > + * Author: Sumit Garg > + */ > + > +#include > +#include > +#include > + > +#include > + > +static struct irq_desc *ipi_desc __read_mostly; > +static int ipi_id __read_mostly; > +static bool is_nmi __read_mostly; > + > +void arch_send_call_nmi_func_ipi_mask(cpumask_t *mask) > +{ > + if (WARN_ON_ONCE(!ipi_desc)) > + return; > + > + __ipi_send_mask(ipi_desc, mask); > +} > + > +static irqreturn_t ipi_nmi_handler(int irq, void *data) > +{ > + /* nop, NMI handlers for special features can be added here. */ > + > + return IRQ_HANDLED; > +} > + > +void ipi_nmi_setup(int cpu) > +{ > + if (!ipi_desc) > + return; ipi_nmi_setup() may be called twice for CPU0: set_smp_ipi_range => set_smp_ipi_nmi => ipi_nmi_setup => ipi_setup => ipi_nmi_setup Actually, I got the following error message via the second ipi_nmi_setup(): GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation GICv3: Cannot set NMI property of enabled IRQ 8 genirq: Failed to setup NMI delivery: irq 8 Why don't we have a check to prevent that? Like as: if (cpumask_test_cpu(cpu, ipi_desc->percpu_enabled)) return; > + > + if (is_nmi) { > + if (!prepare_percpu_nmi(ipi_id)) > + enable_percpu_nmi(ipi_id, 0); It would be better to use IRQ_TYPE_NONE instead of 0. enable_percpu_nmi(ipi_id, IRQ_TYPE_NONE); > + } else { > + enable_percpu_irq(ipi_id, 0); Same as here: enable_percpu_irq(ipi_id, IRQ_TYPE_NONE); Thanks, Masa > + } > +} > + > +void ipi_nmi_teardown(int cpu) > +{ > + if (!ipi_desc) > + return; > + > + if (is_nmi) { > + disable_percpu_nmi(ipi_id); > + teardown_percpu_nmi(ipi_id); > + } else { > + disable_percpu_irq(ipi_id); > + } > +} > + > +void __init set_smp_ipi_nmi(int ipi) > +{ > + int err; > + > + err = request_percpu_nmi(ipi, ipi_nmi_handler, "IPI", &cpu_number); > + if (err) { > + err = request_percpu_irq(ipi, ipi_nmi_handler, "IPI", > + &cpu_number); > + WARN_ON(err); > + is_nmi = false; > + } else { > + is_nmi = true; > + } > + > + ipi_desc = irq_to_desc(ipi); > + irq_set_status_flags(ipi, IRQ_HIDDEN); > + ipi_id = ipi; > + > + /* Setup the boot CPU immediately */ > + ipi_nmi_setup(smp_processor_id()); > +} > -- > 2.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel