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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id x1sm20948151wrl.41.2020.10.13.06.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Oct 2020 06:25:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Victor Kamensky Subject: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property Date: Tue, 13 Oct 2020 15:25:32 +0200 Message-Id: <20201013132535.3599453-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Khem Raj , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Richard Purdie , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Yocto developers have expressed interest in running MIPS32=0D CPU with custom number of TLB:=0D https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html=0D =0D Help them by making the number of TLB entries a CPU property,=0D keeping our set of CPU definitions in sync with real hardware.=0D =0D Please test/review,=0D =0D Phil.=0D =0D Philippe Mathieu-Daud=C3=A9 (3):=0D target/mips: Make cpu_mips_realize_env() propagate Error=0D target/mips: Store number of TLB entries in CPUMIPSState=0D target/mips: Make the number of TLB entries a CPU property=0D =0D target/mips/cpu.h | 1 +=0D target/mips/internal.h | 10 +++++++++-=0D target/mips/cpu.c | 12 ++++++++++--=0D target/mips/translate.c | 16 ++++++++++++++--=0D target/mips/translate_init.c.inc | 2 +-=0D 5 files changed, 35 insertions(+), 6 deletions(-)=0D =0D -- =0D 2.26.2=0D =0D