Re: [Intel-gfx] [PATCH] drm/i915/gt: Fixup tgl mocs for PTE tracking

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Oct 14, 2020 at 11:31:52AM +0100, Chris Wilson wrote:
> Forcing mocs:1 [used for our winsys follows-pte mode] to be cached
> caused display glitches. Though it is documented as deprecated (and so
> likely behaves as uncached) use the follow-pte bit and force it out of
> L3 cache.

The MOCS PTE -> L3=UC thing is something we should perhaps roll out to
every platform. IIRC at least the earlier platforms were documented to
evict from L3 into LLC/eLLC even when LLC/eLLC is marked UC. Though
IIRC we don't have that L3 control in the kernel on all the platforms,
so to be totally correct we'd need to fix userspace as well.

For SKL+ I see this in the spec:
"Index 'd63 is used for two purposes. 
 It is used by the L3 for all its evictions. The programming of the
 index 'd63 is expected to allow LLC cacheability to enable coherent
 flows to be maintained.
 It is also used by hardware to force L3 uncacheable cycles. The
 prgramming of the index #63 is expected to make the surface L3
 uncacheable."

Though we're not even programming that for pre-icl, so not sure
if the spec is just confused or what.

Anyways, makes sense to me:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Fixes: 4d8a5cfe3b13 ("drm/i915/gt: Initialize reserved and unspecified MOCS indices")
> Testcase: igt/kms_frontbuffer_tracking
> Testcase: igt/kms_big_fb
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 39179a3eee98..093b32db3428 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -243,8 +243,9 @@ static const struct drm_i915_mocs_entry tgl_mocs_table[] = {
>  	 * only, __init_mocs_table() take care to program unused index with
>  	 * this entry.
>  	 */
> -	MOCS_ENTRY(1, LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
> -		   L3_3_WB),
> +	MOCS_ENTRY(I915_MOCS_PTE,
> +		   LE_0_PAGETABLE | LE_TC_0_PAGETABLE,
> +		   L3_1_UC),
>  	GEN11_MOCS_ENTRIES,
>  
>  	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
> -- 
> 2.20.1

-- 
Ville Syrjälä
Intel
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