From: Leo Yan <leo.yan@linaro.org>
To: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Kan Liang <kan.liang@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>, Ian Rogers <irogers@google.com>,
Joe Mario <jmario@redhat.com>, David Ahern <dsahern@gmail.com>,
Don Zickus <dzickus@redhat.com>, Al Grant <Al.Grant@arm.com>,
James Clark <james.clark@arm.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 0/8] perf c2c: Sort cacheline with LLC load
Date: Thu, 15 Oct 2020 23:14:27 +0800 [thread overview]
Message-ID: <20201015151427.GC462@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <20201015150506.GB2959014@kernel.org>
On Thu, Oct 15, 2020 at 12:05:06PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Thu, Oct 15, 2020 at 03:50:33PM +0100, Leo Yan escreveu:
> > If the memory event doesn't contain HITM tag (like Arm SPE), it cannot
> > rely on HITM display to report cache false sharing. Alternatively, we
> > can use the LLC access and multi-threads info to locate the potential
> > false sharing's data address, and if we connect with source code and
> > analyze the multi-threads' execution timing, if can conclude load and
> > store the same cache line at the meantime, thus this can be helpful for
> > resolve the cache false sharing issue.
> >
> > This patch set is to enable the display with sorting on LLC load
> > accesses; it adds dimensions for total LLC hit and LLC load accesses,
> > and these dimensions are used for shared cache line table and pareto.
> >
> > This patch set is dependend on the patch set "perf c2c: Refine the
> > organization of metrics" [1].
> >
> > [1] https://lore.kernel.org/patchwork/cover/1321499/
>
> Ok, that one is applied and will appear publicly as soon as it goes thru
> my usual set of build tests.
Thank you, Arnaldo!
Leo
next prev parent reply other threads:[~2020-10-15 15:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-15 14:50 [PATCH v1 0/8] perf c2c: Sort cacheline with LLC load Leo Yan
2020-10-15 14:50 ` [PATCH v1 1/8] perf mem: Add structure field c2c_stats::tot_llchit Leo Yan
2020-10-15 14:50 ` [PATCH v1 2/8] perf c2c: Add dimensions for total LLC hit Leo Yan
2020-10-15 14:50 ` [PATCH v1 3/8] perf c2c: Add dimensions for LLC load hit Leo Yan
2020-10-15 14:50 ` [PATCH v1 4/8] perf c2c: Change to general naming for macros Leo Yan
2020-10-15 14:50 ` [PATCH v1 5/8] perf c2c: Rename for shared cache line stats Leo Yan
2020-10-15 14:50 ` [PATCH v1 6/8] perf c2c: Refactor hist entry validation Leo Yan
2020-10-15 14:50 ` [PATCH v1 7/8] perf c2c: Add option '-d llc' for sorting with LLC load Leo Yan
2020-10-20 7:25 ` Jiri Olsa
2020-10-20 8:08 ` Leo Yan
2020-10-22 8:43 ` Jiri Olsa
2020-10-20 7:26 ` Jiri Olsa
2020-10-20 8:14 ` Leo Yan
2020-10-15 14:50 ` [PATCH v1 8/8] perf c2c: Update documentation for display option 'llc' Leo Yan
2020-10-20 7:26 ` Jiri Olsa
2020-10-15 15:05 ` [PATCH v1 0/8] perf c2c: Sort cacheline with LLC load Arnaldo Carvalho de Melo
2020-10-15 15:14 ` Leo Yan [this message]
2020-10-20 8:13 ` Namhyung Kim
2020-10-20 8:18 ` Leo Yan
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