Hi Ankit, [FYI, it's a private test report for your RFC patch.] [auto build test WARNING on drm-tip/drm-tip] [cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master drm/drm-next v5.9 next-20201015] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Ankit-Nautiyal/Add-support-for-DP-HDMI2-1-PCON/20201015-190247 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-a004-20201014 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce (this is a W=1 build): # https://github.com/0day-ci/linux/commit/7e4e2d9558b0439382a9b2a477d7ab9d25e09394 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Ankit-Nautiyal/Add-support-for-DP-HDMI2-1-PCON/20201015-190247 git checkout 7e4e2d9558b0439382a9b2a477d7ab9d25e09394 # save the attached .config to linux build tree make W=1 ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All warnings (new ones prefixed by >>): >> drivers/gpu/drm/i915/display/intel_dp.c:3885:6: warning: no previous prototype for 'intel_dp_get_pcon_dsc_cap' [-Wmissing-prototypes] 3885 | void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) | ^~~~~~~~~~~~~~~~~~~~~~~~~ vim +/intel_dp_get_pcon_dsc_cap +3885 drivers/gpu/drm/i915/display/intel_dp.c 3884 > 3885 void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 3886 { 3887 u8 buf; 3888 u8 rc_buf_blk_size; 3889 u8 max_slices = 0; 3890 3891 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3892 struct intel_dp_pcon_dsc *pcon_dsc = &intel_dp->pcon_dsc; 3893 3894 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENCODER, &buf) < 0) { 3895 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_ENCODER\n"); 3896 return; 3897 } 3898 pcon_dsc->enc_support = buf & DP_PCON_DSC_ENCODER_SUPPORTED; 3899 pcon_dsc->pps_override_support = buf & DP_PCON_DSC_PPS_ENC_OVERRIDE; 3900 3901 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_VERSION, &buf) < 0) { 3902 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_VERSION\n"); 3903 return; 3904 } 3905 pcon_dsc->version_major = (buf & DP_PCON_DSC_MAJOR_MASK) >> 3906 DP_PCON_DSC_MAJOR_SHIFT; 3907 pcon_dsc->version_minor = (buf & DP_PCON_DSC_MINOR_MASK) >> 3908 DP_PCON_DSC_MINOR_SHIFT; 3909 3910 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_BLK_INFO, &buf) < 0) { 3911 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_RC_BUF_BLK_INFO\n"); 3912 return; 3913 } 3914 3915 switch (buf & DP_PCON_DSC_RC_BUF_BLK_SIZE) { 3916 case DP_PCON_DSC_RC_BUF_BLK_1KB : 3917 rc_buf_blk_size = 1; 3918 break; 3919 case DP_PCON_DSC_RC_BUF_BLK_4KB : 3920 rc_buf_blk_size = 4; 3921 break; 3922 case DP_PCON_DSC_RC_BUF_BLK_16KB : 3923 rc_buf_blk_size = 16; 3924 break; 3925 case DP_PCON_DSC_RC_BUF_BLK_64KB : 3926 rc_buf_blk_size = 64; 3927 break; 3928 default : 3929 rc_buf_blk_size = 0; 3930 } 3931 3932 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_RC_BUF_SIZE, &buf) < 0) { 3933 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_RC_BUF_SIZE\n"); 3934 return; 3935 } 3936 /* storing rc_buf_size in bytes */ 3937 pcon_dsc->rc_buf_size = (buf + 1) * rc_buf_blk_size * 1024; 3938 3939 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_2, &buf) < 0) { 3940 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_SLICE_CAP_2\n"); 3941 return; 3942 } 3943 if (buf & DP_PCON_DSC_24_PER_DSC_ENC) 3944 max_slices = 24; 3945 else if (buf & DP_PCON_DSC_20_PER_DSC_ENC) 3946 max_slices = 20; 3947 else if (buf & DP_PCON_DSC_16_PER_DSC_ENC) 3948 max_slices = 16; 3949 3950 if (max_slices == 0) { 3951 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_SLICE_CAP_1, 3952 &buf) < 0) { 3953 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_SLICE_CAP_2\n"); 3954 return; 3955 } 3956 3957 if (buf & DP_PCON_DSC_12_PER_DSC_ENC) 3958 max_slices = 12; 3959 else if (buf & DP_PCON_DSC_10_PER_DSC_ENC) 3960 max_slices = 10; 3961 else if (buf & DP_PCON_DSC_8_PER_DSC_ENC) 3962 max_slices = 8; 3963 else if (buf & DP_PCON_DSC_6_PER_DSC_ENC) 3964 max_slices = 6; 3965 else if (buf & DP_PCON_DSC_4_PER_DSC_ENC) 3966 max_slices = 4; 3967 else if (buf & DP_PCON_DSC_2_PER_DSC_ENC) 3968 max_slices = 2; 3969 else if (buf & DP_PCON_DSC_1_PER_DSC_ENC) 3970 max_slices = 1; 3971 } 3972 3973 pcon_dsc->max_slices = max_slices; 3974 3975 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BUF_BIT_DEPTH, &buf) < 0) { 3976 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_BUF_BIT_DEPTH\n"); 3977 return; 3978 } 3979 switch (buf & DP_PCON_DSC_BIT_DEPTH_MASK) { 3980 case DP_PCON_DSC_DEPTH_8_BITS : 3981 pcon_dsc->line_buf_bit_depth = 8; 3982 break; 3983 case DP_PCON_DSC_DEPTH_9_BITS : 3984 pcon_dsc->line_buf_bit_depth = 9; 3985 break; 3986 case DP_PCON_DSC_DEPTH_10_BITS : 3987 pcon_dsc->line_buf_bit_depth = 10; 3988 break; 3989 case DP_PCON_DSC_DEPTH_11_BITS : 3990 pcon_dsc->line_buf_bit_depth = 11; 3991 break; 3992 case DP_PCON_DSC_DEPTH_12_BITS : 3993 pcon_dsc->line_buf_bit_depth = 12; 3994 break; 3995 case DP_PCON_DSC_DEPTH_13_BITS : 3996 pcon_dsc->line_buf_bit_depth = 13; 3997 break; 3998 case DP_PCON_DSC_DEPTH_14_BITS : 3999 pcon_dsc->line_buf_bit_depth = 14; 4000 break; 4001 case DP_PCON_DSC_DEPTH_15_BITS : 4002 pcon_dsc->line_buf_bit_depth = 15; 4003 break; 4004 case DP_PCON_DSC_DEPTH_16_BITS : 4005 pcon_dsc->line_buf_bit_depth = 16; 4006 break; 4007 default : 4008 pcon_dsc->line_buf_bit_depth = 0; 4009 } 4010 4011 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BLOCK_PREDICTION, &buf) < 0) { 4012 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_BLOCK_PREDICTION\n"); 4013 return; 4014 } 4015 if (buf && DP_PCON_DSC_BLOCK_PRED_SUPPORT) 4016 pcon_dsc->blk_prediction_support = true; 4017 4018 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENC_COLOR_FMT_CAP, &buf) < 0) { 4019 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_ENC_COLOR_FMT_CAP\n"); 4020 return; 4021 } 4022 pcon_dsc->color_fmt_mask = buf; 4023 4024 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_ENC_COLOR_DEPTH_CAP, &buf) < 0) { 4025 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_ENC_COLOR_DEPTH_CAP\n"); 4026 return; 4027 } 4028 pcon_dsc->color_depth_mask = buf; 4029 4030 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_MAX_SLICE_WIDTH, &buf) < 0) { 4031 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_MAX_SLICE_WIDTH\n"); 4032 return; 4033 } 4034 pcon_dsc->max_slice_width = buf;; 4035 4036 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_DSC_BPP_INCR, &buf) < 0) { 4037 drm_err(&i915->drm, "Failed to read DP_PCON_DSC_BPP_INCR\n"); 4038 return; 4039 } 4040 switch(buf & DP_PCON_DSC_BPP_INCR_MASK) { 4041 case DP_PCON_DSC_ONE_16TH_BPP: 4042 pcon_dsc->bpp_precision_incr = 16; 4043 break; 4044 case DP_PCON_DSC_ONE_8TH_BPP: 4045 pcon_dsc->bpp_precision_incr = 8; 4046 break; 4047 case DP_PCON_DSC_ONE_4TH_BPP: 4048 pcon_dsc->bpp_precision_incr = 4; 4049 break; 4050 case DP_PCON_DSC_ONE_HALF_BPP: 4051 pcon_dsc->bpp_precision_incr = 2; 4052 break; 4053 case DP_PCON_DSC_ONE_BPP: 4054 pcon_dsc->bpp_precision_incr = 1; 4055 break; 4056 default : 4057 pcon_dsc->bpp_precision_incr = 0; 4058 } 4059 } 4060 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org