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[111.243.184.51]) by smtp.gmail.com with ESMTPSA id gd14sm260489pjb.31.2020.10.19.20.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 20:37:49 -0700 (PDT) From: Green Wan To: Subject: [PATCH v8 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection Date: Tue, 20 Oct 2020 11:37:31 +0800 Message-Id: <20201020033732.12921-2-green.wan@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201020033732.12921-1-green.wan@sifive.com> References: <20201020033732.12921-1-green.wan@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=green.wan@sifive.com; helo=mail-pl1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, bmeng.cn@gmail.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, green.wan@sifive.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" - Add write operation to update fuse data bit when PWE bit is on. - Add array, fuse_wo, to store the 'written' status for all bits of OTP to block the write operation. Signed-off-by: Green Wan Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/misc/sifive_u_otp.c | 30 +++++++++++++++++++++++++++++- include/hw/misc/sifive_u_otp.h | 3 +++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index c2f3c8e129..b9238d64cb 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -25,6 +25,14 @@ #include "qemu/module.h" #include "hw/misc/sifive_u_otp.h" +#define WRITTEN_BIT_ON 0x1 + +#define SET_FUSEARRAY_BIT(map, i, off, bit) \ + map[i] = bit ? (map[i] | bit << off) : (map[i] & ~(0x1 << off)) + +#define GET_FUSEARRAY_BIT(map, i, off) \ + ((map[i] >> off) & 0x1) + static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) { SiFiveUOTPState *s = opaque; @@ -123,7 +131,24 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr, s->ptrim = val32; break; case SIFIVE_U_OTP_PWE: - s->pwe = val32; + s->pwe = val32 & SIFIVE_U_OTP_PWE_EN; + + /* PWE is enabled. Ignore PAS=1 (no redundancy cell) */ + if (s->pwe && !s->pas) { + if (GET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio)) { + qemu_log_mask(LOG_GUEST_ERROR, + "write once error: idx<%u>, bit<%u>\n", + s->pa, s->paio); + break; + } + + /* write bit data */ + SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin); + + /* update written bit */ + SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON); + } + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx @@ -165,6 +190,9 @@ static void sifive_u_otp_reset(DeviceState *dev) /* Make a valid content of serial number */ s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); + + /* Initialize write-once map */ + memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo)); } static void sifive_u_otp_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h index 82c9176c8f..ebffbc1fa5 100644 --- a/include/hw/misc/sifive_u_otp.h +++ b/include/hw/misc/sifive_u_otp.h @@ -36,6 +36,8 @@ #define SIFIVE_U_OTP_PTRIM 0x34 #define SIFIVE_U_OTP_PWE 0x38 +#define SIFIVE_U_OTP_PWE_EN (1 << 0) + #define SIFIVE_U_OTP_PCE_EN (1 << 0) #define SIFIVE_U_OTP_PDSTB_EN (1 << 0) @@ -75,6 +77,7 @@ struct SiFiveUOTPState { uint32_t ptrim; uint32_t pwe; uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES]; /* config */ uint32_t serial; }; -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kUiTC-00013F-6O for mharc-qemu-riscv@gnu.org; Mon, 19 Oct 2020 23:37:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kUiTB-000120-7F for qemu-riscv@nongnu.org; Mon, 19 Oct 2020 23:37:53 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:52420) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kUiT9-0005rd-3t for qemu-riscv@nongnu.org; Mon, 19 Oct 2020 23:37:52 -0400 Received: by mail-pj1-x1032.google.com with SMTP id gm14so196531pjb.2 for ; Mon, 19 Oct 2020 20:37:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZP0P1YsDvhVLDnigTxcAr9bHNAEed+EOs9ZCHTy6oW4=; b=UNeCv3KTmdKm1whUsrV5w9u6rgdnSKwi6+EwtUyPfoh8j47ILXt3HMqUeXTxXHv0Zd jaTHnczn9oOEmCNzhkuf5jaZwkjeDPmoBJJkyMDW5eVlHikjEEqcw3+IIaQBkmMHvxnZ e49M8jGb/gp2FBQVhDj/T9MweqB5DCod17s4Lhy94DVhLYGJbV2vih84bVT4DCc4ktbX QI2XLlO0FeoC/a/INw6gkqZjEjbJSjCygPhLmg6JTAgxIB56wA/mi6nSyXZbmwiOfdpS jGehgujXKk8BW9QgAKacXn/p83AK8tEBWu8RwOLPEV08m8iN8uAcWxMCWUW5uXErU8zP PiFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZP0P1YsDvhVLDnigTxcAr9bHNAEed+EOs9ZCHTy6oW4=; b=SHm/8n2dnL+dba2c+j7x5FDHC1N4z+bHOxOsNO5afHg6hrL/yJIWCfMeaHHuQxs/IX R9KJhFkxkM8xckzyOXNBJMwpDEa+d2bPu6L66ToqDJ0ugIdXJhsWAbtqheJd0jyZwkyt kLjDlve1EkMjaMwpeCLuRGJnY/TFhF61ZzewfZY9I342q+6K7LQnJvsY+uG9+fKsLjIu 6qdWUY4Tg19kt9+QNvz8Ec8kKUPTK6Lr8QVlG05LgAA/nYkx7CJaRlE7J85J+Bt9HpEf FkXk6RvfZCija2AyktkKKqlozVXXGj9ayJadOqwTs8RZ2x0FXn8UG4WP7417KDBrPckm AxHg== X-Gm-Message-State: AOAM532YGoMb2o2u3WHOIL0FV1GIc8dzAh458GATIlT7grtipxLsXK++ ntDtpnSTNR74dfXZ4C6JxuGjTQ== X-Google-Smtp-Source: ABdhPJzE+bXKiNVWDVnI6kAWlKNSVHF3eJmNoGR4UZypKQ4GUThjQWsZarP6CloXbnJQw24LrifxIA== X-Received: by 2002:a17:902:a40a:b029:d5:a7d7:4ea0 with SMTP id p10-20020a170902a40ab02900d5a7d74ea0mr975262plq.9.1603165069809; Mon, 19 Oct 2020 20:37:49 -0700 (PDT) Received: from localhost.localdomain (111-243-184-51.dynamic-ip.hinet.net. [111.243.184.51]) by smtp.gmail.com with ESMTPSA id gd14sm260489pjb.31.2020.10.19.20.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 20:37:49 -0700 (PDT) From: Green Wan To: Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, bmeng.cn@gmail.com, alistair23@gmail.com, green.wan@sifive.com Subject: [PATCH v8 1/2] hw/misc/sifive_u_otp: Add write function and write-once protection Date: Tue, 20 Oct 2020 11:37:31 +0800 Message-Id: <20201020033732.12921-2-green.wan@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201020033732.12921-1-green.wan@sifive.com> References: <20201020033732.12921-1-green.wan@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=green.wan@sifive.com; helo=mail-pj1-x1032.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Oct 2020 03:37:53 -0000 - Add write operation to update fuse data bit when PWE bit is on. - Add array, fuse_wo, to store the 'written' status for all bits of OTP to block the write operation. Signed-off-by: Green Wan Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/misc/sifive_u_otp.c | 30 +++++++++++++++++++++++++++++- include/hw/misc/sifive_u_otp.h | 3 +++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index c2f3c8e129..b9238d64cb 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -25,6 +25,14 @@ #include "qemu/module.h" #include "hw/misc/sifive_u_otp.h" +#define WRITTEN_BIT_ON 0x1 + +#define SET_FUSEARRAY_BIT(map, i, off, bit) \ + map[i] = bit ? (map[i] | bit << off) : (map[i] & ~(0x1 << off)) + +#define GET_FUSEARRAY_BIT(map, i, off) \ + ((map[i] >> off) & 0x1) + static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) { SiFiveUOTPState *s = opaque; @@ -123,7 +131,24 @@ static void sifive_u_otp_write(void *opaque, hwaddr addr, s->ptrim = val32; break; case SIFIVE_U_OTP_PWE: - s->pwe = val32; + s->pwe = val32 & SIFIVE_U_OTP_PWE_EN; + + /* PWE is enabled. Ignore PAS=1 (no redundancy cell) */ + if (s->pwe && !s->pas) { + if (GET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio)) { + qemu_log_mask(LOG_GUEST_ERROR, + "write once error: idx<%u>, bit<%u>\n", + s->pa, s->paio); + break; + } + + /* write bit data */ + SET_FUSEARRAY_BIT(s->fuse, s->pa, s->paio, s->pdin); + + /* update written bit */ + SET_FUSEARRAY_BIT(s->fuse_wo, s->pa, s->paio, WRITTEN_BIT_ON); + } + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx @@ -165,6 +190,9 @@ static void sifive_u_otp_reset(DeviceState *dev) /* Make a valid content of serial number */ s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); + + /* Initialize write-once map */ + memset(s->fuse_wo, 0x00, sizeof(s->fuse_wo)); } static void sifive_u_otp_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h index 82c9176c8f..ebffbc1fa5 100644 --- a/include/hw/misc/sifive_u_otp.h +++ b/include/hw/misc/sifive_u_otp.h @@ -36,6 +36,8 @@ #define SIFIVE_U_OTP_PTRIM 0x34 #define SIFIVE_U_OTP_PWE 0x38 +#define SIFIVE_U_OTP_PWE_EN (1 << 0) + #define SIFIVE_U_OTP_PCE_EN (1 << 0) #define SIFIVE_U_OTP_PDSTB_EN (1 << 0) @@ -75,6 +77,7 @@ struct SiFiveUOTPState { uint32_t ptrim; uint32_t pwe; uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + uint32_t fuse_wo[SIFIVE_U_OTP_NUM_FUSES]; /* config */ uint32_t serial; }; -- 2.17.1