From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH] riscv: fu540: dts: Correct reg size of clint node
Date: Tue, 20 Oct 2020 11:03:02 +0530 [thread overview]
Message-ID: <20201020053309.19542-1-pragnesh.patel@sifive.com> (raw)
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index a06e1b11c6..b7cd600b8c 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -62,7 +62,7 @@
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
- reg = <0x0 0x2000000 0x0 0xc0000>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
u-boot,dm-spl;
};
prci: clock-controller at 10000000 {
--
2.17.1
next reply other threads:[~2020-10-20 5:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-20 5:33 Pragnesh Patel [this message]
2020-10-20 6:15 ` [PATCH] riscv: fu540: dts: Correct reg size of clint node Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA47C2AB8@ATCPCS16.andestech.com>
2020-10-21 3:33 ` Rick Chen
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