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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable
Date: Thu, 22 Oct 2020 15:27:05 -0700	[thread overview]
Message-ID: <20201022222709.29386-8-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20201022222709.29386-1-manasi.d.navare@intel.com>

This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  5 ++++
 drivers/gpu/drm/i915/display/intel_vrr.c | 38 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |  2 ++
 3 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 09811be08cfe..391c51979334 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -49,6 +49,7 @@
 #include "intel_sprite.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 
 struct ddi_buf_trans {
 	u32 trans1;	/* balance leg enable, de-emph level */
@@ -4046,6 +4047,10 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
 
 	intel_ddi_enable_transcoder_func(encoder, crtc_state);
 
+	/* Enable VRR if requested through CRTC property */
+	if (crtc_state->vrr.enable)
+		intel_vrr_enable(encoder, crtc_state);
+
 	intel_enable_pipe(crtc_state);
 
 	intel_crtc_vblank_on(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 56114f535f94..7f1353bac583 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -64,3 +64,41 @@ intel_vrr_compute_config(struct intel_dp *intel_dp,
 		 crtc_state->vrr.vtotalmax);
 }
 
+void intel_vrr_enable(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum pipe pipe = crtc->pipe;
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	u32 trans_vrr_ctl = 0, trans_vrr_vmax = 0, trans_vrr_vmin = 0, trans_vrr_flipline = 0, trans_push = 0;
+	u16 framestart_to_pipelinefull_linecnt = 0;
+
+	framestart_to_pipelinefull_linecnt =
+		min_t(u16, 255, (crtc_state->vrr.vtotalmin - adjusted_mode->crtc_vdisplay));
+
+	trans_vrr_ctl = VRR_CTL_VRR_ENABLE |  VRR_CTL_IGN_MAX_SHIFT |
+		VRR_CTL_FLIP_LINE_EN | VRR_CTL_LINE_COUNT(framestart_to_pipelinefull_linecnt) |
+		VRR_CTL_SW_FULLLINE_COUNT;
+
+	/* Programming adjustments for 0 based regs */
+	trans_vrr_vmax = crtc_state->vrr.vtotalmax - 1;
+	trans_vrr_vmin = crtc_state->vrr.vtotalmin - 1;
+	trans_vrr_flipline = crtc_state->vrr.vtotalmin - 1;
+
+	trans_push = TRANS_PUSH_EN;
+
+	intel_de_write(dev_priv, TRANS_VRR_VMIN(pipe), trans_vrr_vmin);
+	intel_de_write(dev_priv, TRANS_VRR_VMAX(pipe), trans_vrr_vmax);
+	intel_de_write(dev_priv, TRANS_VRR_CTL(pipe), trans_vrr_ctl);
+	intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(pipe), trans_vrr_flipline);
+	intel_de_write(dev_priv, TRANS_PUSH(pipe), trans_push);
+
+	drm_dbg(&dev_priv->drm,	"Enabling VRR on pipe (%c)\n", pipe_name(pipe));
+	drm_dbg(&dev_priv->drm, "VRR Parameters: Vblank - Min = %d, Max = %d Flipline Count = %d, CTL Reg = 0x%08x, TRANS PUSH reg = 0x%08x",
+		crtc_state->vrr.vtotalmin, crtc_state->vrr.vtotalmax,
+		crtc_state->vrr.vtotalmin, trans_vrr_ctl,
+		trans_push);
+}
+
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 1e6fe8fe92ec..05d982d6fbae 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -17,5 +17,7 @@ struct intel_dp;
 bool intel_is_vrr_capable(struct drm_connector *connector);
 void intel_vrr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state);
+void intel_vrr_enable(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.19.1

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  parent reply	other threads:[~2020-10-22 22:25 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-22 22:26 [Intel-gfx] [PATCH 00/11] VRR/Adaptive Sync enabling in i915 Manasi Navare
2020-10-22 22:26 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add REG_FIELD_PREP to VRR register def Manasi Navare
2020-11-10 10:13   ` Jani Nikula
2020-12-01 22:41     ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 02/11] drm/i915/display/vrr: Create VRR file and add VRR capability check Manasi Navare
2020-11-10 10:39   ` Jani Nikula
2020-12-01 22:21     ` Navare, Manasi
2020-12-02 22:40       ` Navare, Manasi
2020-12-03 16:35         ` Jani Nikula
2020-12-03 19:38           ` Navare, Manasi
2020-11-10 16:06   ` Ville Syrjälä
2020-11-10 18:48     ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 03/11] drm/i915/display/dp: Attach and set drm connector VRR property Manasi Navare
2020-11-10 10:41   ` Jani Nikula
2020-12-01 22:46     ` Navare, Manasi
2020-12-03 16:37       ` Jani Nikula
2020-12-03 19:37         ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 04/11] drm/i915/display/dp: Add VRR crtc state variables Manasi Navare
2020-11-10 10:41   ` Jani Nikula
2020-12-01 22:49     ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 05/11] drm/i915/display/dp: Compute VRR state in atomic_check Manasi Navare
2020-11-10 10:47   ` Jani Nikula
2020-12-01 22:52     ` Navare, Manasi
2020-12-02 22:38       ` Navare, Manasi
2020-12-03 16:39         ` Jani Nikula
2020-12-03 19:36           ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 06/11] drm/i915/display/dp: Do not enable PSR if VRR is enabled Manasi Navare
2020-10-22 22:27 ` Manasi Navare [this message]
2020-11-10 10:56   ` [Intel-gfx] [PATCH 07/11] drm/i915/display/vrr: Configure and enable VRR in modeset enable Jani Nikula
2020-12-01 22:56     ` Navare, Manasi
2020-12-03 16:40       ` Jani Nikula
2020-10-22 22:27 ` [Intel-gfx] [PATCH 08/11] drm/i915/display/vrr: Send VRR push to flip the frame Manasi Navare
2020-11-10 10:59   ` Jani Nikula
2020-12-01 22:57     ` Navare, Manasi
2020-12-03 19:58       ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 09/11] drm/i915/display/vrr: Disable VRR in modeset disable path Manasi Navare
2020-11-10 11:01   ` Jani Nikula
2020-12-01 22:34     ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 10/11] drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP Sink Manasi Navare
2020-12-01 22:59   ` Navare, Manasi
2020-12-03 16:49     ` Jani Nikula
2020-12-03 19:33       ` Navare, Manasi
2020-10-22 22:27 ` [Intel-gfx] [PATCH 11/11] drm/i915/display: Add HW state readout for VRR Manasi Navare
2020-10-23 17:42   ` [Intel-gfx] [PATCH v2 " Manasi Navare
2020-10-22 22:37 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for VRR/Adaptive Sync enabling in i915 Patchwork
2020-10-23 17:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for VRR/Adaptive Sync enabling in i915 (rev2) Patchwork
2020-10-23 17:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 18:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 21:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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