From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dario Binacchi Date: Sun, 25 Oct 2020 13:40:00 +0100 Subject: [PATCH v5 17/27] omap: timer: fix the rate setting In-Reply-To: <20201025124010.18215-16-dariobin@libero.it> References: <20201025124010.18215-16-dariobin@libero.it> Message-ID: <20201025124010.18215-18-dariobin@libero.it> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The prescaler (PTV) setting must be taken into account even when the timer input clock frequency has been set. Signed-off-by: Dario Binacchi --- (no changes since v1) drivers/timer/omap-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c index 4eecb3e64d..c08cb5ad2e 100644 --- a/drivers/timer/omap-timer.c +++ b/drivers/timer/omap-timer.c @@ -19,8 +19,6 @@ #define TCLR_PRE_EN BIT(5) /* Pre-scaler enable */ #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ -#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) - struct omap_gptimer_regs { unsigned int tidr; /* offset 0x00 */ unsigned char res1[12]; @@ -61,7 +59,9 @@ static int omap_timer_probe(struct udevice *dev) struct omap_timer_priv *priv = dev_get_priv(dev); if (!uc_priv->clock_rate) - uc_priv->clock_rate = TIMER_CLOCK; + uc_priv->clock_rate = V_SCLK; + + uc_priv->clock_rate /= (2 << CONFIG_SYS_PTV); /* start the counter ticking up, reload value on overflow */ writel(0, &priv->regs->tldr); -- 2.17.1